TW201729419A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201729419A
TW201729419A TW105135261A TW105135261A TW201729419A TW 201729419 A TW201729419 A TW 201729419A TW 105135261 A TW105135261 A TW 105135261A TW 105135261 A TW105135261 A TW 105135261A TW 201729419 A TW201729419 A TW 201729419A
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fin
layer
field effect
effect transistor
semiconductor layer
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TW105135261A
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馮家馨
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置被提出。半導體裝置包括形成於一第一半導體層中的一第一鰭片、形成於一第二半導體層中的一第二鰭片以及位於第一鰭片與第二鰭片之間的一絕緣層。第一鰭片、第二鰭片以及絕緣層形成一基板上的堆疊結構。

Description

半導體裝置
本揭露是關於一種半導體裝置。
在半導體結構和製程此二領域的許多發展上，都已對其尺寸的縮減以及積體電路的性能做出了貢獻。其中一個在半導體結構的最新進展是推出了一種被稱為鰭型場效電晶體的電晶體結構。鰭型場效電晶體包括高的深寬比(high-aspect ratio)結構，其可能在蝕刻製程中導致不想要的錐形結構。
本揭露的一實施例的半導體裝置包括一第一鰭片、一第二鰭片以及一絕緣層。第一鰭片形成於一第一半導體層中。第二鰭片形成於一第二半導體層中。絕緣層位於第一鰭片與第二鰭片之間。第一鰭片、第二鰭片以及絕緣層形成一基板上的堆疊結構。
102‧‧‧鰭片
200‧‧‧半導體裝置
200A、354‧‧‧鰭型場效電晶體
104、204、314‧‧‧第一鰭片
106、206、318‧‧‧第二鰭片
208、344‧‧‧絕緣層
210、348‧‧‧金屬閘極
212、346‧‧‧閘極介電層
214、328‧‧‧間隔物
216‧‧‧導電材料
218、350‧‧‧遮罩層
220、352‧‧‧接點
201、301‧‧‧平面
302‧‧‧基板
304a‧‧‧p-位能井
304b‧‧‧n-位能井
306‧‧‧第一半導體層
308‧‧‧中介層
310‧‧‧第二半導體層
312‧‧‧硬遮罩
316‧‧‧條
320‧‧‧矽層
322‧‧‧淺溝槽隔離材料
324‧‧‧犧牲介電質
326‧‧‧犧牲閘極
330‧‧‧凹部
332‧‧‧切條
334‧‧‧矽橋
336‧‧‧源/汲極材料
340‧‧‧絕緣插塞
342‧‧‧空洞
402‧‧‧第一介電層
404‧‧‧第二介電層
406‧‧‧第三介電層
d‧‧‧厚度
閱讀以下詳細敘述並搭配對應之圖式，可了解 本揭露之多個態樣。應注意，根據業界中的標準做法，多個特徵並非按比例繪製。事實上，多個特徵之尺寸可任意增加或減少以利於討論的清晰性。
第1A圖為一種鰭型場效電晶體在蝕刻鰭片之後的範例式鰭片的剖面圖。
第1B圖為依據本揭露的一實施例的一種包括堆疊式鰭片的鰭型場效電晶體結構的剖面圖。
第2A圖與第2B圖為依據本揭露的一實施例的一種鰭型場效電晶體裝置的剖面圖。
第3A圖至第3T圖為依據本揭露的部分實施例的鰭型場效電晶體裝置的製造流程的剖面圖。
第4圖為依據本揭露的一實施例的二堆疊鰭片之間的裝置元件層的剖面圖。
以下揭露提供眾多不同的實施例或範例，用於實施本案提供的主要內容之不同特徵。下文描述一特定範例之組件及配置以簡化本揭露。當然，此範例僅為示意性，且並不擬定限制。舉例而言，以下描述「第一特徵形成在第二特徵之上方或之上」，於實施例中可包括第一特徵與第二特徵直接接觸，且亦可包括在第一特徵與第二特徵之間形成額外特徵使得第一特徵及第二特徵無直接接觸。此外，本揭露可在各範例中重複使用元件符號及/或字母。此重複之目的在於簡化及釐清，且其自身並不規定所討論的各實施例及/或配置之間的關 係。並且，為使說明簡化及明確，不同特徵亦將任意地以不同尺度繪製。
此外，空間相對術語，諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」等等在本文中用於簡化描述，以描述如附圖中所圖示的一個元件或特徵結構與另一元件或特徵結構的關係。除了描繪圖示之方位外，空間相對術語也包含元件在使用中或操作下之不同方位。此裝置可以其他方式定向(旋轉90度或處於其他方位上)，而本案中使用之空間相對描述詞可相應地進行解釋。
在本文中所使用的「FET」縮寫，指的是場效電晶體。一種非常普遍的場效電晶體的類型被被稱為金氧半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor；MOSFET)。歷史性地說，金氧半導體場效電晶體是建構在與一基板的平面表面上的平面結構，基板例如是半導體晶圓。但近來半導體製造業上的進展已經導致垂直結構的使用。
術語「鰭型場效電晶體」指的是一種被形成在鰭片上的場效電晶體，而鰭片被垂直定向在相對於晶圓的平坦表面。
術語「源/汲極(S/D)」指的是形成場效電晶體的四個端子的其中之二的源/汲極接點。
「磊晶層」的表述在此指的是單晶半導體材料的一種層或結構。類似地，「磊晶成長」的表述在此指的是成 長單晶半導體材料的一種層或結構。
「高介電係數(high-k)」的表述在此指的是一高介電常數。在半導體裝置結構和製程的領域中，高介電係數指的是比二氧化矽的介電常數大的介電常數(即大於3.9)。
術語「垂直的」在此指的是名義上垂直於基板的表面。
概述
本揭露的各種實施例提供了一種具有高深寬比的改良輪廓的鰭型場效電晶體裝置。在此內容中，改良輪廓指的是與在習知鰭型場效電晶體裝置中發現的錐面相較之下，鰭型場效電晶體裝置具有較少部分的錐面。
第1A圖為一範例式鰭片102的剖面圖，其已經從大塊基板蝕刻至具有高度h、頂部表面的第一寬度w1以及其底部表面的第二寬度w2。由於高深寬比結構的蝕刻過程，鰭片102具有一個錐形輪廓，導致一個在底部比在頂部大的寬度。在部分例子中，對一約介於40奈米至80奈米之間的高度h而言，頂部和底部的寬度之間的差異(w2-w1)大於4奈米。此錐形輪廓會使得閘極長度小於5奈米或閘極長度小於3奈米的鰭型場效電晶體裝置難以形成。
第1B圖為依據本揭露的一實施例的一種鰭型場效電晶體裝置的鰭狀結構的剖面圖，此鰭型場效電晶體裝置包括在第二鰭片106上圖案化的第一鰭片104。由於蝕刻製程可使用兩道獨立的蝕刻製程來執行，第一鰭片104可以被蝕刻成具有較第二鰭片106更直的側壁。此種結果的整體 結構會包括此二鰭片，其皆在頂部寬度與寬度之間的側壁具有較少部分的錐面。舉例而言，對一約介於40奈米至80奈米之間的高度h而言，頂部和底部的寬度之間的差異(w4-w3)會小於3奈米。
應理解的是，在第1B圖所繪示的鰭狀結構可以包括多於兩個的堆疊鰭片。此外，每個鰭片的個別高度可被調整(意即，每個鰭片的高度並不需要是相同的)。每一個鰭片104、106可以在不同的半導體層進行蝕刻。舉例而言，每一個鰭片104、106在矽層中被蝕刻。
第2A圖與第2B圖為依據本揭露的一實施例的一種具有改良鰭型場效電晶體輪廓的半導體裝置200的剖面圖。第2B圖為通過第2A圖所示的平面201的橫截面。
半導體裝置200包括數個鰭型場效電晶體200A，其中每個鰭型場效電晶體200A包括一第一鰭片204、一第二鰭片206以及一位於第一鰭片204與第二鰭片206之間的絕緣層208。如此一來，依據一實施例，第一鰭片204、第二鰭片206以及絕緣層208會形成基板上的堆疊結構。第一鰭片204和第二鰭片206可由矽被圖案化而形成，而絕緣層208可以是二氧化矽。一個金屬閘極210被沉積在一閘介電層212上，並且具有在金屬閘極210的任一邊上被圖案化的間隔物214。此外，如第2B圖所示，一導電材料216在源/汲極區域中被磊晶成長，以形成相鄰的鰭型場效電晶體裝置的源極或漏極。一接點220被圖案化以與導電材料216電連接。在一實例中，導電材料216包括鍺化矽，而 接點220包括鎢或鋁。亦可提供一遮罩層218，以幫助隔離金屬閘極210與接點220。
藉由形成具有兩個(或更多)的蝕刻鰭片，而不是使用一個蝕刻鰭片，將可減少整體結構的側壁錐面。舉例而言，第一鰭片204的側壁可藉由在反應離子蝕刻第一鰭片204期間時，施加高能量來被拉直。一蝕刻停止層可在第一鰭片204和第二鰭片206之間被圖案化，以作為用於偏壓化第二鰭片206的蝕刻的硬遮罩。對鰭型場效電晶體裝置而言，這些獨立的蝕刻製程的結果是一種改良的整體輪廓。
第3A圖至第3T圖為依據本揭露的實施例的半導體裝置200的製造流程的剖面圖。應當理解的是，未繪示出的其它製造步驟也可被執行。
第3A圖繪示了基板302。基板302可為一矽基板或其他半導體材料。在一個例子中，基板302被摻雜以形成一p-位能井304a與一n-位能井304b。任何標準的摻雜製程，例如等離子體摻雜或離子注入皆可以用於形成摻雜井。當例示的n型摻雜劑包括磷或砷時，例示的p型摻雜劑包括硼。在另一個實施方案中，基板302沒有被摻雜。
第3B圖繪示了位於基板302上的三層結構。此三層結構可以包括一第一半導體層306，一中介層308和一第二半導體層310。在一實施例中，中介層308是能夠與第一半導體層306和第二半導體層310的材料晶格匹配的材料。舉例而言，當中介層308為鍺化矽(SiGe)時，第一半導體層306和第二半導體層310可以為矽。第一半導體層 306、中介層308和第二半導體層310之各者皆可磊晶成長在基板302上。第一半導體層306和第二半導體層310可以各自具有一約介於5奈米與50奈米之間的厚度。中介層308可具有一約介於2奈米至10奈米之間的厚度。
依據一實施例，第3C圖繪示了第3B圖的第二半導體層310的隨後蝕刻製程的結構，其用以形成一個或多個第一鰭片314。一硬遮罩層形成在半導體層310上，並在之後被圖案化以形成硬遮罩312，其在蝕刻製程期間保護其下方的半導體層310的一部分。在一個實施例中，第二半導體層310的蝕刻持續進行到中介層308被暴露出來，而有效地作為一蝕刻停止層。
當半導體層310是矽時，半導體層310可以利用任何熟知的矽蝕刻製程進行蝕刻。舉例而言，可以使用碳基或氟基蝕刻。亦可使用其他的濕化學蝕刻，例如四甲基銨氫氧化物(TMAH)或氫氧化鉀(KOH)。一反應性離子蝕刻(RIE)或深反應離子蝕刻(DRIE)製程，可被用於形成第一鰭片314。依據一實施例，由於中介層308能作為蝕刻停止層的存在，可以施加一高反應性離子蝕刻的能量以建構第一鰭片的更垂直的側壁。
依據一實施例，第3D圖繪示了在第3C圖的中介層308上執行一蝕刻製程後的結構，其包含一第一鰭片314的橫向蝕刻以形成條316。橫向蝕刻的範圍約可介於每邊1奈米至5奈米之間，或是介於每邊1奈米至3奈米之間。任何已知的化學蝕刻可用於蝕刻中介層308。舉例而言，當 中介層308包括鍺化矽時，可以使用氟基、氯基、或溴基等電漿蝕刻。
依據一實施例，第3E圖繪示了在第3D圖的第一半導體層306的隨後蝕刻製程的結構，其用以形成一個或多個第二鰭片318。用以形成第二鰭片318的蝕刻製程可使用類似於用以形成第一鰭片314的化學蝕刻。位於第一鰭片314與第二鰭片318之間的條316可以作為第二鰭片318的蝕刻過程的遮罩層。依據一實施例，第二鰭片318的側壁可比第一鰭片314的側壁更傾斜。
依據一實施例，第3F圖繪示了第3E圖形成了一矽層320的結構。矽層320可使用任何已知的方法，如化學氣相沉積，濺射或磊晶成長來形成。在隨後的製程步驟時，矽層320可用於以保護條316，然而，矽層320的包含與否是可選擇的。
依據一實施例，第3G圖繪示了第3F圖在沉積淺溝槽隔離(shallow-trench isolation；STI)材料322和移除硬遮罩312後的結構。淺溝槽隔離材料322可在沉積之後成為凹部，以使淺溝槽隔離材料322的頂表面低於第二鰭片318的頂表面。淺溝槽隔離材料322可以是任何電性絕緣材料，如二氧化矽。
依據一實施例，第3H圖繪示了第3G圖在沉積犧牲介電質324和犧牲閘極326後的結構。犧牲介電質324可以是二氧化矽，或者可以絕緣層，諸如氧化物、氮化物、氧化物(ONO)的堆疊形式出現。犧牲閘極326可以是多晶 矽。一種化學機械研磨(chemical-mechanical polishing；CMP)製程可以被執行，以平面化犧牲閘極326的頂表面。
第31圖繪示了通過平面301所取的第二橫截面圖，以更好地可視化其餘的製造步驟。間隔物328可藉由一異向性回蝕製程後的沉積而設置在犧牲閘極326的兩側。間隔物328可以是氮化矽，二氧化矽，或相對於多晶矽而言，具有高蝕刻選擇性的任何其他絕緣材料。
在間隔物328被設置前，第一鰭片314和第二鰭片318可使用犧牲閘極326作為遮罩而是p摻雜的(以形成一個p通道型鰭型場效電晶體)或是n摻雜的(以形成一個n通道鰭型場效電晶體)。
依據一個實施例，凹部330可經由蝕刻第一鰭片314和第二鰭片318，以創建源極/汲極(S/D)區域。間隔物328可以提供凹部330蝕刻過程的遮罩。凹部330可經由蝕刻第一鰭片314、條316和第二鰭片318的堆疊而形成。
第3J圖繪示了在條316上進行的額外的橫向蝕刻製程，以形成切條332。條316的蝕刻製程可以使用類似於蝕刻中介層308的蝕刻製程。
依據一實施例，第3K圖繪示了矽橋334在圍繞底切條332的暴露邊緣的磊晶成長。矽橋334在圍繞底切條332的側面連接第一鰭片314至第二鰭片318。
第3L圖繪示了在凹部330內的源/汲極材料336的沉積。源/汲極材料336可以包括鍺化矽，並作為每個相 鄰鰭型場效電晶體裝置的源極或汲極。源/汲極材料336可以與n型摻雜劑或p型摻雜劑進行摻雜。舉例而言，源/汲極材料336可包括摻雜磷的矽(n摻雜)或摻雜硼的鍺化矽(p摻雜)。在一實施例中，源/汲極材料336完全填充凹部330。
依據一實施例，第3M圖與第3N圖繪示了犧牲閘極326和犧牲介電質324的移除。可選擇地是，一個絕緣插塞340可以被沉積在鄰近鰭型場效電晶體裝置之間的源/汲極材料336上。絕緣插塞340可以包括二氧化矽，且具有利用化學機械研磨製程而平坦化的頂表面。
依據一實施例，第3O圖與第3P圖繪示了切條332的移除，其在第一鰭片314和第二鰭片318之間留下空洞342。第一鰭片314和第二鰭片318經由矽橋334連接。一化學蝕刻可用來選擇性地去除切條332，且對第一鰭片314和第二鰭片318提供很少或幾乎沒有的蝕刻過程。
依據一實施例，第3Q圖與第3R圖繪示了絕緣層344和金屬閘極348的形成。絕緣層344可包括二氧化矽，並且可以填充第一鰭片314和第二鰭片318之間的空洞342。相同二氧化矽的沉積也可形成在金屬閘極348下方的閘介電質346。在另一例子中，一個單獨的沉積步驟被執行以形成閘介電質346。絕緣層344可以絕緣層堆疊的形式出現，如二氧化矽和高介電係數介電質的疊層，或二氧化矽、高介電係數介電質和氮化鈦的疊層。金屬閘極348可填充在移除犧牲閘極326後所留下來的區域。金屬閘極348的頂表面可利用化學機械研磨製程而平坦化。
依據一實施例，第3S圖與第3T圖繪示了接點352的形成，以使其與源/汲極材料336電性接連接。一遮罩層350可以先沉積以保護金屬閘極348而免於與接點352形成短路。接點352可以是金屬接點，如鎢或鋁。
如此而得的鰭型場效電晶體裝置354包括了一第一鰭片314、一絕緣層344以及一第二鰭片318的堆疊結構。經由平面301所取的橫截面還繪示了源/汲極材料336如何被佈置在鰭型場效電晶體裝置的兩側上，以形成其源/汲極區域。依據一實施例，第一鰭片314的一頂部寬度與第二鰭片318的一底部寬度的差異小於3奈米。
如上所述，依據一實施例，中介層308的厚度設置了每個鰭型場效電晶體裝置內的第一鰭片314和第二鰭片318之間的間隙。一旦該層被移除，留下的空洞會被介電層填充，其也形成鰭型場效電晶體裝置的閘介電質。此間隙距離可有助於描述存在於第一鰭片314和第二鰭片318之間的空間的介電層。
第4圖為第一鰭片314和第二鰭片318之間的具有間隙厚度d的空間的剖面圖。當間隙厚度d約介於6至8奈米之間時，可在間隙內沉積一個以上的介電層。舉例而言，此間隙可被一第一介電層402、一第二介電層404和一第三介電層406填充。第一介電層402可以與絕緣層344相同，且其可以是二氧化矽。第二介電層404可以是高介電係數介電材料。第三介電層406可以是氮化鈦。對於具有小厚度d的間隙，可存在較少的層。舉例而言，約介於3至5奈米之 間的間隙距離可以僅包括第一介電層402和第二介電層404。約小於3奈米的間隙距離可以僅包括第一介電層402。在另一實施例中，第一介電層402被沉積足夠厚到充滿第一鰭片314和第二鰭片318之間的間隙，即使該間隙約大於3奈米以上。
在一實施例中，一種半導體裝置包括形成於一第一半導體層中的一第一鰭片、形成於一第二半導體層中的一第二鰭片以及位於第一鰭片與第二鰭片之間的一絕緣層。第一鰭片、第二鰭片以及絕緣層形成一基板上的堆疊結構。
第一半導體層與第二半導體層包含矽，且第一鰭片與第二鰭片可經由一或多個沿絕緣層的側邊而形成的矽橋連接。
在另一實施例中，一種半導體裝置的製造方法包括蝕刻一第一半導體層以形成一第一鰭片、蝕刻一被提供在第一半導體層下方的中介層以及蝕刻一第二半導體層以形成一第二鰭片。中介層的蝕刻過程為橫向蝕刻在第一鰭片下方的中介層。第一鰭片、第二鰭片以及中介層形成一基板上的堆疊結構。
在第一半導體層的蝕刻與第二半導體層的蝕刻後，第一鰭片的側壁相較於第二鰭片的側壁更為垂直地排列。在另一實施例中，第一半導體層與第二半導體層為摻雜矽，且此製造方法也包括形成矽橋，矽橋沿中介層的側邊連接第一鰭片與第二鰭片。此製造方法更包括移除中介層，並以一絕緣層取代，其中中介層包含鍺化矽和絕緣層包含二氧化矽。
應了解實施方式的部分僅用於解釋申請專利範圍。而摘要部分僅描述一個或多個實施例，且並非發明人所思忖之全部實施例，因此並不用於限制本揭露以及申請專利範圍。
上文概述了若干實施例的特徵，以便本領域熟習此項技藝者可更好地理解本揭露的態樣。本領域熟習此項技藝者應當瞭解到他們可容易地使用本揭露作為基礎來設計或者修改其他製程及結構，以實行相同目的及/或實現相同優勢的。本領域熟習此項技藝者亦應當瞭解到，此類等效構造不脫離本揭露的精神及範疇，以及在不脫離本揭露的精神及範疇的情況下，其可對本文進行各種改變、取代及變更。
本揭露的廣度和範圍不應受任何上述示例性的實施例限制，而應僅根據下面的申請專利範圍及其等效範圍來限定。
200‧‧‧半導體裝置
200A‧‧‧鰭型場效電晶體
204‧‧‧第一鰭片
206‧‧‧第二鰭片
208‧‧‧絕緣層
210‧‧‧金屬閘極
212‧‧‧閘極介電層
218‧‧‧遮罩層
201‧‧‧平面

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  1. 一種半導體裝置，包括：一第一鰭片，形成於一第一半導體層中；一第二鰭片，形成於一第二半導體層中；以及一絕緣層，位於該第一鰭片與該第二鰭片之間，以使該第一鰭片、該第二鰭片以及該絕緣層形成一基板上的堆疊結構。
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