CN104576378A - 一种mosfet结构及其制造方法 - Google Patents

一种mosfet结构及其制造方法 Download PDF

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CN104576378A
CN104576378A CN201310476543.6A CN201310476543A CN104576378A CN 104576378 A CN104576378 A CN 104576378A CN 201310476543 A CN201310476543 A CN 201310476543A CN 104576378 A CN104576378 A CN 104576378A
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semiconductor layer
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尹海洲
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Institute of Microelectronics of CAS
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Abstract

本发明提供一种MOSFET结构及其制造方法，其中该方法包括：a.提供衬底(100)；b.在衬底上形成硅锗沟道层(101)、伪栅叠层(200)和牺牲侧墙(102)；c.去除未被伪栅叠层(200)覆盖的以及位于伪栅叠层(200)两侧下方的硅锗沟道层(101)和部分衬底(100)，形成空位(201)；d.在所述半导体结构上选择性外延生长第一半导体层(300)以填充空位(201)的底部和侧壁区域；e.去除牺牲侧墙(102)，在未被第一半导体层(300)填充的空位(201)中填充第二半导体层(400)。本发明方法所制备的半导体结构能够提高沟道中的载流子迁移率，有效地抑制了短沟道效应的不良影响，提高了器件性能。

Description

一种MOSFET结构及其制造方法
技术领域
本发明涉及一种MOSFET结构及其制造方法。更具体而言，涉及一种用于降低关态漏电流的MOSFET结构及其制造方法。
技术背景
随着器件越来越薄，器件关态时由带带隧穿引发的栅致漏极泄漏(GIDL)电流越来越大，它已经成为严重限制MOSFET以及FLASH存储器的问题之一。GIDL电流本身便引入了热空穴注入，它使得空穴陷落在栅氧化层中从而导致器件的不稳定性以及能导致栅氧层击穿。因此随着氧化层厚度的减小，关态氧化层的可靠性将会越来越重要，此方面已经引发了越来越多的关注。
减小GIDL的常规技术是提高栅氧化层形成的温度到大约1000℃到1100℃。提高氧化温度主要是较少衬底的表面态密度，以减少GIDL。现在的主流工艺主要是通过快速热氧化作用工艺(RTO)和现场水汽生成工艺(In-situ steam generation，ISSG)来生长栅氧化层。但是RTO比用氧化炉的氧化作用会导致栅氧化层更差的均匀性，这种不均匀导致器件的阈值电压变化大，这是不希望的；此外利用ISSG生长氧化层，随着器件尺寸的缩小到55nm制程以下，对GIDL电流减小的控制能力也逐渐减低。
另一种减小GIDL的技术是减小轻掺杂漏区(LDD)的浓度。由于器件尺寸减少，短沟道效应成为日渐严重的问题。LDD的主要目的是为了这种抑制短沟道效应。为了降低短沟道效应，LDD必须采用超浅结。但是为了避免驱动电流的降低，LDD的浓度也日益增强。如果采用一味降低LDD浓度的方法来减小GIDL电流，就会增加沟道区电阻，同时降低了驱动电流，让器件的性能变差。因此，一味地用减小LDD的浓度来降低GIDL电流对未来的集成电路(IC)器件也是不可取的。
因此，如何提供一种可有效减小MOS器件GIDL电流的MOS管制作方法，已成为业界亟待解决的技术问题。
发明内容
本发明提供了一种有效减小MOS器件GIDL电流的MOS管制作方法，有效抑制了器件的短沟道效应，提高了器件性能。具体地，本发明提供的制造方法包括以下步骤：
一种MOSFET制造方法，包括：
a.提供衬底；
b.在衬底上形成硅锗沟道层、伪栅叠层和牺牲侧墙；
c.去除未被伪栅叠层覆盖的以及位于伪栅叠层两侧下方的硅锗沟道层和部分衬底，形成空位；
d.在所述半导体结构上选择性外延生长第一半导体层以填充空位的底部和侧壁区域；
e.去除牺牲侧墙，在未被硅填充的空位中填充第二半导体层。
其中，所述硅锗沟道层的厚度为3～6nm。
其中，形成所述空位的方法是各向异性刻蚀和各向同性刻蚀的组合。其中，所述空位与伪栅叠层重叠的长度H为5～10nm。
其中，所述第一半导体层的禁带宽度大于所述硅锗沟道层的禁带宽度，第一半导体层的材料是硅，所述第二半导体层的材料为硅或硅锗。其中，所述第二半导体层的材料为硅锗时，所述硅锗中锗所占的比例小于硅锗沟道层中锗所占的比例。
其中，所述第二半导体层的填充方法为外延生长或化学汽相淀积。
其中，在步骤e之后还包括步骤：
f.在所述半导体结构上依次形成源漏扩展区、侧墙、源漏区以及层间介质层；
g.去除伪栅叠层以形成伪栅空位，在所述伪栅空位中依次沉积栅极介质层、功函数调节层和栅极金属层。
相应的，本发明还提供了一种MOSFET结构，包括：衬底、位于所述衬底上方的硅锗沟道层、位于所述硅锗沟道层上方的栅极叠层、位于栅极叠层两侧的衬底中的第一半导体层和第二半导体层、位于所述第一半导体层和第二半导体层中的源漏扩展区和源漏区、覆盖所述栅极叠层和所述源漏区的层间介质层，其中，
构成所述第一半导体层的材料禁带宽度大于所述硅锗沟道层的禁带宽度。
其中，所述第一半导体层位于栅极叠层边缘下方，其与栅极叠层相重叠的截面长度的最大值H大于源漏扩展区的长度L。
其中，所述硅锗沟道层的厚度为3～6nm。
其中，所述第一半导体层与栅极叠层相重叠的截面长度H为5～10nm。
其中，所述第二半导体层的半导体材料为硅或硅锗；
所述第二半导体层为硅锗时，其中锗所占的比例小于硅锗沟道层中锗所占的比例。
根据本发明提供的MOS晶体管结构，采用禁带宽度较大的半导体材料替换漏端附近的沟道材料，即GIDL效应作用的区域，有效地减小了由GIDL效应所引起的漏电流。同时，采用禁带宽度较大的半导体材料填充源漏区，可对沟道区产生相应的应力，提高沟道中的载流子迁移率。与现有技术相比，本发明有效地抑制了短沟道效应的不良影响，提高了器件性能。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1～图8为根据本发明的一个具体实施方式中MOSFET各个制造阶段的剖面图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
本发明提供了一种MOSFET结构，包括：半导体层100、硅锗沟道层101、第一半导体层300、第二半导体层400、源漏扩展区210、源漏区202、层间介质层500以及栅极叠层600，其中，构成所述第一半导体层300的材料禁带宽度大于所述硅锗沟道层101的禁带宽度。
所述第一半导体层300位于栅极叠层600边缘下方，其与栅极叠层相重叠的截面厚度的最大值H大于源漏扩展区210的长度L，所述硅锗沟道层101的厚度为3～6nm，所述第一半导体层300的厚度为5～10nm。
所述半导体材料400为硅或硅锗，所述硅锗中锗所占的比例小于硅锗沟道层101中锗所占的比例。
半导体沟道区位于衬底的表面，其优选材料为单晶硅或单晶锗合金薄膜，其厚度为5～20nm。该区域是极轻掺杂甚至未掺杂的。在掺杂的情况下，其掺杂类型与源漏区掺杂相反。
源区和漏区分别位于栅极叠层600两侧，衬底上方的半导体层内。源区的厚度大于漏区的厚度。靠近源区一侧的沟道部分厚度大于靠近漏端一侧的沟道厚度，为10nm～60nm。
下面结合附图对本发明的制作方法进行详细说明，包括以下步骤。需要说明的是，本发明各个实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
参见图1，首先在衬底上形成硅锗沟道101。所述硅锗沟道的厚度不超过6nm。具体的，可采用原子层沉积(ALD)形成所述硅锗沟道101，通过控制反应原子的比例可以调节硅锗沟道101中锗的的百分比。
接下来，在所述衬底100上形成伪栅结构200。所述伪栅结构200可以是单层的，也可以是多层的。伪栅结构200可以包括聚合物材料、非晶硅、多晶硅或TiN，厚度可以为10nm～200nm。本实施例中，伪栅结构包括多晶硅和二氧化，具体的，采用化学汽相淀积的方法在栅极空位中填充多晶硅，其高度略低于侧墙10～20nm，接着在多晶硅上方形成一层二氧化硅介质层，形成方法可以是外延生长、氧化、CVD等。接着采用常规CMOS工艺光刻和刻蚀所淀积的伪栅叠层形成栅电极图形。硅锗沟道层101中被栅极介质层所覆盖的部分形成晶体管的沟道区。需说明地是，以下若无特别说明，本发明实施例中各种介质材料的淀积均可采用上述所列举的形成栅介质层相同或类似的方法，故不再赘述。
可选地，在栅极堆叠的侧壁上形成牺牲侧墙102，用于将栅极隔开，如图1所示。具体的，用LPCVD淀积40nm～80nm厚的牺牲侧墙介质层氮化硅，接着用会客技术再栅电极两侧形成宽度为35nm～75nm的氮化硅牺牲侧墙102。牺牲侧墙102还可以由氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。牺牲侧墙102可以具有多层结构。牺牲侧墙102还可以通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm-100nm，如30nm、50nm或80nm。
接下来，去除未被伪栅叠层200覆盖的以及位于伪栅叠层200两侧下方的硅锗沟道层101和部分衬底100，硅锗沟道层101和部分衬底100，形成空位201，如图2所示。具体的，以伪栅叠层200和牺牲侧墙102为掩膜，对所述半导体结构进行各向异性刻蚀，刻蚀方法一般为干法刻蚀，刻蚀深度所需空位201深度的1/3至1/2。之后，在形成的空位内部采用各向同性刻蚀，去除位于伪栅叠层200两侧下方的硅锗沟道层101和部分衬底100。刻蚀完成之后，在所述半导体结构上形成空位201，空位201位于伪栅叠层200两侧，其与伪栅叠层200重叠的长度H为5～10nm。
接下来，在所述半导体结构上选择性外延生长第一半导体层300以填充空位201的底部和侧壁区域。具体的，在暴露处的空位201表面生长第一半导体材料300，所述第一半导体层300的禁带宽度大于所述硅锗沟道层101的禁带宽度。由于GIDL产生的漏电流大小与该区域内的半导体材料禁带宽度大小密切相关，且随着材料禁带宽度的增大而减小，因此，采用禁带宽度较大第一半导体材料300替换原沟道材料硅锗，可有效增大GIDL区域的材料禁带宽度，从而减小漏电流，优化器件性能。在本实施例中，优选的，采用硅作为第一半导体层300的材料进行外延生长，直至生长出的硅层与伪栅结构200边界处平齐时，停止生长。生长完成的半导体结构如图3所示。
接下来，去除牺牲侧墙102，在未被硅300填充的空位201中填充第二半导体层400，所述第二半导体层400的材料为硅或硅锗，并且所述硅锗中锗所占的比例小于硅锗沟道层101中锗所占的比例。具体的，去除所述学生侧墙102的方法可以采用湿法刻蚀，所述第二半导体层400的填充方法可以为外延生长或化学汽相淀积。由于所述第二半导体层400中锗的比例大于硅锗沟道层101中锗所占的比例，其具有更大的禁带宽度，由于晶格不匹配，第二半导体层400将会对硅锗沟道层101产生应力，从而增大沟道中载流子的迁移率，进一步提高器件性能。在本实施例中，优选的，采用硅作为第二半导体层400的材料。完成之后的半导体结构剖面图如图4所示。
接下来，对伪栅结构200两侧的衬底进行掺杂，以形成源漏扩展区，还可以进行Halo注入，以形成Halo注入区。其中源漏扩展区的杂质类型与器件类型一致，Halo注入的杂质类型与器件类型相反。
可选地，在栅极堆叠的侧壁上形成侧墙401，用于将栅极隔开，如图6所示。具体的，用LPCVD淀积40nm～80nm厚的牺牲侧墙介质层氮化硅，接着用会客技术再栅电极两侧形成宽度为35nm～75nm的氮化硅牺牲侧墙102。牺牲侧墙102还可以由氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。牺牲侧墙102可以具有多层结构。牺牲侧墙102还可以通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm-100nm，如30nm、50nm或80nm。
接下来，在所述半导体结构上淀积一层厚度为10nm～35nm厚的二氧化硅介质层，并以该介质层为缓冲层，离子注入源漏区。对P型晶体而言，掺杂剂为硼或弗化硼或铟或镓等。对N型晶体而言，掺杂剂为磷或砷或锑等。掺杂浓度为5e1019cm-3～1e1020cm-3。源漏区掺杂完成后，在所述半导体结构上形成层间介质层500。在本实施例中，层间介质层500的材料为二氧化硅。淀积完层间介质层500的半导体结构如图7所示。
接下来，去除所述伪栅结构200，形成伪栅空位。去除伪栅结构200可以采用湿刻和/或干刻除去。在一个实施例中，采用等离子体刻蚀。
接下来，如图8所示，在栅极空位中形成栅极叠层。栅极叠层可以只为金属栅极，也可以为金属/多晶硅复合栅极，其中多晶硅上表面上具有硅化物。
具体的，优选的，在伪栅空位中栅极介质层601，接下来沉积功函数调节层602，之后再在功函数金属层之上形成栅极金属层603。所述栅极介质层601可以是热氧化层，包括氧化硅、氮氧化硅；也可为高K介质，例如HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON、A12O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅极介质层601的厚度可以为1nm-10nm，例如3nm、5nm或8nm。可以采用热氧化、化学气相沉积(CVD)或原子层沉积(ALD)等工艺来形成栅极介质层601。
功函数金属层可以采用TiN、TaN等材料制成，其厚度范围为3nm～15nm。金属导体层可以为一层或者多层结构。其材料可以为TaN、TaC、TiN、TaAlN、TiAlN、MoAlN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合。其厚度范围例如可以为10nm-40nm，如20nm或30nm。
最后进入常规CMOS厚道工艺，包括点击钝化层、开接触孔以及金属化等，即可制的所述超薄SOI MOS晶体管。
由于GIDL产生的漏电流大小与该区域内的半导体材料禁带宽度大小密切相关，且随着材料禁带宽度的增大而减小，因此，采用禁带宽度较大第一半导体材料300替换原沟道材料硅锗，可有效增大GIDL区域的材料禁带宽度，从而减小漏电流，优化器件性能。同时，由于所述第二半导体层400中锗的比例大于硅锗沟道层101中锗所占的比例，其具有更大的禁带宽度，由于晶格不匹配，第二半导体层400将会对硅锗沟道层101产生应力，从而增大沟道中载流子的迁移率，进一步提高器件性能。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (16)

1.一种MOSFET制造方法，包括：
a.提供衬底(100)；
b.在衬底上形成硅锗沟道层(101)、伪栅叠层(200)和牺牲侧墙(102)；
c.去除未被伪栅叠层(200)覆盖的以及位于伪栅叠层(200)两侧下方的硅锗沟道层(101)和部分衬底(100)，形成空位(201)；
d.在所述半导体结构上选择性外延生长第一半导体层(300)以填充空位(201)的底部和侧壁区域；
e.去除牺牲侧墙(102)，在未被第一半导体层(300)填充的空位(201)中填充第二半导体层(400)。
2.根据权利要求1所述的制造方法，其特征在于，所述硅锗沟道层(101)的厚度为3～6nm。
3.根据权利要求1所述的制造方法，其特征在于，形成所述空位(201)的方法是各向异性刻蚀和各向同性刻蚀的组合。
4.根据权利要求1所述的制造方法，其特征在于，所述空位(201)与伪栅叠层(200)重叠的长度H为5～10nm。
5.根据权利要求1所述的制造方法，其特征在于，所述第一半导体层(300)的禁带宽度大于所述硅锗沟道层(101)的禁带宽度。
6.根据权利要求1或5所述的制造方法，其特征在于，所述第一半导体层(300)的材料是硅。
7.根据权利要求1所述的制造方法，其特征在于，所述第二半导体层(400)的材料为硅或硅锗。
8.根据权利要求7所述的制造方法，其特征在于，所述第二半导体层(400)为硅锗时，其中锗所占的比例小于硅锗沟道层(101)中锗所占的比例。
9.根据权利要求1所述的制造方法，其特征在于，所述第二半导体层(400)的填充方法为外延生长或化学汽相淀积。
10.根据权利要求1所述的制造方法，其特征在于，在步骤e之后还包括步骤：
f.在所述半导体结构上依次形成源漏扩展区、侧墙(401)、源漏区以及层间介质层(500)；
g.去除伪栅叠层(200)以形成伪栅空位，在所述伪栅空位中依次沉积栅极介质层(601)、功函数调节层(602)和栅极金属层(603)。
11.一种MOSFET结构，包括：衬底(100)、位于所述衬底(100)上方的硅锗沟道层(101)、位于所述硅锗沟道层(101)上方的栅极叠层(600)、位于栅极叠层(600)两侧的衬底中的第一半导体层(300)和第二半导体层(400)、位于所述第一半导体层(300)和第二半导体层(400)中的源漏扩展区(210)和源漏区(202)、覆盖所述栅极叠层(600)和所述源漏区(202)的层间介质层(500)，其中，
构成所述第一半导体层(300)的材料禁带宽度大于所述硅锗沟道层(101)的禁带宽度。
12.根据权利要求11所述的制造方法，其特征在于，所述第一半导体层(300)位于栅极叠层(600)边缘下方，其与栅极叠层相重叠的截面长度的最大值H大于源漏扩展区(201)的长度L。
13.根据权利要求11所述的制造方法，其特征在于，所述硅锗沟道层(101)的厚度为3～6nm。
14.根据权利要求11或12所述的制造方法，其特征在于，所述第一半导体层(300)的长度H为5～10nm。
15.根据权利要求11所述的制造方法，其特征在于，所述第二半导体层(400)的半导体材料为硅或硅锗。
16.根据权利要求15所述的制造方法，其特征在于，所述第二半导体层(400)为硅锗时，其中锗所占的比例小于硅锗沟道层(101)中锗所占的比例。
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