CN104576338B - 一种mosfet结构及其制造方法 - Google Patents

一种mosfet结构及其制造方法 Download PDF

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CN104576338B
CN104576338B CN201310476462.6A CN201310476462A CN104576338B CN 104576338 B CN104576338 B CN 104576338B CN 201310476462 A CN201310476462 A CN 201310476462A CN 104576338 B CN104576338 B CN 104576338B
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尹海洲
李睿
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Institute of Microelectronics of CAS
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Abstract

本发明提供一种MOSFET及其制造方法，其中所述方法包括：a.提供衬底（100）、伪栅空位、第一侧墙（150）、源漏扩展区（205）、源漏区（200）和层间介质层（300）；b.在所述伪栅空位中的衬底上形成二氧化硅层（160）；c.在所述半导体材料上淀积栅极介质层(400)；d.在所述伪栅空位形成第二侧墙（450），所述第二侧墙（450）紧邻栅极介质层（400），与层间介质层（300）平齐；e.在所述伪栅空位中形成栅极叠层（500）。本发明有效地避免了栅极下方的氧化层厚度不均所引起的各种不良效应，优化了器件性能。

Description

一种MOSFET结构及其制造方法
技术领域
本发明涉及一种MOSFET结构及其制造方法。更具体而言，涉及一种用于优化栅极结构以改善器件性能的MOSFET结构及其制造方法。
技术背景
在MOSFET中，为了尽可能的优化器件性能，其栅极叠层一般由栅极介质层和功函数调节层组成。同时，为了改善栅极介质层和沟道材料之间的界面性能，通常在形成栅极介质层之前，先在沟道上方形成一层薄氧化层以消除沟道表面的界面态。现有技术中，对于硅衬底的器件，多采用直接氧化的方式形成所述二氧化硅层，但是由于热氧化生长是以衬底的硅为材料氧化生成二氧化硅，在沟道两端边界处，由于侧墙的阻挡，侧墙下方的硅并不能被氧化，因此两侧的二氧化硅层会比沟道中部的二氧化硅层薄，越靠近侧墙处，氧化层越薄，氧化层在靠近沟道两端的地方是斜坡状的而非平坦的。这一现象使得随后淀积在氧化层上的栅极介质层和功函数调节层都出现了一定程度的倾斜，在靠近侧墙的地方形成尖峰。而这种尖峰的存在，在器件工作时会影响电场的分布，尖峰处的电场线会较别处密集，引起电流集边效应等一些列不良影响。
针对这一问题，本发明提出了一种用于优化栅极结构以改善器件性能的MOSFET结构及其制造方法。具体的，本发明在位于沟道上方第一侧墙的侧壁方向上的氧化层与栅极介质层之间形成了第二侧墙，所述第二侧墙的宽度为3～7nm，覆盖了二氧化硅层边界处的斜坡区域，有效地避免了栅极下方的氧化层厚度不均所引起的各种不良效应，优化了器件性能。
发明内容
本发明提供了一种用于优化栅极结构以改善器件性能的MOSFET结构及其制造方法。具体的，本发明提供的制造一种MOSFET制造方法，包括：
a.提供衬底、伪栅空位、第一侧墙、源漏扩展区、源漏区和层间介质层；
b.在所述伪栅空位中的衬底上形成二氧化硅层；
c.在所述半导体材料上淀积栅极介质层；
d.在所述伪栅空位形成第二侧墙，所述第二侧墙紧邻栅极介质层，与层间介质层平齐；
e.在所述伪栅空位中形成栅极叠层。
其中，所述源漏扩展区的边界延伸至二氧化硅层下方，二者重叠的部分长度大于或等于第二侧墙的宽度与栅极介质层的厚度之和；
其中，形成所述源漏扩展区的方法为向着栅极叠层方向倾斜的离子注入；
其中，所述第二侧墙的宽度为3～7nm。
本发明还提供一种半导体结构，包括：
衬底；
形成于所述衬底之上二氧化硅层；
形成于所述二氧化硅层上方的栅极叠层；
形成于所述栅极叠层两侧并且在衬底之上的第一侧墙；
形成于所述栅极叠层两侧并且在衬底中的源漏区；
形成于所述栅极叠层下方并且在衬底中的源漏扩展区；
其中还包括：
栅极介质层，其位于所述栅极叠层与二氧化硅层之间，以及所述第一侧墙的内壁上；
第二侧墙，其位于与所述第一侧墙相邻接部分所述栅极介质层与所述栅极叠层之间并且位于所述二氧化硅层上方。
其中，所述源漏扩展区的边界延伸至二氧化硅层下方，二者重叠的部分长度大于等于第二侧墙的宽度与栅极介质层的厚度之和；
其中所述第二侧墙的宽度为3～7nm。
根据本发明提出的一种用于优化栅极结构以改善器件性能的MOSFET结构及其制造方法，具体的，本发明在位于沟道上方第一侧墙的侧壁方向上的氧化层与栅极介质层之间形成了第二侧墙，所述第二侧墙所述第二侧墙的宽度为3～7nm，覆盖了二氧化硅层边界处的斜坡区域，有效地避免了栅极下方的氧化层厚度不均所引起的各种不良效应，优化了器件性能。
附图说明
图1至图7示意性地示出了形成根据本发明的制造方法各阶段半导体结构的剖面图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
参见图7，本发明提供了一种半导体结构，包括：
衬底100；
形成于所述衬底100之上二氧化硅层160；
形成于所述二氧化硅层160上方的栅极叠层500；
形成于所述栅极叠层500两侧并且在衬底100之上的第一侧墙150；
形成于所述栅极叠层500两侧并且在衬底100中的源漏区200；
形成于所述栅极叠层500下方并且在衬底100中的源漏扩展区205；
其中还包括：
栅极介质层400，其位于所述栅极叠层500与二氧化硅层160之间，以及所述第一侧墙150的内壁上；
第二侧墙450，其位于与所述第一侧墙150相邻接部分所述栅极介质层400与所述栅极叠层500之间并且位于所述二氧化硅层160上方。
栅极叠层包括功函数调节层和栅极金属层。栅极金属层可以只为金属栅极，也可以为金属/多晶硅复合栅极，其中多晶硅上表面上具有硅化物。栅介质层优选材料为氮氧化硅，也可为氧化硅或高K材料。其等效氧化厚度为0.5nm～5nm。
半导体沟道区位于衬底100的表面，其优选材料为单晶硅，其厚度为2～20nm。该区域是极轻掺杂甚至未掺杂的。在掺杂的情况下，其掺杂类型与源漏区掺杂相反。
源区和漏区分别位于栅极叠层两侧，衬底100内。源区与漏区相对称，其掺杂类型与衬底相反。
源漏扩展区205的边界延伸至二氧化硅层160下方，二者重叠的部分长度大于等于第二侧墙450的宽度与栅极介质层400的厚度之和。
通常形成二氧化硅层160时，其与第一侧墙150相接的边界处存在斜坡区域，如果直接在所述二氧化硅层上形成栅极，则栅极下方的二氧化硅层160厚度不均所引起的各种不良效应，例如电流集边效应，以及边界处氧化层过薄会导致热载流子穿越该二氧化硅层160，在栅极介质中引入缺陷。
本发明通过在所述二氧化硅层160与第一侧墙150交界处的上方形成第二侧墙，其宽度例如为3～7nm，覆盖了二氧化硅层边界处的斜坡区域，有效地避免了栅极下方的氧化层厚度不均所引起的各种不良效应，优化了器件性能。
下面结合附图对本发明的制作方法进行详细说明，包括以下步骤。需要说明的是，本发明各个实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
首先提供衬底，并在所述衬底上形成伪栅结构101。所述伪栅结构101可以是单层的，也可以是多层的。伪栅结构101可以包括聚合物材料、非晶硅、多晶硅或TiN，厚度可以为10nm～200nm。本实施例中，伪栅结构包括多晶硅和二氧化，具体的，采用化学汽相淀积的方法在栅极空位中填充多晶硅，接着在多晶硅上方形成一层二氧化硅介质层，形成方法可以是外延生长、氧化、CVD等。接着采用常规CMOS工艺光刻和刻蚀所淀积的伪栅叠层形成栅电极图形，然后以栅电极图形为掩膜腐蚀掉栅极介质层的裸露部分。需说明地是，以下若无特别说明，本发明实施例中各种介质材料的淀积均可采用上述所列举的形成栅介质层相同或类似的方法，故不再赘述。
接下来，对伪栅结构两侧的衬底100进行浅掺杂，以形成源漏扩展区205，还可以进行Halo注入，以形成Halo注入区。其中源漏扩展区205的杂质类型与器件类型一致，Halo注入的杂质类型与器件类型相反。具体的，形成所述源漏扩展区205的方法为倾斜的离子注入，如图1所示，使得所述源漏扩展区205的边界延伸至伪栅空位下方。
接下来，在栅极堆叠的侧壁上形成第一侧墙150，用于将栅极隔开。具体的，用LPCVD淀积40nm～80nm厚的牺牲侧墙介质层氮化硅，接着用会客技术在栅极两侧形成宽度为35nm～75nm的氮化硅的第一侧墙150。第一侧墙150还可以由氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。第一侧墙150可以具有多层结构。第一侧墙150还可以通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm-100nm，如30nm、50nm或80nm。
接下来，在所述半导体结构上淀积一层厚度为10nm～35nm厚的二氧化硅介质层，形成层间介质层300，并以该介质层为缓冲层，离子注入源漏区。对P型晶体而言，掺杂剂为硼或弗化硼或铟或镓等。对N型晶体而言，掺杂剂为磷或砷或锑等。掺杂浓度为5e1019cm-3～1e1020cm-3。完成掺杂之后的半导体结构如图2所示。
接下来，去除所述伪栅结构，形成伪栅空位，如图3所示。去除伪栅结构可以采用湿刻和/或干刻除去。在一个实施例中，采用等离子体刻蚀。
接下来，在伪栅空位中的沟道表面形成二氧化硅层160，如图4所示。具体的，可采用干氧氧化的方法形成所述二氧化硅层160，可以看出，由于氧化的过程中采用衬底的硅材料作为氧化层中硅的来源，因此由于第一侧墙150的阻挡，沟道两端的氧化层厚度明显薄于沟道中央的氧化层厚度，且越靠近侧墙，可用于氧化的硅材料越少，形成的氧化层也就越薄。因此，在靠近侧墙的地方，氧化层呈斜坡状。如图4所示。
如果直接在所述二氧化硅层上形成栅极，则栅极下方的二氧化硅层160厚度不均所引起的各种不良效应，例如电流集边效应，以及边界处氧化层过薄会导致热载流子穿越该二氧化硅层160，在栅极介质中引入缺陷。
本发明通过在所述二氧化硅层160与第一侧墙150交界处的上方形成第二侧墙，覆盖了二氧化硅层边界处的斜坡区域，有效地避免了栅极下方的氧化层厚度不均所引起的各种不良效应，优化了器件性能。
为了实现上述目的，接下来，在所述二氧化硅层160上方淀积栅极介质层400，如图5所示。具体的，述栅极介质层可以是热氧化层，包括氧化硅、氮氧化硅；也可为高K介质，例如HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅极介质层的厚度可以为1nm-10nm，例如3nm、5nm或8nm，，其等效氧化厚度为0.5nm～5nm。可以采用热氧化、化学气相沉积（CVD）或原子层沉积（ALD）等工艺来形成栅极介质层。所述栅极介质层400与二氧化硅层160具有相同的形貌，即位于靠近第一侧墙150的沟道上方的部分具有斜坡形。
接下来，如图6所示，在所述栅极介质层垂直方向的侧壁上形成第二侧墙450。具体的，用LPCVD淀积40nm～80nm厚的牺牲侧墙介质层氮化硅，接着用会客技术在栅电极两侧形成宽度为35nm～75nm的氮化硅第二侧墙450。第二侧墙450还可以由氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。所述第二侧墙所述第二侧墙的宽度为3～7nm，覆盖了二氧化硅层边界处的斜坡区域，有效地避免了栅极下方的氧化层厚度不均所引起的各种不良效应，优化了器件性能。
上文所述源漏扩展区205的边界延伸至二氧化硅层160下方，二者重叠的部分长度大于或等于所述第二侧墙450的宽度与栅极介质层400的厚度之和。使得当位于所述栅极叠层下方的衬底形成反型沟道时，所述反型沟道可以将源漏扩展区205连接起来，使器件正常工作。
接下来，在栅极空位中形成栅极叠层500，所述栅极叠层500包括功函数调节层和栅极金属层。栅极金属层可以只为金属栅极，也可以为金属/多晶硅复合栅极，其中多晶硅上表面上具有硅化物。具体的如图7所示，优选的，在栅极介质层上先沉积功函数金属层，之后再在功函数金属层之上形成金属导体层。功函数金属层可以采用TiN、TaN等材料制成，其厚度范围为3nm～15nm。金属导体层可以为一层或者多层结构。其材料可以为TaN、TaC、TiN、TaAlN、TiAlN、MoAlN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合。其厚度范围例如可以为10nm-40nm，如20nm或30nm。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
根据本发明提出的一种用于优化栅极结构以改善器件性能的MOSFET结构及其制造方法，具体的，本发明在位于沟道上方第一侧墙的侧壁方向上的氧化层与栅极介质层之间形成了第二侧墙，所述第二侧墙所述第二侧墙的宽度为3～7nm，覆盖了二氧化硅层边界处的斜坡区域，有效地避免了栅极下方的氧化层厚度不均所引起的各种不良效应，优化了器件性能。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (7)

1.一种MOSFET制造方法，包括：
a.提供衬底(100)、伪栅空位、第一侧墙(150)、源漏扩展区(205)、源漏区(200)和层间介质层(300)；
b.在所述伪栅空位中的衬底上形成二氧化硅层(160)；
c.在所述二氧化硅层(160)和所述伪栅空位侧壁上淀积栅极介质层(400)；
d.在所述伪栅空位形成第二侧墙(450)，所述第二侧墙(450)紧邻栅极介质层(400)，与层间介质层(300)平齐；
e.在所述伪栅空位中形成栅极叠层(500)。
2.根据权利要求1所述的制造方法，其特征在于，所述源漏扩展区(205)的边界延伸至二氧化硅层(160)下方，二者重叠的部分长度大于或等于第二侧墙(450)的宽度与栅极介质层(400)的厚度之和。
3.根据权利要求1所述的制造方法，其特征在于，形成所述源漏扩展区(205)的方法为向着栅极叠层方向倾斜的离子注入。
4.根据权利要求1所述的制造方法，其特征在于，所述第二侧墙(450)的宽度为3～7nm。
5.一种半导体结构，包括：
衬底(100)；
形成于所述衬底(100)之上二氧化硅层(160)；
形成于所述二氧化硅层(160)上方的栅极叠层(500)；
形成于所述栅极叠层(500)两侧并且在衬底(100)之上的第一侧墙(150)；
形成于所述栅极叠层(500)两侧并且在衬底(100)中的源漏区(200)；
形成于所述栅极叠层(500)下方并且在衬底(100)中的源漏扩展区(205)；
其中还包括：
栅极介质层(400)，其位于所述栅极叠层(500)与二氧化硅层(160)之间，以及所述第一侧墙(150)的内壁上；
第二侧墙(450)，其位于与所述第一侧墙(150)相邻接部分所述栅极介质层(400)与所述栅极叠层(500)之间并且位于所述二氧化硅层(160)上方。
6.根据权利要求5所述的半导体结构，其特征在于，所述源漏扩展区(205)的边界延伸至二氧化硅层(160)下方，二者重叠的部分长度大于等于第二侧墙(450)的宽度与栅极介质层(400)的厚度之和。
7.根据权利要求5所述的半导体结构，其特征在于，所述第二侧墙(450)的宽度为3～7nm。
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