WO2015051562A1 - 一种mosfet结构及其制造方法 - Google Patents

一种mosfet结构及其制造方法 Download PDF

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Publication number
WO2015051562A1
WO2015051562A1 PCT/CN2013/085650 CN2013085650W WO2015051562A1 WO 2015051562 A1 WO2015051562 A1 WO 2015051562A1 CN 2013085650 W CN2013085650 W CN 2013085650W WO 2015051562 A1 WO2015051562 A1 WO 2015051562A1
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gate
layer
dielectric layer
silicon dioxide
source
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PCT/CN2013/085650
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French (fr)
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尹海洲
李睿
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中国科学院微电子研究所
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Priority to US14/905,151 priority Critical patent/US20160163825A1/en
Publication of WO2015051562A1 publication Critical patent/WO2015051562A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates to a MOSFET structure and a method of fabricating the same. More specifically, it relates to a MOSFET structure for optimizing a gate structure to improve device performance and a method of fabricating the same.
  • the gate stack typically consists of a gate dielectric layer and a work function adjustment layer.
  • a thin oxide layer is formed over the channel to eliminate the interface state of the channel surface before forming the gate dielectric layer.
  • the silicon dioxide layer is formed by direct oxidation, but the thermal oxidation growth is performed by oxidizing silicon at the bottom of the substrate to form silicon dioxide at both ends of the channel.
  • the silicon under the side wall cannot be oxidized, so the silicon dioxide layer on both sides is thinner than the silicon dioxide layer in the middle of the channel, and the closer to the side wall, the thinner the oxide layer is.
  • the oxide layer is sloped rather than flat near the ends of the channel. This phenomenon causes a certain degree of tilt of the gate dielectric layer and the work function adjusting layer which are subsequently deposited on the oxide layer, forming a peak near the side wall. The presence of such spikes affects the distribution of the electric field during operation of the device.
  • the electric field lines at the peaks are denser than others, causing some adverse effects such as current edge effects.
  • the present invention proposes a MOSFET structure for optimizing a gate structure to improve device performance and a method of fabricating the same.
  • the present invention forms a second sidewall between the oxide layer and the gate dielectric layer in the direction of the sidewall of the first sidewall above the trench, and the width of the second spacer is 3-7 nm, covering
  • the slope region at the boundary of the silicon dioxide layer effectively avoids various adverse effects caused by uneven thickness of the oxide layer under the gate, and optimizes device performance.
  • the present invention provides a MOSFET structure and method of fabricating the same for optimizing a gate structure to improve device performance.
  • the present invention provides a method of fabricating a MOSFET, comprising: a. providing a substrate, a dummy gate vacancy, a first sidewall, a source/drain extension region, a source/drain region, and an interlayer dielectric layer; b. Forming a silicon dioxide layer on the bottom of the dummy gate vacancies;
  • a boundary of the source/drain extension region extends below the silicon dioxide layer, and a portion length of the overlap portion is greater than or equal to a sum of a width of the second sidewall spacer and a thickness of the gate dielectric layer;
  • the method of forming the source/drain extension region is ion implantation inclined toward the gate stack direction;
  • the width of the second sidewall spacer is 3-7 nm.
  • the present invention also provides a semiconductor structure, including:
  • a first sidewall spacer formed on both sides of the gate stack and above the substrate
  • a source-drain extension region formed under the gate stack and in the substrate
  • a gate dielectric layer between the gate stack and the silicon dioxide layer, and an inner wall of the first sidewall
  • the boundary of the source/drain extension region extends below the silicon dioxide layer, and the overlapping portions thereof
  • the length of the sub-length is greater than or equal to the sum of the width of the second sidewall spacer and the thickness of the gate dielectric layer;
  • the width of the second sidewall spacer is 3-7 nm.
  • a MOSFET structure and a method of fabricating the same for optimizing a gate structure to improve device performance specifically, an oxide layer in the direction of a sidewall of a first spacer above the trench Forming a second sidewall between the gate dielectric layer and the second sidewall spacer having a width of 3-7 nm covering the slope region at the boundary of the silicon dioxide layer, thereby effectively avoiding the gate
  • Various adverse effects caused by uneven thickness of the oxide layer under the pole optimize the device performance.
  • FIG. 1 through 7 schematically illustrate cross-sectional views of semiconductor structures at various stages of forming a fabrication method in accordance with the present invention. detailed description
  • the present invention provides a semiconductor structure, including:
  • a first spacer 150 formed on both sides of the gate stack 500 and above the substrate 100; source and drain regions 200 formed on both sides of the gate stack 500 and in the substrate 100;
  • a source/drain extension region 205 formed under the gate stack 500 and in the substrate 100;
  • a second spacer 450 is disposed between the gate dielectric layer 400 and the gate stack 500 adjacent to the first spacer 150 and over the silicon dioxide layer 160.
  • the gate stack includes a work function adjustment layer and a gate metal layer.
  • the gate metal layer may be only a metal gate or a metal/polysilicon composite gate, wherein the polysilicon has a silicide on its upper surface.
  • the preferred material of the gate dielectric layer is silicon oxynitride, which may also be silicon oxide or a high K material. Its equivalent oxidation thickness is 0.5 nm to 5 nm.
  • the semiconductor channel region is located on the surface of the substrate 100, and the preferred material is single crystal silicon having a thickness of 2 to 20 nm. This region is extremely lightly doped or even undoped. In the case of doping, the doping type is opposite to that of the source and drain regions.
  • the source and drain regions are respectively located on both sides of the gate stack, within the village 100.
  • the source region is symmetrical with the drain region, and its doping type is opposite to that of the village.
  • the boundary of the source/drain extension region 205 extends below the silicon dioxide layer 160, and the length of the overlap portion is greater than or equal to the sum of the width of the second spacer 450 and the thickness of the gate dielectric layer 400.
  • the silicon dioxide layer 160 When the silicon dioxide layer 160 is generally formed, there is a slope region at a boundary where it contacts the first spacer 150, and if a gate is formed directly on the silicon dioxide layer, the silicon dioxide under the gate Various undesirable effects caused by uneven thickness of layer 160, such as current edge effects, and excessively thin oxide layers at the boundaries can cause hot carriers to traverse the silicon dioxide layer 160, introducing defects into the gate dielectric.
  • the present invention forms a second spacer wall above the interface between the silicon dioxide layer 160 and the first spacer 150, and has a width of, for example, 3 to 7 nm, covering a slope region at a boundary of the silicon dioxide layer.
  • a village bottom is first provided, and a dummy gate structure 101 is formed on the bottom of the village.
  • the dummy gate structure 101 may be a single layer or a plurality of layers.
  • the dummy gate structure 101 may include a polymer material, amorphous silicon, polysilicon or TiN, and may have a thickness of 10 nm to 200 nm.
  • the dummy gate structure includes Polycrystalline silicon and dioxide, specifically, chemical vapor deposition is used to fill the gate vacancies with polysilicon, and then a layer of silicon dioxide dielectric is formed over the polysilicon by epitaxial growth, oxidation, CVD, and the like.
  • the gate electrode pattern is formed by photolithography and etching of the deposited dummy gate stack by a conventional CMOS process, and then the exposed portion of the gate dielectric layer is etched away by using the gate electrode pattern as a mask. It should be noted that the above-described methods of forming the gate dielectric layer are the same or similar, and therefore will not be described again.
  • the village substrate 100 on both sides of the dummy gate structure is shallowly doped to form a source/drain extension region 205, and Halo implantation may also be performed to form a Halo implantation region.
  • the impurity type of the source/drain extension region 205 is the same as the device type, and the impurity type of the Halo implant is opposite to the device type.
  • the method of forming the source/drain extension region 205 is oblique ion implantation, as shown in FIG. 1, such that the boundary of the source/drain extension region 205 extends below the dummy gate vacancy.
  • a first spacer 150 is formed on the sidewall of the gate stack for separating the gates. Specifically, a 40 nm to 80 nm thick sacrificial spacer dielectric layer of silicon nitride is deposited by LPCVD, and then a first spacer 150 of silicon nitride having a width of 35 nm to 75 nm is formed on both sides of the gate by a guest technique.
  • the first side wall 150 can also be formed from silicon oxide, silicon oxynitride, silicon carbide, combinations thereof, and/or other suitable materials.
  • the first side wall 150 may have a multi-layered structure.
  • the first side wall 150 may also be formed by a process including a deposition etch which may range from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • a silicon dioxide dielectric layer having a thickness of 10 nm to 35 nm is deposited on the semiconductor structure to form an interlayer dielectric layer 300, and the dielectric layer is used as a buffer layer, and the ion implantation source and drain are formed. Area.
  • the dopant is boron or boron or indium or gallium.
  • the dopant is phosphorus or arsenic or antimony.
  • the doping concentration is 5el0 19 cm_ 3 ⁇ lel0 2() cm_ 3 .
  • the semiconductor structure after doping is completed as shown in FIG. 2.
  • the dummy gate structure is removed to form dummy gate vacancies, as shown in FIG.
  • the removal of the dummy gate structure can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
  • a silicon dioxide layer 160 is formed on the channel surface in the dummy gate vacancies, as shown in FIG. Specifically, the silicon dioxide layer 160 can be formed by dry oxidation. It can be seen that since the silicon material of the village bottom is used as the source of silicon in the oxide layer during the oxidation process, the first sidewall 150 is Blocking, the thickness of the oxide layer at both ends of the channel is significantly thinner than the thickness of the oxide layer in the center of the channel, and the closer The side walls, the less silicon material that can be used for oxidation, the thinner the oxide layer formed. Therefore, the oxide layer is sloped near the side wall. As shown in Figure 4.
  • the present invention forms a second spacer wall above the boundary between the silicon dioxide layer 160 and the first sidewall spacer 150, covering a slope region at the boundary of the silicon dioxide layer, effectively avoiding the underside of the gate electrode.
  • Various adverse effects caused by uneven thickness of the oxide layer optimize device performance.
  • a gate dielectric layer 400 is deposited over the silicon dioxide layer 160, as shown in FIG.
  • the gate dielectric layer may be a thermal oxide layer, including silicon oxide or silicon oxynitride; or a high-k dielectric such as HfA10N, HfSiA10N, HfTaA10N, HfTiA10N, HfON, HfSiON, HfTaON, HfTiON, A1 2 0 3
  • the thickness of the gate dielectric layer may be 1 nm to 10 nm, for example, 3 nm, 5 nm, or 8 nm, and the equivalent oxidation thickness thereof is 0.5 nm to 5 nm.
  • the gate dielectric layer can be formed by processes such as thermal oxidation, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
  • the gate dielectric layer 400 has the same topography as the silicon dioxide layer 160, that is, a portion located above the channel of the first spacer 150 has a slope shape.
  • the second sidewall spacer of the second sidewall spacer has a width of 3 to 7 nm and covers a slope region at a boundary of the silicon dioxide layer, thereby effectively avoiding various defects caused by uneven thickness of the oxide layer under the gate electrode. Effect, optimized device performance.
  • the boundary of the source/drain extension region 205 extends above the silicon dioxide layer 160, and the length of the overlap portion is greater than or equal to the width of the second spacer 450 and the thickness of the gate dielectric layer 400. with.
  • the inversion channel can connect the source/drain extension regions 205 to make the device operate normally.
  • a gate stack 500 is formed in the gate vacancies, the gate stack 500 including a work function adjusting layer and a gate metal layer.
  • the gate metal layer may be only a metal gate or a metal/polysilicon composite gate, wherein the polysilicon has a silicide on its upper surface.
  • a work function metal layer is deposited on the gate dielectric layer, and then a metal conductor layer is formed on the work function metal layer.
  • the work function metal layer can be made of materials such as TiN and TaN, and the thickness thereof is
  • a MOSFET structure and a method of fabricating the same for optimizing a gate structure to improve device performance specifically, an oxide layer in the direction of a sidewall of a first spacer above the trench Forming a second sidewall between the gate dielectric layer and the second sidewall spacer having a width of 3-7 nm covering the slope region at the boundary of the silicon dioxide layer, thereby effectively avoiding the gate
  • Various adverse effects caused by uneven thickness of the oxide layer under the pole optimize the device performance.

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Abstract

本发明提供一种 MOSFET及其制造方法，其中所述方法包括：a.提供衬底（100）、伪栅空位、第一侧墙（150）、源漏扩展区（205）、源漏区（200）和层间介质层（300）；b.在所述伪栅空位中的衬底上形成二氧化硅层（160）； c.在所述半导体材料上淀积栅极介质层(400)；d.在所述伪栅空位形成第二侧墙（450），所述第二侧墙（450）紧邻栅极介质层（400），与层间介质层（300）平齐；e.在所述伪栅空位中形成栅极叠层（500）。本发明有效地避免了栅极下方的氧化层厚度不均所引起的各种不良效应，优化了器件性能。

Description

一种 MOSFET结构及其制造方法
[0001]本申请要求了 2013年 10月 13 日提交的、 申请号为 201310476462.6、 发明名称为 "一种 MOSFET 结构及其制造方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
[0002】本发明涉及一种 MOSFET结构及其制造方法。 更具体而言， 涉及一种 用于优化栅极结构以改善器件性能的 MOSFET结构及其制造方法。 技术背景
[0003】在 MOSFET中， 为了尽可能的优化器件性能， 其栅极叠层一般由栅极 介质层和功函数调节层组成。 1§]时， 为了改善栅极介质层和沟道材料之间的 界面性能， 通常在形成栅极介质层之前， 先在沟道上方形成一层薄氧化层以 消除沟道表面的界面态。 现有技术中， 对于硅村底的器件， 多采用直接氧化 的方式形成所述二氧化硅层， 但是由于热氧化生长是以村底的硅为材料氧化 生成二氧化硅， 在沟道两端边界处， 由于侧墙的阻挡， 侧墙下方的硅并不能 被氧化， 因此两侧的二氧化硅层会比沟道中部的二氧化硅层薄， 越靠近侧墙 处， 氧化层越薄， 氧化层在靠近沟道两端的地方是斜坡状的而非平坦的。 这 一现象使得随后淀积在氧化层上的栅极介质层和功函数调节层都出现了一定 程度的倾斜， 在靠近侧墙的地方形成尖峰。 而这种尖峰的存在， 在器件工作 时会影响电场的分布， 尖峰处的电场线会较別处密集， 引起电流集边效应等 一些列不良影响。
[0004]针对这一问题， 本发明提出了一种用于优化栅极结构以改善器件性能 的 MOSFET结构及其制造方法。 具体的， 本发明在位于沟道上方第一侧墙的 侧壁方向上的氧化层与栅极介质层之间形成了第二侧墙， 所述第二侧墙的宽 度为 3~7nm， 覆盖了二氧化硅层边界处的斜坡区域， 有效地避免了栅极下方 的氧化层厚度不均所引起的各种不良效应， 优化了器件性能。 发明内容
[0005]本发明提供了一种用于优化栅极结构以改善器件性能的 MOSFET结构 及其制造方法。 具体的， 本发明提供的制造一种 MOSFET制造方法， 包括： a. 提供村底、 伪栅空位、 第一侧墙、 源漏扩展区、 源漏区和层间介质层； b. 在所述伪栅空位中的村底上形成二氧化硅层；
c 在所述半导体材料上淀积栅极介质层；
d. 在所述伪栅空位形成第二侧墙， 所述第二侧墙紧邻栅极介质层， 与层间 介质层平齐；
e. 在所述伪栅空位中形成栅极叠层。
[0006】其中， 所述源漏扩展区的边界延伸至二氧化硅层下方， 二者重叠的部 分长度大于或等于第二侧墙的宽度与栅极介质层的厚度之和；
[0007]其中， 形成所述源漏扩展区的方法为向着栅极叠层方向倾斜的离子注 入；
[0008】其中， 所述第二侧墙的宽度为 3~7nm。
[0009]本发明还提供一种半导体结构， 包括：
村底；
形成于所述村底之上二氧化硅层；
形成于所述二氧化硅层上方的栅极叠层；
形成于所述栅极叠层两侧并且在村底之上的第一侧墙；
形成于所述栅极叠层两侧并且在村底中的源漏区；
形成于所述栅极叠层下方并且在村底中的源漏扩展区；
[0010]其中还包括：
栅极介质层， 其位于所述栅极叠层与二氧化硅层之间， 以及所述第一侧 墙的内壁上；
第二侧墙， 其位于与所述第一侧墙相邻接部分所述栅极介质层与所述栅 极叠层之间并且位于所述二氧化硅层上方。
[0011】其中， 所述源漏扩展区的边界延伸至二氧化硅层下方， 二者重叠的部 分长度大于等于第二侧墙的宽度与栅极介质层的厚度之和；
[0012]其中所述第二侧墙的宽度为 3~7nm。
[0013]根据本发明提出的一种用于优化栅极结构以改善器件性能的 MOSFET 结构及其制造方法， 具体的， 本发明在位于沟道上方第一侧墙的侧壁方向上 的氧化层与栅极介质层之间形成了第二侧墙， 所述第二侧墙所述第二侧墙的 宽度为 3~7nm， 覆盖了二氧化硅层边界处的斜坡区域， 有效地避免了栅极下 方的氧化层厚度不均所引起的各种不良效应， 优化了器件性能。 附图说明
[0014]图 1至图 7示意性地示出了形成根据本发明的制造方法各阶段半导体 结构的剖面图。 具体实施方式
[0015】为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本 发明的实施例作详细描述。
[0016】下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不能解释为对本发明的限制。
[0017】参见图 7， 本发明提供了一种半导体结构， 包括：
村底 100 ;
形成于所述村底 100之上二氧化硅层 160 ;
形成于所述二氧化硅层 160上方的栅极叠层 500 ;
形成于所述栅极叠层 500两侧并且在村底 100之上的第一侧墙 150 ; 形成于所述栅极叠层 500两侧并且在村底 100中的源漏区 200 ;
形成于所述栅极叠层 500下方并且在村底 100中的源漏扩展区 205 ;
[0018]其中还包括：
栅极介质层 400， 其位于所述栅极叠层 500与二氧化硅层 160之间， 以及 所述第一侧墙 150的内壁上；
第二侧墙 450， 其位于与所述第一侧墙 150相邻接部分所述栅极介质层 400与所述栅极叠层 500之间并且位于所述二氧化硅层 160上方。
[0019]栅极叠层包括功函数调节层和栅极金属层。 栅极金属层可以只为金属 栅极， 也可以为金属 /多晶硅复合栅极， 其中多晶硅上表面上具有硅化物。 栅 介质层优选材料为氮氧化硅， 也可为氧化硅或高 K材料。 其等效氧化厚度为 0.5nm~5nm。
[0020】半导体沟道区位于村底 100 的表面， 其优选材料为单晶硅， 其厚度为 2~20nm。 该区域是极轻摻杂甚至未摻杂的。 在摻杂的情况下， 其摻杂类型与 源漏区摻杂相反。
[0021]源区和漏区分別位于栅极叠层两侧，村底 100内。源区与漏区相对称， 其摻杂类型与村底相反。
[0022]源漏扩展区 205的边界延伸至二氧化硅层 160下方， 二者重叠的部分 长度大于等于第二侧墙 450的宽度与栅极介质层 400的厚度之和。
[0023]通常形成二氧化硅层 160时， 其与第一侧墙 150相接的边界处存在斜 坡区域， 如果直接在所述二氧化硅层上形成栅极， 则栅极下方的二氧化硅层 160厚度不均所引起的各种不良效应， 例如电流集边效应， 以及边界处氧化层 过薄会导致热载流子穿越该二氧化硅层 160， 在栅极介质中引入缺陷。
[0024]本发明通过在所述二氧化硅层 160与第一侧墙 150交界处的上方形成 第二侧墙， 其宽度例如为 3~7nm， 覆盖了二氧化硅层边界处的斜坡区域， 有 效地避免了栅极下方的氧化层厚度不均所引起的各种不良效应， 优化了器件 性能。
[0025】下面结合附图对本发明的制作方法进行详细说明， 包括以下步骤。 需 要说明的是， 本发明各个实施例的附图仅是为了示意的目的， 因此没有必要 按比例绘制。
[0026】首先提供村底， 并在所述村底上形成伪栅结构 101。 所述伪栅结构 101 可以是单层的， 也可以是多层的。 伪栅结构 101 可以包括聚合物材料、 非晶 硅、 多晶硅或 TiN， 厚度可以为 10nm~200nm。 本实施例中， 伪栅结构包括 多晶硅和二氧化， 具体的， 采用化学汽相淀积的方法在栅极空位中填充多晶 硅，接着在多晶硅上方形成一层二氧化硅介质层，形成方法可以是外延生长、 氧化、 CVD等。接着采用常规 CMOS工艺光刻和刻蚀所淀积的伪栅叠层形成 栅电极图形， 然后以栅电极图形为掩膜腐蚀掉栅极介质层的棵露部分。 需说 上述所列举的形成栅介质层相同或类似的方法， 故不再赘述。
[0027】接下来， 对伪栅结构两侧的村底 100进行浅摻杂， 以形成源漏扩展区 205， 还可以进行 Halo注入， 以形成 Halo注入区。 其中源漏扩展区 205的杂 质类型与器件类型一致， Halo 注入的杂质类型与器件类型相反。 具体的， 形 成所述源漏扩展区 205的方法为倾斜的离子注入， 如图 1所示， 使得所述源 漏扩展区 205的边界延伸至伪栅空位下方。
[0028】接下来， 在栅极堆叠的侧壁上形成第一侧墙 150， 用于将栅极隔开。 具 体的， 用 LPCVD淀积 40nm~80nm厚的牺牲侧墙介质层氮化硅， 接着用会客 技术在栅极两侧形成宽度为 35nm~75nm的氮化硅的第一侧墙 150。 第一侧墙 150 还可以由氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的材料形 成。 第一侧墙 150可以具有多层结构。 第一侧墙 150还可以通过包括沉积刻 蚀工艺形成， 其厚度范围可以是 10nm -100nm， 如 30nm、 50nm或 80nm。
[0029】接下来， 在所述半导体结构上淀积一层厚度为 10nm~35nm厚的二氧化 硅介质层， 形成层间介质层 300， 并以该介质层为緩冲层， 离子注入源漏区。 对 P型晶体而言， 摻杂剂为硼或弗化硼或铟或镓等。 对 N型晶体而言， 摻杂 剂为磷或砷或銻等。摻杂浓度为 5el019cm_3~lel02() cm_3。 完成摻杂之后的半导 体结构如图 2所示。
[0030】接下来， 去除所述伪栅结构， 形成伪栅空位， 如图 3 所示。 去除伪栅 结构可以采用湿刻和 /或干刻除去。 在一个实施例中， 采用等离子体刻蚀。
[0031】接下来， 在伪栅空位中的沟道表面形成二氧化硅层 160， 如图 4所示。 具体的， 可采用干氧氧化的方法形成所述二氧化硅层 160， 可以看出， 由于氧 化的过程中采用村底的硅材料作为氧化层中硅的来源，因此由于第一侧墙 150 的阻挡， 沟道两端的氧化层厚度明显薄于沟道中央的氧化层厚度， 且越靠近 侧墙， 可用于氧化的硅材料越少， 形成的氧化层也就越薄。 因此， 在靠近侧 墙的地方， 氧化层呈斜坡状。 如图 4所示。
[0032]如果直接在所述二氧化硅层上形成栅极，则栅极下方的二氧化硅层 160 厚度不均所引起的各种不良效应， 例如电流集边效应， 以及边界处氧化层过 薄会导致热载流子穿越该二氧化硅层 160， 在栅极介质中引入缺陷。
[0033]本发明通过在所述二氧化硅层 160与第一侧墙 150交界处的上方形成 第二侧墙， 覆盖了二氧化硅层边界处的斜坡区域， 有效地避免了栅极下方的 氧化层厚度不均所引起的各种不良效应， 优化了器件性能。
[0034】为了实现上述目的， 接下来， 在所述二氧化硅层 160 上方淀积栅极介 质层 400，如图 5所示。具体的，述栅极介质层可以是热氧化层，包括氧化硅、 氮氧化硅；也可为高 K介质，例如 HfA10N、HfSiA10N、HfTaA10N、HfTiA10N、 HfON、 HfSiON、 HfTaON、 HfTiON、 A1203、 La203、 Zr02、 LaAlO中的一种 或其组合， 栅极介质层的厚度可以为 lnm -10nm， 例如 3nm、 5nm或 8nm，， 其等效氧化厚度为 0.5nm~5nm。 可以采用热氧化、 化学气相沉积 （CVD) 或 原子层沉积 （ALD) 等工艺来形成栅极介质层。 所述栅极介质层 400 与二氧 化硅层 160具有相同的形貌， 即位于靠近第一侧墙 150的沟道上方的部分具 有斜坡形。
[0035】接下来， 如图 6 所示， 在所述栅极介质层垂直方向的侧壁上形成第二 侧墙 450。具体的，用 LPCVD淀积 40nm~80nm厚的牺牲侧墙介质层氮化硅， 接着用会客技术在栅电极两侧形成宽度为 35nm~75nm的氮化硅第二侧墙 450。 第二侧墙 450还可以由氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适 的材料形成。 所述第二侧墙所述第二侧墙的宽度为 3~7nm， 覆盖了二氧化硅 层边界处的斜坡区域， 有效地避免了栅极下方的氧化层厚度不均所引起的各 种不良效应， 优化了器件性能。
[0036]上文所述源漏扩展区 205的边界延伸至二氧化硅层 160下方， 二者重 叠的部分长度大于或等于所述第二侧墙 450的宽度与栅极介质层 400的厚度 之和。 使得当位于所述栅极叠层下方的村底形成反型沟道时， 所述反型沟道 可以将源漏扩展区 205连接起来， 使器件正常工作。 [0037]接下来， 在栅极空位中形成栅极叠层 500， 所述栅极叠层 500包括功函 数调节层和栅极金属层。 栅极金属层可以只为金属栅极， 也可以为金属 /多晶 硅复合栅极， 其中多晶硅上表面上具有硅化物。具体的如图 7所示，优选的， 在栅极介质层上先沉积功函数金属层， 之后再在功函数金属层之上形成金属 导体层。 功函数金属层可以采用 TiN、 TaN等材料制成， 其厚度范围为
3nm~15nm。金属导体层可以为一层或者多层结构。其材料可以为 TaN、 TaC、 TiN、 TaAlN、 TiAlN、 ΜοΑ1Ν、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、RuTax、NiTax中的一种或其组合。其厚度范围例如可以为 10nm -40nm， 如 20nm或 30nm。
[0038]虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0039]根据本发明提出的一种用于优化栅极结构以改善器件性能的 MOSFET 结构及其制造方法， 具体的， 本发明在位于沟道上方第一侧墙的侧壁方向上 的氧化层与栅极介质层之间形成了第二侧墙， 所述第二侧墙所述第二侧墙的 宽度为 3~7nm， 覆盖了二氧化硅层边界处的斜坡区域， 有效地避免了栅极下 方的氧化层厚度不均所引起的各种不良效应， 优化了器件性能。
[0040]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本 领域的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发出的 工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明 描述的对应实施例大体相同的功能或者获得大体相同的结果， 依照本发明可 以对它们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、 机构、 制 造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种 MOSFET制造方法， 包括：
a. 提供村底 （100)、 伪栅空位、 第一侧墙 （150)、 源漏扩展区 （205 )、 源漏区 （200) 和层间介质层 （300) ;
b. 在所述伪栅空位中的村底上形成二氧化硅层 （160) ;
c 在所述半导体材料上淀积栅极介质层 (400) ;
d. 在所述伪栅空位形成第二侧墙 （450)， 所述第二侧墙 （450) 紧邻栅极 介质层 （400)， 与层间介质层 （300) 平齐；
e. 在所述伪栅空位中形成栅极叠层 （500)。
2、 根据权利要求 1 所述的制造方法， 其特征在于， 所述源漏扩展区 （205 ) 的边界延伸至二氧化硅层 （160) 下方， 二者重叠的部分长度大于或等于第二 侧墙 （450) 的宽度与栅极介质层 （400) 的厚度之和。
3、 根据权利要求 1所述的制造方法，其特征在于，形成所述源漏扩展区（205) 的方法为向着栅极叠层方向倾斜的离子注入。
4、 根据权利要求 1 所述的制造方法， 其特征在于， 所述第二侧墙 （450) 的 宽度为 3~7nm。
5、 一种半导体结构， 包括：
村底 （100) ;
形成于所述村底 （100) 之上二氧化硅层 （160) ;
形成于所述二氧化硅层 （160) 上方的栅极叠层 （500) ;
形成于所述栅极叠层（500)两侧并且在村底（100)之上的第一侧墙（150) ; 形成于所述栅极叠层（500) 两侧并且在村底（100) 中的源漏区 （200) ; 形成于所述栅极叠层（500)下方并且在村底（100)中的源漏扩展区（205 ) ; 其中还包括：
栅极介质层 （400)， 其位于所述栅极叠层 （500) 与二氧化硅层 （160) 之间， 以及所述第一侧墙 （150) 的内壁上；
第二侧墙 （450)， 其位于与所述第一侧墙 （150) 相邻接部分所述栅极介 质层 （400) 与所述栅极叠层 （500) 之间并且位于所述二氧化硅层 （160) 上 方。
6、 根据权利要求 5所述的半导体结构，其特征在于，所述源漏扩展区（205) 的边界延伸至二氧化硅层 （160) 下方， 二者重叠的部分长度大于等于第二侧 墙 （450) 的宽度与栅极介质层 （400) 的厚度之和。
7、 根据权利要求 5 所述的半导体结构， 其特征在于， 所述第二侧墙 （450) 的宽度为 3~7nm。
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