WO2013026243A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2013026243A1
WO2013026243A1 PCT/CN2011/083325 CN2011083325W WO2013026243A1 WO 2013026243 A1 WO2013026243 A1 WO 2013026243A1 CN 2011083325 W CN2011083325 W CN 2011083325W WO 2013026243 A1 WO2013026243 A1 WO 2013026243A1
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Prior art keywords
gate
layer
dummy gate
forming
dielectric layer
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PCT/CN2011/083325
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English (en)
French (fr)
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尹海洲
骆志炯
朱慧珑
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中国科学院微电子研究所
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Priority to US13/505,731 priority Critical patent/US20130043517A1/en
Publication of WO2013026243A1 publication Critical patent/WO2013026243A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates to the field of semiconductor fabrication, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • the gate is fabricated after the source/drain regions, avoiding the high temperature processing of the source/drain annealing process, ie avoiding the interfacial reaction caused by the high temperature process and the metal gate work function change, the PMOS threshold voltage rise, etc. problem.
  • a dummy gate is formed first, followed by source/drain ion implantation and annealing operations, and finally the dummy gate is removed and filled to form a metal gate.
  • the gate length of the semiconductor device is reduced to 20 nm or less, and gate filling in such a small space causes voids and the like to affect the performance and reliability of the semiconductor device.
  • the present invention is directed to at least solving the above technical deficiencies, and provides a method for fabricating a semiconductor device and a structure thereof.
  • the process difficulty is reduced, voids are avoided, and device reliability is improved.
  • the present invention provides a method of fabricating a semiconductor structure, the method comprising the steps of:
  • the dummy gate layer forms a concentration gradient distribution in which the dopant ions gradually decrease from the surface to the inside, and in the subsequent patterning step, a suitable etching method is selected, the dummy gate layer There is a gradually increasing etching rate from the surface to the inside, so that a gate structure similar to an inverted frustum shape can be formed.
  • Another aspect of the present invention also provides a semiconductor structure including a substrate, a gate stack, sidewall spacers, and source/drain regions, wherein:
  • the gate stack is disposed on the substrate, including a gate dielectric layer and a gate, a top cross section of the gate is larger than a bottom cross section of the gate, and the gate dielectric layer is sandwiched between the gate And the gate dielectric layer wraps the sidewalls and the bottom of the gate;
  • the side walls are located on both sides of the gate stack
  • the source/drain regions are formed in the substrate on both sides of the gate stack.
  • FIG. 1 is a flow chart of one embodiment of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2 to FIG. 16 are schematic cross-sectional structural views of the semiconductor structure at various stages of fabrication in the process of fabricating a semiconductor structure according to the method illustrated in FIG. 1; 17 is a data table showing the relationship between the corrosion rate of ⁇ 100> Si and the boron doping concentration in the KOH etching solution. detailed description
  • first and second features are formed in direct contact
  • additional features formed between the first and second features. Embodiments such that the first and second features may not be in direct contact.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIGS. 2 through 16 are cross-sectional views showing stages of fabricating a semiconductor structure in accordance with the flow of FIG. 1 in accordance with an embodiment of the present invention.
  • the method of forming the semiconductor structure of Fig. 1 will be specifically described below with reference to Figs. 2 to 16. It is to be understood that the drawings of the embodiments of the present invention are for the purpose of illustration
  • step S101 a substrate 100 is provided on which a dielectric layer 200 and a dummy gate layer 210 are formed.
  • the substrate 100 includes a silicon substrate (eg, a silicon wafer).
  • the substrate 100 can include various doping configurations in accordance with design requirements known in the art, such as a P-type substrate or an N-type substrate.
  • the substrate 100 in other embodiments may also include other basic semiconductors such as germanium, or compound semiconductors (such as III-V materials) such as silicon carbide, gallium arsenide, indium arsenide.
  • substrate 100 can have, but is not limited to, a thickness of about a few hundred microns, such as from 200 um to 800 um. Within the thickness range.
  • isolation regions such as shallow trench isolation (STI) structures 110, may be formed in substrate 100, as shown in FIG. 2, to electrically isolate the continuous field effect transistor devices. Field injection can also be performed on the surface of the substrate 100.
  • STI shallow trench isolation
  • the dielectric layer 200 is formed on the substrate 100, which may be silicon oxide, silicon nitride, or a high-k material such as Hf0 2 , HfSiO, HfSiON, HfTaO, Hf iO, HfZrO. , A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO or a combination thereof.
  • the dielectric layer 200 has a thickness ranging from 2 nm to 10 nm.
  • polysilicon is deposited on the dielectric layer 200 to form a dummy gate layer 210 having a thickness of 10 nm to 200 nm.
  • the polysilicon dummy may be formed by a suitable method such as sputtering or chemical vapor deposition.
  • Gate layer 210 Preferably, as shown in FIG. 4, a hard mask layer 220 may also be formed on the dummy gate layer 210, for example, by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or a combination thereof to protect the dummy gate.
  • the top area of layer 210 is not limited to depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or a combination thereof.
  • step S102 is performed to dope and anneal the dummy gate layer 210.
  • the dummy gate layer 210 is doped for the first ion implantation 001 to form a doping profile. In other embodiments of the present invention, doping may also be performed by diffusion.
  • the doped element is boron, phosphorus or arsenic.
  • the concentration peak of the ion implantation is on the upper surface of the dummy gate layer 210, and then annealing treatment is performed to obtain A doping concentration distribution in the dummy gate layer 210 that gradually decreases inward from the surface.
  • the doping concentration of the surface of the dummy gate layer 210 is in the range of 1 ⁇ 10 19 cm— 3 to 10 21 cm” 3 .
  • step S103 is performed to pattern the dummy gate layer to form a dummy gate 210 having a shape of an inverted truncated cone shape that is large and small.
  • the cross-sectional shape is an inverted trapezoid.
  • FIG. 6 is a cross-sectional view showing the hard mask layer 220 in a pattern.
  • Figure 7 is a cross-sectional view of the dummy gate layer after patterning.
  • the method of etching the dummy gate layer includes wet etching using potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) or ethylenediamine-catechol (EDP).
  • KOH potassium hydroxide
  • TMAH tetramethylammonium hydroxide
  • EDP ethylenediamine-catechol
  • Figure 17 shows the relationship between the corrosion rate of KOH etching solution ⁇ 100> Si and the boron doping concentration. It can be seen that the etching rate is basically constant when the doping concentration is less than the concentration threshold of 1 X 10 19 cm- 3 . When the threshold concentration is exceeded, the corrosion rate is inversely proportional to the fourth power of the doping concentration. At a certain concentration, the corrosion rate is small, and even corrosion can be considered to stop. For the doping of elements such as phosphorus and arsenic, there is a tendency that the corrosion rate changes with the doping concentration.
  • the method of combining the RIE dry etching and the wet etching is performed on the dummy gate layer patterning.
  • the patterned hard mask layer 220 is used as a mask, and the RIE dry method is used.
  • the dummy gate layer is etched, and the resulting dummy gate has approximately vertical sidewalls.
  • wet etching is performed by using a suitable etching solution such as potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) or ethylenediamine-catechol (EDP) to control the concentration of the corrosive solution, temperature, Corrosion time or the like, a dummy gate 210 having an inverted frustum-shaped interface is obtained.
  • KOH potassium hydroxide
  • TMAH tetramethylammonium hydroxide
  • EDP ethylenediamine-catechol
  • step S104 is performed to form the side wall 400 and the source/drain regions 310.
  • step S104 further comprising forming the source/drain extension region 300 first.
  • a shallow source/drain extension 300 is formed in the substrate 100 by low energy large angle implantation (second ion implantation 002), and P-type or N-type dopants or impurities may be implanted into the substrate 100, for example
  • source/drain extension 300 can be P-type doped Si; for NMOS, source/drain extension 300 can be N-type doped Si.
  • the semiconductor structure is subsequently annealed to activate doping in the source/drain extension 300, and the annealing may be formed by other suitable methods including rapid annealing, spike annealing, and the like.
  • the annealing operation may also be performed after forming the source/drain regions 310. Since the thickness of the source/drain extension region 300 is shallow, the short channel effect can be effectively suppressed.
  • Figure 8 is a cross-sectional view showing the structure after the source/drain extension 300 is formed. Alternatively, tilt ion implantation may also be performed to form a Halo implant region.
  • the sidewall spacer 400 is formed after the source/drain extension region is formed.
  • the spacer 400 is formed on the sidewall of the dummy gate 210 for separating the gates.
  • the sidewall 400 can be formed by a deposition-etch process from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the spacer 400 may have a multilayer structure and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • source/drain regions 310 are located in the substrate, as shown in FIG. 10, and may be formed on both sides of the dummy gate 210 by implanting P-type or N-type dopants or impurities into the substrate 100.
  • source/drain regions 310 can be P-type doped Si; for NMOS, source/drain regions 310 can be N-type doped Si.
  • the source/drain regions 310 may be formed by a method including photolithography, ion implantation, diffusion, and/or other suitable processes, and in the present embodiment, source/drain regions are formed by a third ion implantation 003. 310.
  • the semiconductor structure is then annealed to activate doping in the source/drain regions 110, and the annealing may be formed by other suitable methods including rapid annealing, spike annealing, and the like.
  • the source/drain regions 310 are inside the substrate 100.
  • the source/drain regions 310 may be lifted source/drain structures formed by selective epitaxial growth, the top portion of the epitaxial portion Higher than the dummy gate bottom (the dummy gate bottom referred to in this specification means the boundary between the dummy gate and the substrate 100).
  • the exposed dielectric layer 200 may be etched away after forming the dummy gate 210, or the exposed dielectric layer 200 may be etched away after forming the source and drain regions.
  • a layer of metal such as Ti, Pt, Co, Ni, Cu, etc. may be deposited on the substrate, after being annealed at the source.
  • a silicide contact layer (not shown) is formed on/drain region 310.
  • step S105 is performed to deposit the interlayer dielectric layer 500 and planarize.
  • the interlayer dielectric layer 500 may be formed by chemical vapor deposition (CVD), high density plasma CVD, spin coating, and/or other suitable processes.
  • the material of the interlayer dielectric layer 500 may include silicon oxide, doped silicon oxide (such as fluorosilicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass), low-k dielectric material (such as black diamond, coral, etc.). One or a combination thereof.
  • the interlayer dielectric layer 500 may have a thickness ranging from 40 nm to 150 nm, such as 80 nm, 100 nm or 120 nm, and may have a multilayer structure (the materials may be different between adjacent layers).
  • the interlayer dielectric layer 500 is planarized to expose the upper surface of the dummy gate 210 as shown in FIG.
  • the interlayer dielectric layer 500 may be ground and thinned by a chemical mechanical polishing (CMP) method while chemically polishing the hard mask layer 220 on the dummy gate 210 such that the dummy gate 210 and the interlayer dielectric layer 500
  • CMP chemical mechanical polishing
  • step S106 is performed to remove the dummy gate 210 to form an opening 410.
  • Dry RIE etching thermal acid, hydrofluoric acid-nitric acid-acetic acid (HNA), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) or ethylenediamine-catechol (EDP)
  • HNA hydrofluoric acid-nitric acid-acetic acid
  • KOH potassium hydroxide
  • TMAH tetramethylammonium hydroxide
  • EDP ethylenediamine-catechol
  • the dummy gate 210 is removed by a suitable method such as wet etching.
  • the dielectric layer 200 underlying the dummy gate 210 may remain as a gate dielectric layer of the semiconductor device.
  • the dielectric layer 200 under the dummy gate 210 is also removed, and the gate dielectric layer is re-formed in a subsequent process step, which can be flexibly selected according to the design of the semiconductor device structure, process specifications, and the like. Since the gate dielectric layer and the gate stack are formed in the inverted frustum-shaped opening 410, even if the bottom width of the inverted frustum-shaped opening is small, since the upper end of the inverted truncated-cone opening has a large width, when the gate stack is formed, It is easy to fill the entire inverted frustum-shaped opening, and no defects such as voids are generated, thereby reducing the process difficulty and improving the yield.
  • step S107 is performed to form a gate and planarize.
  • the dielectric layer 200 may be retained as the gate dielectric layer 420.
  • the dielectric layer 200 is removed in step S106.
  • the gate dielectric layer 420 is reformed, and the material thereof may be Silicon oxide, silicon nitride, silicon oxynitride, or a high K material such as Hf0 2 , HfSiO, HfSiON, HfTaO, Hf iO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO or a combination thereof.
  • the gate dielectric layer 420 may be formed by a CVD or atomic layer deposition (ALD) process. Typically, the gate dielectric layer 420 has a thickness ranging from 2 nm to 10 nm. Then, as shown in FIG. 15, a gate 430 is formed on the gate dielectric layer 420 to fill the opening 410.
  • the gate 430 may be heavily doped polysilicon formed by deposition or a metal layer of a success function.
  • NMOS such as TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x , etc.
  • PMOS such as MoN x , TiSiN, TiCN, TaAlC, TiAIN, TaN, PtSi x , Ni 3 Si, Pt, Ru, Ir, Mo, HfRu, RuO x
  • the gate electrode 430 is formed by doping polysilicon, Ti, Co, Ni, Al, W, or an alloy thereof.
  • CMP chemical mechanical polishing
  • the present invention also provides a semiconductor structure.
  • the semiconductor structure includes a substrate 100, a gate 430, a gate dielectric layer 420, a sidewall spacer 400, and source/drain regions 310.
  • the gate 430 is located above the substrate 100 and has an inverted truncated cone shape with an inverted trapezoidal cross section.
  • the gate dielectric layer 420 is sandwiched between the gate 430 and the substrate 100, or a gate dielectric layer 420 enclosing a sidewall and a bottom of the gate 430; the sidewall 400 is located at a sidewall of the gate 430; the source/drain region 310 is formed in the substrate The two sides of the gate stack.
  • the semiconductor structure further includes a source/drain extension region 300 embedded in the substrate 100 between the source/drain regions 310 and a channel region under the gate.
  • the semiconductor structure with the inverted frustum-shaped gate provided by the invention avoids defects such as voids and voids in the gate, and improves the performance and reliability of the device.

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Abstract

提供一种半导体结构的制造方法，该方法包括以下步骤：提供衬底（100）；在衬底上形成介质层（200）和伪栅层（210）；对伪栅层（210）进行掺杂（001）并退火；对伪栅层（210）进行图形化，以形成伪栅，其中伪栅的顶部截面大于伪栅的底部截面；形成侧墙（400）和源/漏区（310）；沉积层间介质层（500）并对进行平坦化；去除伪栅以在侧墙内形成开口（410）；在开口内形成栅极（430）。相应的，还提供了一种半导体结构。通过形成倒锥台形的伪栅，使得在后续去除伪栅并进行栅极材料填充的过程中，避免了栅极材料中空洞的出现，提高了器件的可靠性。

Description

一种半导体结构及其制造方法
[0001]本申请要求了 2011年 8月 19日提交的、 申请号为 201110238839.5、发 明名称为"一种半导体结构及其制造方法"的中国专利申请的优先权，其全部内 容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体制造领域， 尤其涉及一种半导体结构及其制造方法。 背景技术
[0003】为了提高集成电路芯片的性能和集成度， 器件特征尺寸按照摩尔定 律不断缩小， 目前已经进入纳米尺度。 随着器件尺寸减小， 栅介质层厚度 不断减小， 超薄栅介质导致较严重的栅隧穿电流， 多晶硅栅的耗尽效应也 使得半导体器件的性能和可靠性面临较严重的挑战。采用高 K栅介质 /金属 栅极代替传统的 SiON栅介质 /多晶硅栅，几乎已经成为 45纳米及其以下制 程的必备技术。 具体工艺方面， 高 K/金属栅的制作分为先栅（gate-first ) 工艺和后栅（gate-last )工艺。 在后栅工艺中， 栅极制作在源 /漏区之后， 避 开了源 /漏区退火工序的高温处理， 即避免了高温工艺引起的界面反应和金 属栅功函数改变、 PMOS阈值电压升高等问题。
[0004】在后栅工艺中， 需先形成伪栅， 随后进行源 /漏区离子注入以及退火 操作， 最后去掉伪栅， 填充形成金属栅极。 随着器件特征尺寸不断减小， 半导体器件栅长减小到 20nm及其以下， 如此细小空间内进行栅极填充， 会导致出现空洞空隙等， 影响半导体器件的性能以及可靠性。 发明内容
[0005]本发明旨在至少解决上述技术缺陷， 提供一种半导体器件的制造方 法及其结构， 在进行栅极材料填充的过程中， 减小其工艺难度， 避免出现 空洞， 提高器件的可靠性。 为达上述目的， 本发明提供了一种半导体结构 的制造方法， 该方法包括以下步骤：
( a ) 提供衬底， 在所述衬底上形成介质层和伪栅层； ( b ) 对所述伪栅层进行掺杂并退火；
( c ) 对所述伪栅层进行图形化， 并形成伪栅， 所述伪栅的顶部截面大 于所述伪栅的底部截面；
( d ) 形成侧墙、 源 /漏区；
( e ) 沉积层间介质层并平坦化；
( f ) 去除伪栅以在所述侧墙内形成开口；
( g ) 在所述开口内形成栅极。
[0006】其中， 在步骤（b ) 中， 所述伪栅层形成掺杂离子从表面到内部逐渐 减小的浓度梯度分布， 在后续图形化步骤中， 选择合适的刻蚀方法， 伪栅 层从表面到内部具有逐渐增大的刻蚀速率， 从而可以形成上大下小的类似 倒锥台形的栅极结构。
[0007】本发明另一方面还提出一种半导体结构， 该结构包括衬底、 栅堆叠、 侧墙、 源 /漏区， 其中：
[0008】所述栅堆叠位于所述衬底之上， 包括栅介质层和栅极， 所述栅极的 顶部截面大于所述栅极的底部截面， 所述栅介质层夹于所述栅极和所述衬 底之间， 或所述栅介质层包裹所述栅极的侧壁和底部；
[0009]所述侧墙位于所述栅堆叠的两侧；
[0010]所述源 /漏区形成于所述衬底之中， 位于所述栅堆叠的两侧。
[0011]根据本发明提供的半导体结构及其制造方法，通过形成倒锥台形的栅极 结构， 在去除伪栅后可以实现较好的栅极填充， 避免出现空洞空隙等， 减小其 工艺难度， 提高器件的可靠性。 附图说明
[0012]本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的描 述中将变得明显和容易理解， 其中：
[0013】图 1 是根据本发明的半导体结构的制造方法的一个具体实施方式的 流程图；
[0014] 图 2至图 16为根据图 1示出的方法制造半导体结构过程中该半导体结 构在各个制造阶段的剖面结构示意图； [0015] 图 17是 KOH腐蚀液中<100> Si的腐蚀速率与硼掺杂浓度的关系数据 表。 具体实施方式
[0016]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似 功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本 发明， 而不能解释为对本发明的限制。 下文的公开提供了许多不同的实施 例或例子用来实现本发明的不同结构。 为了筒化本发明的公开， 下文中对 特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在 于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了筒化和清楚的目的， 其本身不指示所讨论各种实施例和 /或 设置之间的关系。 此外， 本发明提供了的各种特定的工艺和材料的例子， 但是本领域普通技术人员可以意识到其他工艺的可应用于性和 /或其他材 料的使用。 另外， 以下描述的第一特征在第二特征之 "上" 的结构可以包 括第一和第二特征形成为直接接触的实施例， 也可以包括另外的特征形成 在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
[0017]图 1为根据本发明的半导体结构制造方法的流程图， 图 2至图 16为根 据本发明的一个实施例，按照图 1所示流程制造半导体结构的各个阶段的剖面 示意图。 下面将结合图 2至图 16对图 1中形成半导体结构的方法进行具体地 描述。 需要说明的是， 本发明实施例的附图仅是为了示意的目的， 因此没 有必要按比例绘制。
[0018】参考图 2至图 4 , 在步骤 S101 中， 提供衬底 100 , 在所述衬底 100 上形成介质层 200和伪栅层 210。
[0019】在本实施例中， 衬底 100包括硅衬底（例如硅晶片）。 根据现有技术公 知的设计要求 (例如 P型衬底或者 N型衬底）， 衬底 100可以包括各种掺杂 配置。 其他实施例中衬底 100还可以包括其他基本半导体， 例如锗， 或化 合物半导体 （如 III - V族材料） ， 例如碳化硅、 砷化镓、 砷化铟。 典型地， 衬底 100可以具有但不限于约几百微米的厚度， 例如可以在 200um-800um 的厚度范围内。
[0020]特别地， 可以在衬底 100中形成隔离区， 例如浅沟槽隔离（STI)结构 110 , 如图 2所示， 以便电隔离连续的场效应晶体管器件。 还可以在所述衬 底 100的表面进行场区注入。
[0021]如图 3所示， 所述介质层 200形成在所述衬底 100上， 可以是氧化 硅、氮化硅，或高 K材料如 Hf02、 HfSiO、 HfSiON, HfTaO , Hf iO、 HfZrO、 A1203、 La203、 Zr02、 LaAlO或其组合。 典型地， 所述介质层 200 的厚度 范围为 2nm~10nm。
[0022]而后，如图 4所示，在所述介质层 200上沉积多晶硅形成伪栅层 210, 其厚度为 10nm~200nm, 可以通过溅射、 化学气相沉积等合适的方法形成 所述多晶硅伪栅层 210。 优选地， 如图 4所示， 还可以在伪栅层 210上形 成硬掩模层 220 , 例如通过沉积氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其 组合形成， 用以保护伪栅层 210的顶部区域。
[0023】参考图 1和图 5 , 执行步骤 S102 , 对所述伪栅层 210进行掺杂并退 火处理。 在本实施例中， 对所述伪栅层 210掺杂进行第一次离子注入 001 形成掺杂分布， 在本发明的另外一些实施例中， 也可以采用扩散的方法进 行掺杂。 所掺杂的元素为硼、 磷或砷。 通过调整离子注入的粒子能量、 电 压、 注入剂量等参数， 结合硬掩膜层 220的阻挡作用， 使得离子注入的浓 度峰值在所述伪栅层 210的上表面上， 随后进行退火处理， 得到在伪栅层 210 中从表面向内逐渐减小的掺杂浓度分布。 所述伪栅层 210表面的掺杂 浓度在 1 X 1019cm-3~l 1021cm"3的范围内。
[0024】参考图 1、 图 6和图 7 , 执行步骤 S 103 , 图形化所述伪栅层， 形成伪 栅极 210 , 所述伪栅极的形状为上大下小的倒锥台形， 其剖面形状为倒梯 形。 图 6所示， 为对所述硬掩膜层 220进行图形化后的剖面图。 图 7所示 为伪栅层图形化后的剖面图。 对所述伪栅层进行刻蚀的方法包括采用氢氧 化钾 （KOH ) 、 四甲基氢氧化铵 ( TMAH ) 或乙二胺-邻苯二酚 (EDP ) 等 进行湿法腐蚀。 图 17所示为 KOH腐蚀液†<100> Si的腐蚀速率与硼掺杂浓 度的关系数据表， 可以看出掺杂浓度小于 1 X 1019cm-3浓度阈值时， 刻蚀速率 基本为常数， 超过该阈值浓度时， 腐蚀速率与掺杂浓度的 4次方成反比， 达到 一定浓度时， 腐蚀速率很小， 甚至可以认为腐蚀停止。 对于磷、 砷等元素的掺 杂， 具有类似的腐蚀速率随掺杂浓度变化的趋势。 优选地， 在本实施例中， 对 所述伪栅层图形化采用 RIE干法刻蚀和湿法腐蚀结合的方法， 首先， 以图形 化的硬掩膜层 220为掩膜， 利用 RIE干法刻蚀伪栅层， 得到的伪栅极具有近 似垂直的侧壁。 随后， 进行湿法腐蚀， 用氢氧化钾（KOH ) 、 四甲基氢氧化 铵 （TMAH ) 或乙二胺-邻苯二酚（EDP ) 等合适的腐蚀液， 通过控制腐蚀 液浓度、 温度、 腐蚀时间等， 得到具有倒锥台形界面的伪栅极 210。
[0025】参考图 1、 图 8〜图 10 ,执行步骤 S 104 ,形成侧墙 400和源 /漏区 310。
[0026】可选地， 在步骤 S104中， 还包括首先形成源 /漏延伸区 300。 通过低 能大角度注入（第二次离子注入 002 ) 的方式在衬底 100中形成较浅的源 / 漏延伸区 300, 可以向衬底 100中注入 P型或 N型掺杂物或杂质， 例如， 对于 PMOS来说， 源 /漏延伸区 300可以是 P型掺杂的 Si; 对于 NMOS来 说， 源 /漏延伸区 300可以是 N型掺杂的 Si。 可选地， 随之对所述半导体结 构进行退火， 以激活源 /漏延伸区 300中的掺杂， 退火可以采用包括快速退 火、 尖峰退火等其他合适的方法形成。 在本发明的其他一些实施例中， 退 火操作也可以放在形成源 /漏区 310之后进行。由于源 /漏延伸区 300的厚度 较浅， 可以有效地抑制短沟道效应。 图 8所示为形成所述源 /漏延伸区 300 后的结构剖面图。 可选地， 还可以进行倾角离子注入以形成 Halo注入区。
[0027]如图 9 所示， 形成源漏延伸区之后则形成侧墙 400。 所述侧墙 400 形成于伪栅极 210的侧壁上， 用于将栅极隔开。 侧墙 400可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的材料， 通过沉积- 刻蚀工艺形成。 侧墙 400 可以具有多层结构， 其厚度范围可以是 10nm -lOOnm, 如 30nm、 50nm或 80nm。
[0028】形成侧墙之后， 则进行重掺杂离子注入以形成源 /漏区 310。 源 /漏区 310位于衬底之中， 如图 10所示， 在所述伪栅极 210的两侧， 可以通过向 衬底 100中注入 P型或 N型掺杂物或杂质而形成。例如，对于 PMOS来说， 源 /漏区 310可以是 P型掺杂的 Si; 对于 NMOS来说， 源 /漏区 310可以是 N型掺杂的 Si。 源 /漏区 310可以由包括光刻、 离子注入、 扩散和 /或其他合 适工艺的方法形成， 在本实施例中通过第三次离子注入 003 形成源 /漏区 310。 随后对所述半导体结构进行退火， 以激活源 /漏区 1 10 中的掺杂， 退 火可以采用包括快速退火、 尖峰退火等其他合适的方法形成。 在本实施例 中， 源 /漏区 310在衬底 100内部， 在其他一些实施例中， 源 /漏区 310可以 是通过选择性外延生长所形成的提升的源漏结构， 其外延部分的顶部高于 伪栅极底部（本说明书中所指的伪栅底部意指伪栅与衬底 100的交界线）。
[0029]可选地， 可以在形成伪栅 210之后将暴露的介质层 200刻蚀去除， 或者在形成源漏区之后， 再将暴露的介质层 200刻蚀去除。
[0030】可选地， 在形成所述源 /漏区 310后， 还可以在所述衬底上沉积一层 金属， 如 Ti、 Pt、 Co、 Ni、 Cu等， 经过退火后在所述源 /漏区 310上形成 硅化物接触层 （未在图中示出） 。
[0031】参考图 1、 图 1 1和图 12 , 执行步骤 S105 , 沉积层间介质层 500 , 并 平坦化。如图 1 1所示，所述层间介质层 500可以通过化学气相沉积 (CVD)、 高密度等离子体 CVD、旋涂和 /或其他合适的工艺等方法形成。 所述层间介 质层 500的材料可以包括氧化硅、 掺杂的氧化硅 (如氟硅玻璃、 硼硅玻璃、 磷硅玻璃、 硼磷硅玻璃）、 低 k电介质材料 (如黑钻石、 coral等）中的一种或 其组合。 所述层间介质层 500的厚度范围可以是 40nm-150nm, 如 80nm、 lOOnm或 120nm, 且可以具有多层结构 （相邻两层间， 材料可以不同） 。
[0032】随后， 对所述层间介质层 500进行平坦化处理， 以暴露出伪栅极 210 的上表面， 如图 12所示。 可以通过化学机械抛光（ CMP )的方法对层间介 质层 500进行研磨减薄， 同时对伪栅极 210上的硬掩膜层 220进行化学机 械抛光， 使得伪栅极 210和层间介质层 500的上表面平齐 （本文件内， 术 语 "齐平，， 意指两者之间的高度差在工艺误差允许的范围内） 。
[0033】参考图 1和图 13 , 执行步骤 S106 , 去除伪栅极 210, 形成开口 410。 可以通过干法 RIE刻蚀、 热碑酸、 氢氟酸 -硝酸 -乙酸（HNA ) 、 氢氧化钾 ( KOH ) 、 四甲基氢氧化铵 ( TMAH ) 或乙二胺-邻苯二酚 (EDP ) 湿法腐 蚀等合适的方法去掉所述伪栅极 210。 位于所述伪栅极 210 下面的介质层 200 可以保留作为半导体器件的栅介质层。 在本实施例中， 位于所述伪栅 极 210下面的介质层 200也被去除， 在后续的工艺步骤中重新形成栅介质 层， 可以根据半导体器件结构的设计、 工艺规范等灵活选择。 [0034】由于在倒锥台形的开口 410 中形成栅介质层和栅极堆叠， 因此即便 倒锥台形开口底部宽度较小， 但由于倒锥台形开口上端宽度较大， 因此在 形成栅极堆叠时容易填满整个倒锥台形开口， 不会产生空隙等缺陷， 从而 降低了工艺难度提高成品率。
[0035】参考图 1、 图 14〜图 16 , 执行步骤 S 107 , 形成栅极并平坦化。 可选 地， 可以保留介质层 200作为栅介质层 420 , 在本实施例中， 所述介质层 200在步骤 S106中被去除， 如图 14所示， 重新形成栅介质层 420 , 其材料 可以是氧化硅、 氮化硅、 氮氧化硅， 或高 K材料如 Hf02、 HfSiO、 HfSiON, HfTaO , Hf iO、 HfZrO、 A1203、 La203、 Zr02、 LaAlO 或其组合。 栅介质 层 420可以通过 CVD或者原子层沉积 (ALD)的工艺来形成。 典型地， 所述 栅介质层 420的厚度范围为 2nm~10nm。 而后如图 15所示， 在所述栅介质 层 420上形成栅极 430 , 填充所述开口 410 , 所述栅极 430可以是通过沉积 形成的重掺杂多晶硅，或是先形成功函数金属层（对于 NMOS ,例如 TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax等， 对于 PMOS, 例 ^口 MoNx, TiSiN, TiCN, TaAlC, TiAIN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuOx ), 其厚度可以为 lnm-20nm,如 3nm、 5nm、 8nm、 10nm、 12nm或 15nm, 再在所述功函数金属层上形成重掺杂多晶硅、 Ti、 Co、 Ni、 Al、 W或其合金 等而形成栅极 430。 最后， 执行化学机械抛光（CMP )平坦化处理， 使所述栅 极 430与层间介质层 500的上表面齐平， 形成栅极堆叠结构， 参考图 16。
[0036]随后按照常规半导体制造工艺的步骤完成改半导体结构的制造， 例 如， 沉积介质层以覆盖所述源 /漏区和栅极堆叠； 刻蚀所述层间介质层暴露 源 /漏区以形成接触孔， 在所述接触孔中填充金属； 以及后续的多层金属互 连等工艺步骤。
[0037】本发明还提供了一种半导体结构， 如图 16所示， 所述半导体结构包 括衬底 100、 栅极 430、 栅介质层 420、 侧墙 400、 源 /漏区 310。 其中所述 栅极 430位于所述衬底 100之上， 呈倒锥台形， 其剖面为倒梯形； 所述栅 介质层 420夹于所述栅极 430和所述衬底 100之间， 或所述栅介质层 420 包裹所述栅极 430的侧壁和底部； 所述侧墙 400位于所述栅极 430的侧壁； 所述源 /漏区 310形成于所述衬底之中，位于所述栅极堆叠的两侧。可选地， 该半导体结构还包括源 /漏延伸区 300 , 所述源 /漏延伸区 300嵌于所述衬底 100中， 位于所述源 /漏区 310和栅极之下的沟道区之间。 本发明提供的具 有倒锥台形栅极的半导体结构， 避免了在栅极中出现空洞、 空隙等缺陷， 提高器件的性能和可靠性。
[0038] 虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明 的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种 变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理解在保 持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0039]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领 域的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发出的工 艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明描述 的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它 们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、 机构、 制造、 物质 组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种半导体结构的制造方法， 该方法包括以下步骤：
(a)提供衬底， 在所述衬底上形成介质层和伪栅层；
(b)对所述伪栅层进行掺杂并退火；
(c)对所述伪栅层进行图形化， 并形成伪栅， 所述伪栅的顶部截面大 于所述伪栅的底部截面；
(d) 形成侧墙、 源 /漏区；
(e) 沉积层间介质层并平坦化；
(f) 去除伪栅以在所述侧墙内形成开口；
(g) 在所述开口内形成栅极。
2、 根据权利要求 1 所述的方法， 步骤 （b) 中， 掺杂的方法为扩散或 离子注入， 掺杂的离子为硼、 磷或砷。
3、 根据权利要求 1 所述的方法， 步骤 （b) 中， 所述伪栅层表面的掺 杂浓度为 1 X 1019cm-3~l X 1021cm-3, 经过退火， 在所述伪栅层中， 形成掺杂 离子从表面到内部逐渐减小的浓度梯度分布。
4、 根据权利要求 1或 3所述的方法， 步骤（c) 中， 图形化所述伪栅 层形成伪栅的方法为：
在所述伪栅层上形成硬掩模层， 所述硬掩模层对应将要形成的伪栅顶 部形状；
采用 KOH、 TMAH或 EDP对暴露的伪栅层进行湿法腐蚀。
5、 根据权利要求 4所述的方法， 在进行湿法腐蚀之前， 还包括采用反 应离子刻蚀所述暴露的伪栅层。
6、 根据权利要求 1所述的方法， 其中，
步骤（d) 中形成源漏区之前， 还包括形成源 /漏延伸区；
步骤（d)在形成源漏区之后， 还包括在源 /漏区表面形成硅化物接触。
7、 根据权利要求 6所述的方法， 步骤 （c) 形成伪栅之后或步骤 （d) 形成硅化物接触之前， 还包括去除暴露的所述介质层。
8、 根据权利要求 1 所述的方法， 步骤 （f) 中， 还包括去除位于所述 伪栅下面的介质层。
9、 根据权利要求 1或 8所述的方法， 步骤（g ) 中， 在形成栅极之前 还包括， 在所述开口中形成栅介质层， 所述栅介质层的材料为氧化硅、 氮 化硅、 Hf02、 HfSiO、 HfSiON, HfTaO , Hf iO、 HfZrO、 A1203、 La203、 Zr02、 LaAlO或其组合。
10、 一种半导体结构， 该结构包括衬底、 栅堆叠、 侧墙、 源 /漏区， 其 中：
所述栅堆叠位于所述衬底之上， 包括栅介质层和栅极， 所述栅极的顶 部截面大于所述栅极的底部截面， 所述栅介质层夹于所述栅极和所述衬底 之间， 或所述栅介质层包裹所述栅极的侧壁和底部；
所述侧墙位于所述栅堆叠的两侧；
所述源 /漏区形成于所述衬底之中， 位于所述栅堆叠的两侧。
11、 根据权利要求 10所述的半导体结构， 其中， 所述栅极的侧壁与所 述衬底之间的夹角为 45° ~ 85 ° 。
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