WO2011044776A1 - 半导体器件的形成方法 - Google Patents

半导体器件的形成方法 Download PDF

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Publication number
WO2011044776A1
WO2011044776A1 PCT/CN2010/074205 CN2010074205W WO2011044776A1 WO 2011044776 A1 WO2011044776 A1 WO 2011044776A1 CN 2010074205 W CN2010074205 W CN 2010074205W WO 2011044776 A1 WO2011044776 A1 WO 2011044776A1
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Prior art keywords
dielectric layer
dummy gate
substrate
gate structure
forming
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PCT/CN2010/074205
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English (en)
French (fr)
Inventor
朱慧珑
王文武
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中国科学院微电子研究所
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Priority to US12/922,391 priority Critical patent/US8329566B2/en
Publication of WO2011044776A1 publication Critical patent/WO2011044776A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation

Definitions

  • the present invention generally relates to a method of forming a semiconductor device. More specifically, it relates to a method for forming a semiconductor device having a steep inverted doped well on a semiconductor substrate.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • SCE short channel effect
  • a solution to improve the short channel effect by forming a steep inverted doped well in the substrate can be used to reduce the short channel effect.
  • This approach is based on the formation of a steep inverted doped well in the channel to reduce the thickness of the under-gate depletion layer, thereby reducing the short channel effect. It is usually required that the doped wells have a very steep distribution for good results.
  • rapid photothermal annealing or spike annealing is often used to activate impurities and remove defects caused by ion implantation into the source/drain regions.
  • the thermal budget for annealing the source and drain regions and the source/drain extension regions is too large, and the temperature and time required for such annealing to form atomic diffusion is much greater than that required to anneal only the dopants in the channel region. .
  • This disadvantageously causes the dopant atoms in the channel region to diffuse too much, thereby destroying the steep underdoping distribution.
  • the present invention provides a method of fabricating a semiconductor device, the method comprising: Providing a substrate; forming a source region, a drain region, a dummy gate structure disposed on the substrate between the source region and the drain region, and forming a lining on the substrate a gate dielectric layer between the bottom and dummy gate structures; annealing the source and drain regions; removing the dummy gate structure to form an opening; ion implantation of the substrate from the opening to form a steep An inverted doped well; laser annealing the device to activate impurities; depositing on the gate dielectric layer to form a metal gate. It is also possible to use a flash anneal to anneal the device to activate impurities.
  • the wells are activated by laser annealing for impurities in the doped well, and thus the destruction of the steepness of the inverted doped well due to thermal annealing of the source/drain regions and the extension regions is advantageously avoided.
  • the present invention can reduce the leakage current between the band and reduce the depth of the depletion layer of the channel region of the semiconductor device, the power consumption and the short channel effect can be better reduced.
  • FIG. 1 shows a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention
  • FIGS. 2-7 illustrate structural views of a semiconductor device in accordance with various aspects of the present invention. detailed description
  • the present invention generally relates to a method of fabricating a semiconductor device, and more particularly to a method for forming a semiconductor device having a steep inverted doped well on a semiconductor substrate.
  • the following disclosure provides many different embodiments or examples for implementing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • FIG. 1 there is shown a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.
  • substrate 202 includes a silicon substrate (e.g., a wafer) in a crystal structure.
  • the substrate 202 can include various doping configurations in accordance with design requirements well known in the art, such as a p-type substrate or an n-type substrate. Other examples of substrate 202 may also include other basic semiconductors such as germanium and diamond. Alternatively, substrate 202 may comprise a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium telluride. Additionally, substrate 202 can optionally include an epitaxial layer that can be altered by stress to enhance performance, and can include a silicon-on-insulator (SOI) structure.
  • SOI silicon-on-insulator
  • a source region 204, a drain region 206, a dummy gate structure disposed between the source region and the drain region on the substrate, and a dummy gate structure are formed on the substrate 202.
  • a gate dielectric layer 212 is between the substrate and the dummy gate structure 208.
  • a successful function metal gate layer 210 is formed between the gate dielectric layer 212 and the dummy gate structure 208.
  • the dummy gate structure 208 is a sacrificial layer.
  • the dummy gate structure 208 can be, for example, polysilicon.
  • the dummy gate structure comprises amorphous silicon.
  • the dummy gate structure can be formed by MOS (Metal Oxide Semiconductor) technology processes such as polysilicon deposition, photolithography, etching, and/or other suitable methods.
  • Gate dielectric layer 212 can comprise a high dielectric constant (high k) material.
  • the high k material comprises hafnium oxide (HfO 2 ).
  • Other examples of high k materials include HfSiO, HfSiON, HfTaO, HffiO, HfZrO, combinations thereof, and/or other suitable materials.
  • Gate dielectric layer 212 can include a thickness between about 15 angstroms and 40 angstroms.
  • the gate dielectric layer 212 may be formed by a process such as thermal oxidation, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
  • the gate dielectric layer 212 can also have a multilayer structure including one or more layers having the above materials.
  • a work function metal gate layer 210 may be deposited thereon after the gate dielectric layer 212 is formed.
  • the work function metal gate layer can include a thickness ranging between about 30 angstroms and about 150 angstroms. Materials for the work function metal gate layer may include TiN and TaN.
  • Sidewalls 214 may be formed on both sidewalls of the dummy gate structure 208.
  • the sidewall spacers 214 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride doped silicon glass, low k dielectric materials, combinations thereof, and/or other suitable materials.
  • the side wall 214 may have a multi-layered structure.
  • Side source/drain regions 204, 206 may be implanted or n depending on the desired transistor structure A type of dopant or impurity is formed into the substrate 202.
  • Source/drain regions 204, 206 may be formed by methods including photolithography, ion implantation, diffusion, and/or other suitable processes.
  • Source and drain 204, 206 may be formed prior to gate dielectric layer 212.
  • a stop layer 216 covering the semiconductor device may be formed on the semiconductor device, with reference to FIG.
  • the stop layer may comprise Si 3 N 4 , silicon oxynitride, silicon carbide, and/or other suitable materials.
  • the stop layer 216 can be formed using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other suitable processes.
  • the stop layer 216 has a thickness in the range of about 50 to 200 angstroms.
  • Dielectric layer 218 may be formed on stop layer 216 by chemical vapor deposition (CVD), high density plasma CVD, spin coating, sputtering, or other suitable method, as shown in FIG.
  • Dielectric layer 218 may comprise silicon oxide, silicon oxynitride or a low k material.
  • the dielectric layer 218 is formed using a material that is less rigid than the material of the stop layer 216 to stop on the stop layer 216 during subsequent chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • step 103 the source/drain regions are annealed.
  • the annealing can be carried out using processes known to those skilled in the art including rapid thermal annealing, spike annealing, and the like.
  • the dummy gate structure 208 can be removed such that the resulting metal gate can be formed to replace the dummy gate structure 208. Therefore, the dielectric layer 218 can be planarized by a chemical mechanical polishing process until the stop layer 216 is exposed, as shown in FIG. The exposed stop layer 216 is then selectively etched to expose the dummy gate structure 208, as shown in FIG. The stop layer 216 can be removed using wet etching and/or dry etching. Subsequently, the dummy gate structure 208 is removed, thereby providing the device 600 as shown in FIG. For example, polysilicon is selectively etched and stopped on the work function metal gate layer 210 to remove the dummy gate structure 208 and form the opening 220.
  • the dummy gate structure 208 can be removed using wet etching and/or dry etching.
  • the wet etch process includes including a solution (e.g., ammonium hydroxide), deionized water, and/or other suitable etchant solution to the hydrogen.
  • a group III element is used for ion implantation, such as boron and indium
  • a group VI element is used for the example implantation, germanium and phosphorus.
  • the ion implantation energy that can be used ranges from about 3 to 25 keV, the dose is about 5el3 to 2el4, and the depth of implantation is about 10-25 nm.
  • the device is laser annealed to activate impurities in the inverted doped well.
  • the device is typically annealed using a transient annealing process, such as subtle laser annealing at temperatures above about 1350 °C.
  • FIG. 7 shows device 700, which includes a metal gate 222 deposited into opening 220 for adjusting a threshold voltage.
  • the metal gate material can include one or more layers of material, such as a liner, a material that provides a suitable work function to the gate, a gate electrode material, and/or other suitable materials.
  • one or more elements may be selected from the group consisting of: TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x , and combinations of these materials;
  • one or more elements may be selected from the group consisting of: MoN x , TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni 3 Si, Pt, Ru, Ir, Mo , Hf u, RuO x and combinations of these materials.
  • a chemical mechanical polishing (CMP) process is performed on device 700 to form metal gate 222 and provide device 700.
  • CMP chemical mechanical polishing
  • a steep inverted doped well and a deposited metal gate 222 are formed in device 700.
  • the wells are activated by laser annealing for impurities in the inverted doped well, thereby advantageously avoiding the damage to the steepness of the inverted doped well distribution caused by thermal annealing of the source/drain regions and the extension regions.
  • the invention reduces the depth of the depletion layer of the channel region of the semiconductor device, the short channel effect can be well controlled, and at the same time, since the doped well distribution does not overlap with the doping of the source/drain regions, the reduction can be reduced. Band-to-leakage current in CMOSFET devices.

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Description

半导体器件的形成方法
技术领域
本发明通常涉及一种半导体器件的形成方法。 更具体而言， 涉及一种用于 在半导体衬底上形成具有陡峭的倒掺杂阱的半导体器件的方法。
背景技术
随着半导体行业的发展，具有更高性能和更强功能的集成电路要求更大的 元件密度， 而且各个部件、元件之间或各个元件自身的尺寸、 大小和空间也需 要进一步缩小。 相应地， 为了提高 MOSFET (金属氧化物半导体场效应晶体 管） 器件的性能需要进一步减少 MOSFET器件的栅长。 然而随着栅长持续减 小， 减少到接近源极和漏极的耗尽层的宽度， 例如小于 40nm时， 将会产生较 严重的短通道效应（ short channel effect 或简写为 SCE ), 从而不利地降低器件 的性能，给大规模集成电路的生产造成困难。如何降低短通道效应以及有效地 控制短通道效应， 已经成为集成电路大规模生产中的一个很关键的问题。
一种通过在衬底中形成陡峭的倒掺杂阱来改善短通道效应的方案可以用 来减少短通道效应。此方案是基于在沟道中形成陡峭的倒掺杂阱以减小栅极下 耗尽层的厚度， 进而减少短通道效应。通常要求倒掺杂阱要有很陡峭的分布以 达好的效果。 但是由于快速光热退火或尖峰退火经常用于激活杂质以及去除 对源 /漏区离子注入所导致的缺陷。 而源极区和漏极区以及源 /漏延伸区退火的 热预算太大，这种退火形成原子扩散所需的温度和时间远远大于仅对沟道区中 的掺杂剂进行退火所需。 因此不利地导致沟道区中的掺杂原子扩散过大，从而 破坏陡峭的倒掺杂分布。
因此， 为了改进高性能半导体器件的制造， 需要一种制造陡峭的倒掺杂分 布的方法。
发明内容
鉴于上述问题，本发明提出了一种制造半导体器件的方法，所述方法包括: 提供一个衬底； 在衬底上形成源极区、 漏极区、 设置在所述衬底上位于所 述源极区和所述漏极区之间的伪栅极结构和形成在所述衬底和伪栅极结构 之间栅极介质层； 对所述源极区和漏极区进行退火； 去除所述伪栅极结构以 形成开口； 从所述开口对衬底进行离子注入以形成陡峭的倒掺杂阱； 对所述器 件进行激光退火，以激活杂质；在所述栅极介质层上进行沉积以形成金属栅极。 其中也可以釆用闪光退火， 对所述器件进行退火， 以激活杂质。 杂阱， 并利用激光退火针对倒掺杂阱中的杂质进行激活， 而因此有利地避 免了对源 /漏极区及延伸区进行热退火而导致的对倒掺杂阱分布陡峭度的破 坏。 同时由于本发明可减少能带间漏电流和减小了半导体器件沟道区耗尽 层的深度， 因此可以较好地减小功耗和控制短通道效应。 附图说明
图 1示出了根据本发明的实施例的半导体器件的制造方法的流程图； 图 2-7示出了根据本发明的不同方面的半导体器件的结构图。 具体实施方式
本发明通常涉及一种半导体器件的制造方法， 尤其涉及一种用于在半 导体衬底上形成具有陡峭的倒掺杂阱的半导体器件的方法。 下文的公开提供 了许多不同的实施例或例子用来实现本发明的不同结构。 为了简化本发明 的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示 例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参 考数字和 /或字母。 这种重复是为了简化和清楚的目的， 其本身不指示所讨 论各种实施例和 /或设置之间的关系。 此外， 本发明提供了的各种特定的工 艺和材料的例子， 但是本领域普通技术人员可以意识到其他工艺的可应用 于性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上" 的结构可以包括第一和第二特征形成为直接接触的实施例， 也可以包括另 外的特征形成在第一和第二特征之间的实施例， 这样第一和第二特征可能 不是直接接触。 参考图 1 , 图 1示出了根据本发明的实施例的半导体器件的制造方法的流 程图。 在步骤 101 , 首先提供一个半导体衬底 202, 参考图 2。 在本实施例中， 衬底 202 包括位于晶体结构中的硅衬底 （例如晶片 ) 。 根据现有技术公知 的设计要求 （例如 p型衬底或者 n型衬底） ， 衬底 202可以包括各种掺杂 配置。 其他例子的衬底 202还可以包括其他基本半导体， 例如锗和金刚石。 或者， 衬底 202 可以包括化合物半导体， 例如碳化硅、 砷化镓、 砷化铟或 者碑化铟。 此外， 衬底 202可以可选地包括外延层， 可以被应力改变以增 强性能， 以及可以包括绝缘体上硅（SOI ) 结构。
在步骤 102, 在衬底 202上形成源极区 204、 漏极区 206、 设置在所述 衬底上位于所述源极区和所述漏极区之间的伪栅极结构和形成在在所述衬 底和伪栅极结构 208之间栅极介质层 212。 在一些实施例中在所述栅极介 质层 212和所述伪栅极结构 208之间形成功函数金属栅层 210。
伪栅极结构 208为牺牲层。 伪栅极结构 208可以例如为多晶硅。 在一 个实施例中， 伪栅极结构包括非晶硅。 伪栅极结构可以由 MOS (金属氧化 物半导体)技术工艺， 例如多晶硅沉积、 光刻、 蚀刻及 /或其他合适的方法形 成。 栅极介质层 212可以包括高介电常数（高 k ) 材料。 在一个实施例中， 高 k材料包括二氧化铪（Hf02 )。其他例子的高 k材料包括 HfSiO、 HfSiON、 HfTaO, HffiO , HfZrO及其组合， 以及 /或者其他合适的材料。 栅极介质层 212可以包括大约 15埃到 40埃范围之间的厚度。栅极介质层 212可以通过 例如热氧化、 化学气相沉积（CVD )或者原子层沉积（ALD ) 的工艺来形成。 栅极介质层 212还可以具有多层结构， 包括具有上述材料的一个以上的层。特 别地， 在形成栅极介质层 212之后可以在其上沉积功函数金属栅层 210。 功函 数金属栅层可以包括在大约 30埃到大约 150埃范围之间的厚度。 用于功函 数金属栅层的材料可以包括 TiN以及 TaN。
侧墙 214可以形成在伪栅极结构 208的两个侧壁上。 侧墙 214可以由 氮化硅、 氧化硅、 氮氧化硅、 碳化硅、 氟化物掺杂硅玻璃、 低 k电介质材 料及其组合， 和 /或其他合适的材料形成。 侧墙 214可以具有多层结构。 侧 源 /漏极区 204、 206可以通过根据期望的晶体管结构， 注入 型或 n 型掺杂物或杂质到衬底 202 中而形成。 源 /漏极区 204、 206可以由包括光 刻、 离子注入、 扩散和 /或其他合适工艺的方法形成。 源极和漏极 204、 206 可以先于栅极介质层 212形成。
特别地， 可以在所述半导体器件上形成覆盖所述半导体器件的停止层 216, 参考图 3。 所述停止层可以包括 Si3N4、 氮氧化硅、 碳化硅及 /或其他合 适材料。 停止层 216可以使用例如化学气相沉积 （CVD ) 、 物理气相沉积 ( PVD ) 、 原子层沉积 （ALD )及 /或其他合适的工艺等方法形成。 在一个 实施例中， 停止层 216的厚度范围为大约 50到 200埃。
介质层 218 , 可以通过化学气相沉积（CVD )、 高密度等离子体 CVD、 旋涂、 溅射或其他合适的方法形成在停止层 216上， 如图 4所示。 介质层 218 可以包括氧化硅、 氮氧化硅或者低 k材料。 特别地， 釆用相比停止层 216的材料硬度更小的材料来形成介质层 218 , 以便在随后进行的化学机械 抛光（ CMP ) 时停止在所述停止层 216上。
而后方法进行到步骤 103 ,在该步骤中对所述源 /漏极区进行退火。所述退 火可以釆用包括快速热退火、 尖峰退火等本领域技术人员所知晓的工艺进行。
在步骤中 104中， 伪栅极结构 208可以被移除，从而产生的金属栅极可 以形成以取代伪栅极结构 208。 因此， 可以通过化学机械抛光工艺对介质 层 218进行平整化， 直至暴露停止层 216 , 如图 4所示。 而后选择性地刻 蚀所述暴露的停止层 216, 以便暴露伪栅极结构 208 , 如图 5所示。 停止层 216 可以使用湿蚀刻和 /或干蚀刻除去。 随后， 除去伪栅极结构 208 , 从而 提供如图 6所示的器件 600。 例如， 选择性地蚀刻多晶硅并停止在功函数 金属栅层 210上来除去伪栅极结构 208并形成开口 220。 伪栅极结构 208 可以使用湿蚀刻和 /或干蚀刻除去。 在一个实施例中， 湿蚀刻工艺包括向氢 氧包含溶液（例如氢氧化铵） 、 去离子水以及 /或者其他合适蚀刻剂溶液。
然后步骤进行到 105 , 在该步骤中从所述开口 220对衬底进行离子注 入， 以形成陡峭的倒掺杂阱， 参考图 6。 对于 N型半导体器件， 使用 III族 元素进行离子注入， 例如硼和铟； 对于 P型半导体器件， 使用 VI族元素进行 例子注入， 紳和磷。 可以釆用的离子注入能量的范围大约为 3-25keV, 剂量大 约为 5el3-2el4 , 注入的深度范围大约为 10-25nm。 在步骤 106 , 对器件进行激光退火， 以激活倒掺杂阱中的杂质。 在其他的 实施例中可以釆用其他的退火工艺， 如闪光退火等。 根据本发明的实施例， 通 常釆用瞬间退火工艺对器件进行退火， 例如在大约 1350°C以上的温度进行微 妙级激光退火。
在步骤 107 , 在所述栅极介质层上进行沉积以形成金属栅极。 图 7显示 了器件 700 , 器件 700 包括沉积到开口 220 中的、 用于调节阔值电压的金 属栅极 222。 金属栅极材料可以包括一个或多个材料层， 例如衬层， 向栅 极提供合适功函数的材料， 栅电极材料和 /或其他合适材料。 对于 N型半导 体器件可以从包含下列元素的组中选择一种或多种元素进行沉积： TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax及这些材料 的组合；对于 P型半导体器件可以从包含下列元素的组中选择一种或多种元素 进行沉积： MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 Hf u、 RuOx及这些材料的组合。
最后在步骤 108, 在器件 700上执行化学机械抛光 （CMP ) 工艺， 以 形成金属栅极 222并提供器件 700。 器件 700 中形成有陡峭的倒掺杂阱和 沉积的金属栅极 222。 杂阱， 并利用激光退火针对倒掺杂阱中的杂质进行激活， 而因此有利地避 免了对源 /漏极区及延伸区进行热退火而导致的对倒掺杂阱分布陡峭度的破 坏。 同时由于本发明减小了半导体器件沟道区耗尽层的深度， 因此可以较 好地控制短通道效应， 同时， 由于倒掺杂阱分布不与源 /漏极区的掺杂重叠， 能够减少 CMOSFET器件中的带-带泄漏电流。
虽然关于示例实施例及其优点已经详细说明 ,应当理解在不脱离本发明的 精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变 化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理解在保持 本发明保护范围内的同时， 工艺步骤的次序可以变化。
此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机 构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领域 的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明描述的对 应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进 行应用。 因此， 本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种制造半导体器件的方法， 所述方法包括：
a )提供一个衬底；
b )在衬底上形成源极区、 漏极区、 设置在所述衬底上位于所述源极区 和所述漏极区之间的伪栅极结构和形成在所述衬底和伪栅极结构之间的栅 极介质层；
c )对所述源极区和漏极区进行退火；
d )去除所述伪栅极结构以形成开口；
e ) 从所述开口对衬底进行离子注入以形成陡峭的倒掺杂阱；
f )进行激光退火， 以激活杂质；
g )在所述栅极介质层上进行沉积以形成金属栅极。
2、 根据权利要求 1所述的方法， 其中所述步骤 f为： 进行闪光退火， 以 激活杂质。
3、 根据权利要求 1或 2所述的方法， 其中， 所述进行离子注入以形成陡 峭的倒掺杂阱的步骤包括： 对于 N型半导体器件， 使用 III族元素进行离子注 入； 对于 P型半导体器件， 使用 VI族元素进行例子注入。
4、 根据权利要求 3所述的方法， 其中， 所述 III族元素包括硼和铟， 所述 VI族元素包括紳和磷， 离子注入能量为 3-10keV, 剂量为 5el3-2el4。
5、 根据权利要求 1 或 2 所述的方法， 其中所述离子注入的深度范围为 10-25匪。
6、 根据权利要求 3所述的方法， 其中， 所述 VI族元素包括碑和砷， 所述 VI族元素包括紳和磷， 离子注入能量为 3-25keV, 剂量为 5el3-2el4。
7、 根据权利要求 1 或 2 所述的方法， 其中所述离子注入的深度范围为 10-25匪。
8、 根据权利要求 1或 2所述的方法， 其中在栅极介质层上形成金属栅极 的步骤还包括： 对于 N型半导体器件从包含下列元素的组中选择元素进行沉 积： TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax;对于 P型半导体器件从包含下列元素的组中选择元素进行沉积： MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 魔 u、
RuOx„
9、根据权利要求 1或 2所述的方法，其中在衬底上形成源极区、漏极区、 伪栅极结构以及栅极介质层的步骤还包括在所述栅极介质层和伪栅极结构 之间形成功函数金属栅层。
10、 根据权利要求 1或 2所述的方法， 在衬底上形成源极区、 漏极区、 伪栅极结构以及栅极介质层的步骤还包括在所述伪栅极结构的侧壁形成侧 墙。
11、 根据权利要求 1或 2所述的方法， 还包括如下步骤： 在去除所述伪栅 极结构的步骤前形成覆盖所述半导体器件的停止层。
12、 根据权利要求 11所述的方法， 还包括在所述停止层上形成介质层。
13、 根据权利要求 12所述的方法， 其中去除伪栅极结构的步骤包括进行 化学机械抛光以停止在所述停止层上 ,并且选择性刻蚀所述停止层以暴露所述 伪栅极结构。
14、 所述根据权利要求 12所述的方法， 其中所述停止层从包含下列元素 的组中选择： Si3N4、 氮氧化硅、 碳化硅及其组合； 所述介质层从包含下列元 素的组中选择： 氧化硅、 氮氧化硅及其组合。
15、 根据权利要求 14所述的方法， 其中形成所述停止层的材料具有比形 成所述介质层的材料更大的硬度。
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386095B (zh) * 2010-08-31 2014-05-07 中国科学院微电子研究所 半导体结构的制造方法
US9202913B2 (en) 2010-09-30 2015-12-01 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor structure
CN102446761B (zh) * 2010-09-30 2015-07-15 中国科学院微电子研究所 半导体结构的制造方法
CN102593172B (zh) * 2011-01-14 2015-05-06 中国科学院微电子研究所 半导体结构及其制造方法
CN102623405B (zh) * 2011-01-30 2014-08-20 中国科学院微电子研究所 一种形成半导体结构的方法
CN102651319B (zh) * 2011-02-24 2014-09-03 中芯国际集成电路制造(上海)有限公司 晶体管的制造方法
CN102800578A (zh) * 2011-05-27 2012-11-28 中国科学院微电子研究所 一种半导体结构的制造方法
CN102820228A (zh) * 2011-06-10 2012-12-12 中国科学院微电子研究所 半导体器件的制备方法
CN102891076B (zh) * 2011-07-22 2016-03-16 中芯国际集成电路制造(上海)有限公司 Mos晶体管的结构及其形成方法
CN102931086B (zh) * 2011-08-10 2015-07-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN102956459B (zh) * 2011-08-26 2016-04-13 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
JP5968708B2 (ja) 2012-01-23 2016-08-10 ルネサスエレクトロニクス株式会社 半導体装置
CN103426756B (zh) 2012-05-15 2016-02-10 中国科学院微电子研究所 半导体器件及其制造方法
CN103779196B (zh) 2012-10-19 2016-07-06 中国科学院微电子研究所 半导体器件及其制造方法
CN103779225B (zh) * 2012-10-23 2017-02-22 中国科学院微电子研究所 半导体器件及其制造方法
CN104347707B (zh) * 2013-08-06 2018-01-30 中国科学院微电子研究所 一种mosfet结构及其制造方法
CN104733303B (zh) * 2013-12-18 2017-12-01 中芯国际集成电路制造(上海)有限公司 伪栅的去除方法和mos晶体管的形成方法
CN104795331B (zh) * 2014-01-21 2018-08-10 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN104979174B (zh) * 2014-04-03 2018-03-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件的形成方法
CN105097687B (zh) * 2014-05-04 2017-11-03 中芯国际集成电路制造(上海)有限公司 Cmos晶体管的形成方法
CN105225937B (zh) * 2014-06-30 2018-03-30 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN107785267B (zh) * 2016-08-29 2020-09-08 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
TWI798215B (zh) * 2017-04-20 2023-04-11 美商微材料有限責任公司 選擇性側壁間隔物
CN113394110A (zh) * 2021-05-31 2021-09-14 上海华力集成电路制造有限公司 Hkmg结构制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300201B1 (en) * 2000-03-13 2001-10-09 Chartered Semiconductor Manufacturing Ltd. Method to form a high K dielectric gate insulator layer, a metal gate structure, and self-aligned channel regions, post source/drain formation
US6391728B1 (en) * 2001-03-12 2002-05-21 Advanced Micro Devices, Inc. Method of forming a highly localized halo profile to prevent punch-through
US20060148150A1 (en) * 2005-01-03 2006-07-06 Kavalieros Jack T Tailoring channel dopant profiles

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482724B1 (en) * 1999-09-07 2002-11-19 Texas Instruments Incorporated Integrated circuit asymmetric transistors
KR100372641B1 (ko) 2000-06-29 2003-02-17 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 제조방법
JP2002118261A (ja) 2000-10-05 2002-04-19 Seiko Epson Corp 半導体装置及びその製造方法
JP4971559B2 (ja) * 2001-07-27 2012-07-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6908850B2 (en) * 2003-09-10 2005-06-21 International Business Machines Corporation Structure and method for silicided metal gate transistors
EP1738405A1 (en) * 2004-03-16 2007-01-03 Koninklijke Philips Electronics N.V. Field effect transistor and method of manufacturing a field effect transistor
US20070141775A1 (en) * 2005-12-15 2007-06-21 Chartered Semiconductor Manufacturing, Ltd. Modulation of stress in stress film through ion implantation and its application in stress memorization technique
US7456068B2 (en) * 2006-06-08 2008-11-25 Intel Corporation Forming ultra-shallow junctions
US8329564B2 (en) * 2007-10-26 2012-12-11 International Business Machines Corporation Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300201B1 (en) * 2000-03-13 2001-10-09 Chartered Semiconductor Manufacturing Ltd. Method to form a high K dielectric gate insulator layer, a metal gate structure, and self-aligned channel regions, post source/drain formation
US6391728B1 (en) * 2001-03-12 2002-05-21 Advanced Micro Devices, Inc. Method of forming a highly localized halo profile to prevent punch-through
US20060148150A1 (en) * 2005-01-03 2006-07-06 Kavalieros Jack T Tailoring channel dopant profiles

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