WO2013071656A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2013071656A1
WO2013071656A1 PCT/CN2011/083331 CN2011083331W WO2013071656A1 WO 2013071656 A1 WO2013071656 A1 WO 2013071656A1 CN 2011083331 W CN2011083331 W CN 2011083331W WO 2013071656 A1 WO2013071656 A1 WO 2013071656A1
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Prior art keywords
layer
source
amorphous silicon
contact
gate stack
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PCT/CN2011/083331
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English (en)
French (fr)
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尹海洲
蒋葳
许高博
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中国科学院微电子研究所
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Priority to US13/989,808 priority Critical patent/US20130240990A1/en
Publication of WO2013071656A1 publication Critical patent/WO2013071656A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Definitions

  • the present invention relates to semiconductor fabrication techniques, and more particularly to a semiconductor structure and method of fabricating the same. Background technique
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the gate dielectric layer of the MOSFET is composed of a high-k dielectric material, the gate leakage current can be effectively reduced, but the molecular structure of the high-k gate dielectric layer may be slightly defective when the high-k gate dielectric layer is initially formed. In order to repair this defect, it needs to be annealed at a higher temperature (600 ° C - 800 ° C). In addition, annealing the high-k gate dielectric layer can also improve transistor reliability.
  • a replacement gate process depositing a high-k gate dielectric layer is typically performed after removing the dummy gate, such as after an interlayer dielectric layer has been deposited. If the metal silicide of the source and drain regions has been formed at this time, since the high temperature is required for annealing the high-k dielectric layer, the structure of the metal silicide layer changes at a high temperature, thereby causing an increase in the resistivity of the metal silicide layer, thereby reducing The performance of the transistor.
  • Forming a transistor having a sacrificial gate on a substrate depositing a first interlayer dielectric layer on the substrate; removing the sacrificial gate to form a gate trench; depositing a high K in the gate trench a dielectric layer; annealing the high-k dielectric layer; depositing a metal layer in the gate trench; Depositing a second interlayer dielectric layer on the first interlayer dielectric layer and the transistor; etching the first interlayer dielectric layer and the second interlayer dielectric layer to form a source and a drain respectively a contact trench and a second contact trench; depositing a second metal layer in the first contact trench and the second contact trench; annealing the second metal layer, the source and Forming a metal silicide layer on the drain; and depositing a third metal layer to fill the first contact trench and the second contact trench.
  • a contact layer e.g., a metal silicide layer
  • the metal silicide layer is prevented from being destroyed at a high temperature.
  • the above method can not destroy the metal silicide layer when annealing the high-k gate dielectric layer
  • the limitation of the method is that a metal silicide layer can be formed only between the contact trench and the source/drain regions.
  • the area of the source/drain region covered with the metal silicide is limited in area, so that the contact resistance of the metal silicide layer of the transistor cannot be sufficiently reduced. Therefore, how to reduce the contact resistance of a contact layer (such as a metal silicide layer) has become an urgent problem to be solved. Summary of the invention
  • One object of the present invention is to provide a semiconductor structure and a method of fabricating the same that facilitates reducing the contact resistance of a source/drain contact layer (e.g., a metal silicide layer).
  • a source/drain contact layer e.g., a metal silicide layer
  • a method of fabricating a semiconductor structure comprising the steps of:
  • dummy gate stack includes at least a gate dielectric layer and a dummy gate
  • Another aspect of the invention also provides a semiconductor structure, the semiconductor structure comprising: a substrate;
  • a contact plug composed of a second conductive material penetrating the interlayer dielectric layer and the amorphous silicon layer and electrically connected to the source/drain regions, wherein:
  • a contact layer is present between the contact plug and the source/drain regions and the amorphous silicon layer.
  • the present invention forms a contact layer on the surface of the source/drain region and the amorphous silicon layer, and the metal silicide of the contact layer does not need to be subjected to high temperature treatment of the high-k gate dielectric layer, so that the thickness ratio can be controlled to withstand high temperature when generated.
  • the processing time is high, thereby reducing the contact resistance of the source/drain metal silicide layer; at the same time, the area covering the contact layer on the surface of the source/drain region can be increased, and the source/drain contact resistance can also be reduced.
  • the contact area of the source/drain region and the contact layer is increased, and the contact resistance can be further reduced.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2 through 13 are schematic cross-sectional views showing various stages of fabricating a semiconductor structure in accordance with the flow of FIG. 1 in accordance with a preferred embodiment of the present invention.
  • the same or similar reference numerals in the drawings represent the same or similar components. detailed description
  • step S101 a substrate 100 is provided.
  • the substrate 100 includes a silicon substrate (e.g., a silicon wafer).
  • the substrate 100 can include various doping configurations in accordance with design requirements well known in the art (e.g., a P-type substrate or an N-type substrate).
  • the substrate 100 in other embodiments may also include other basic semiconductors such as germanium.
  • the substrate 100 may comprise a compound semiconductor (e.g., a Group III-V material) such as silicon carbide, gallium arsenide, or indium arsenide.
  • substrate 100 can have, but is not limited to, a thickness of about a few hundred microns, such as can range from 400 um to 800 um.
  • isolation regions such as shallow trench isolation (STI) structures 120, may be formed in substrate 100 to electrically isolate adjacent field effect transistor devices.
  • STI shallow trench isolation
  • a dummy gate stack is formed on the substrate 100, side walls 240 are formed on the dummy gate stack sidewalls, and sources on both sides of the dummy gate stack are/ The drain region 110, wherein the dummy gate stack includes a first gate dielectric layer 210, a dummy gate 220, and a cap layer 230.
  • the first gate dielectric layer 210 is first formed on the substrate 100.
  • the material of the first gate dielectric layer 210 may be silicon oxide.
  • Formed by silicon nitride or a combination thereof, in other embodiments, may also be a high K medium, for example, Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , One or a combination of LaAlO may have a thickness of 2-10 nm.
  • a dummy gate 220 which may have a thickness of 10-80 nm.
  • a capping layer 230 is formed on the dummy gate 220, for example, by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof to protect the top region of the dummy gate 220, and to prevent the dummy gate 220.
  • the top region reacts with the deposited metal layer in a subsequent process of forming a contact layer.
  • the cover layer 230 may not be formed.
  • a dummy gate stack is formed.
  • the dummy gate stack may also be devoid of the first gate dielectric layer 210, but form a gate dielectric layer after removing the dummy gate stack in a subsequent replacement gate process.
  • sidewall spacers 240 are formed on sidewalls of the dummy gate stack for isolating the gates.
  • Sidewall 240 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side walls 240 may have a multi-layered structure, and the materials may be different for the adjacent two layers.
  • the spacer 240 may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • the source/drain regions 110 are located on both sides of the dummy gate stack and may be formed by implanting P-type or N-type dopants or impurities into the substrate 100.
  • the source/drain regions 110 may be P-doped SiGe;
  • source/drain regions 110 may be N-doped Si.
  • Source/drain regions 110 may be formed by methods including photolithography, ion implantation, diffusion, and/or other suitable processes that anneal the semiconductor structures using conventional semiconductor processing techniques and steps to activate source/drain regions 110.
  • the doping, annealing may be formed by other suitable methods including rapid annealing, spike annealing, and the like.
  • the source/drain regions 110 inside the substrate 100 may be elevated source and drain structures formed by selective epitaxial growth, the top of the epitaxial portion being higher than the bottom of the dummy gate stack (this specification
  • the bottom of the dummy gate stack referred to in the middle means the dummy gate stack and the substrate
  • an amorphous silicon layer 251 doped with the source/drain regions is formed on the surface of the source/drain region 110.
  • a layer of amorphous silicon 250 is first deposited to cover the surface of the substrate 100, and the dummy gate stack, sidewall spacers 240, and source/drain regions 110 are covered as shown.
  • the amorphous silicon layer 250 may be subjected to chemical vapor deposition (CVD), plasma enhanced CVD, high density plasma CVD, ALD (atomic layer deposition), plasma enhanced atomic layer deposition (PEALD), pulsed laser. Deposition (PLD) or other suitable method is formed.
  • the thickness of the amorphous silicon layer 250 may be several nanometers to several tens of nanometers.
  • the amorphous silicon layer 250 is then doped. If the source/drain regions are P-type doped, the amorphous silicon layer 250 is also P-doped. If the source/drain regions are N-type doped, then amorphous silicon Layer 250 is also N-doped to maintain the amorphous silicon layer 250 in conformity with the source/drain doping type. Finally, the amorphous silicon layer 250 is covered with a photoresist, and after lithographic patterning, the amorphous silicon layer 250 outside the source/drain regions 110 is etched away to obtain only the source/drain regions 110 as shown in FIG. The doped amorphous silicon layer 251.
  • the sidewall spacers 240 may be removed before the amorphous silicon layer 250 is covered.
  • the selectable range of the contact hole can be increased. The larger the contact hole, the larger the contact area of the source/drain region with the contact layer 111, and the contact resistance of the source/drain region with the contact layer 111 can be correspondingly reduced.
  • an interlayer dielectric layer 300 covering the doped amorphous silicon layer (251) and the dummy gate stack is formed.
  • the interlayer dielectric layer 300 may be formed by chemical vapor deposition (CVD), plasma enhanced CVD, high density plasma CVD, spin coating, and/or other suitable processes.
  • the material of the interlayer dielectric layer 300 may include silicon oxide (USG), doped silicon oxide (such as fluorosilicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass), low-k dielectric material (such as black diamond). , coral, etc., or a combination thereof.
  • the interlayer dielectric layer 300 may have a thickness ranging from 40 nm to 150 nm, such as 80 nm, 100 nm or 120 nm, and may have a multilayer structure (the materials may be different between adjacent layers). Referring to FIGS. 1 and 5, in step S105, a portion of the interlayer dielectric layer 300 is removed to expose the dummy gate stack.
  • a replacement gate process is performed.
  • the interlayer dielectric layer 300 and the dummy gate stack are planarized to expose the upper surface of the dummy gate 220.
  • the interlayer dielectric layer 300 may be removed by a chemical mechanical polishing (CMP) method, and the dummy gate 220 and the upper surface of the interlayer dielectric layer 300 may be flush (in this document, the term "flush" means both The height difference between them is within the range allowed by the process error).
  • CMP chemical mechanical polishing
  • step S106 the dummy gate stack is removed to form an opening 260, and the second gate dielectric layer and the first conductive material are filled in the opening 260, or A portion of the dummy gate stacked above the first gate dielectric layer is removed to form an opening, and the first conductive material is filled in the opening to form a gate stacked structure.
  • the dummy gate 220 and the first gate dielectric layer 210 are removed together, and the gate substrate 100 is exposed to form the opening 260, referring to FIG. 6(b).
  • the dummy gate 220 and the first gate dielectric layer 210 may be removed using wet etching and/or dry etching.
  • the wet etching process includes tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) or other suitable etching solution; the dry etching process includes sulfur hexafluoride (SF 6 ), hydrogen sulfide (HBr) Hydrides of hydrogen iodide (HI), chlorine, argon, helium, methane (and methyl chloride), acetylene, ethylene, and the like, and combinations thereof, and/or other suitable materials.
  • TMAH tetramethylammonium hydroxide
  • KOH potassium hydroxide
  • HBr hydrogen sulfide Hydrides of hydrogen iodide (HI), chlorine, argon, helium, methane (and methyl chloride), acetylene, ethylene, and the like, and combinations thereof, and/or other suitable materials.
  • a gate dielectric layer 270 is deposited covering the bottom of the opening 260 and the inner wall of the sidewall 240, with reference to FIG.
  • the material of the gate dielectric layer 270 may be a high-k dielectric, for example, one of Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, magic rO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO or In combination, the thickness may be from 2 nm to 10 nm, such as 5 nm or 8 nm.
  • the gate dielectric layer 270 may be formed by a CVD or atomic layer deposition (ALD) process.
  • the gate dielectric layer 270 may also have a multilayer structure including two or more layers having the above materials.
  • annealing is further performed to improve the performance of the semiconductor structure, and the annealing temperature ranges from 600 ° C to 800 ° C.
  • a metal gate 280 is formed on the gate dielectric layer 270 by depositing a first conductive material, with reference to FIG.
  • the first conductive material may be TaC, TiN, TaTbN, TaErN, One or a combination of TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x , for the PMOS, the first conductive material may be MoN x , TiSiN, TiCN, TaAlC, TiAlN : TaN, PtSi x , Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuO x ; may have a thickness of 10 nm to 80 nm, such as 30 nm or 50 nm.
  • the metal gate 280 may also have a multi-layered structure including two or more layers having the above materials.
  • the material of the first gate dielectric layer 210 is a high K dielectric, for example, Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3
  • Zr0 2 , LaAlO, or only the dummy gate 220 may be removed to form the opening 260, refer to FIG. 6( a ).
  • the first gate dielectric layer 210 is subjected to high temperature annealing to trim the structure formed before the first conductive material is formed, and then the metal gate 280 is formed, wherein the high temperature annealing and the process of forming the metal gate are as described above.
  • the processes performed after the formation of the gate dielectric layer 270 are the same and will not be described herein.
  • a CMP planarization process is performed to make the metal gate 280 flush with the upper surface of the interlayer dielectric layer 300 to form a gate stack structure, with reference to FIG.
  • a contact hole 310 is formed through the interlayer dielectric layer 300 and the amorphous silicon layer 251, and the contact hole 310 at least partially exposes the source/drain region 110.
  • the interlayer dielectric layer 300 is etched first, and then the doped amorphous silicon layer 251 is etched until the source/drain regions 110 are exposed to form the contact holes 310.
  • the interlayer dielectric layer 300 and the metal gate 280 are covered with a photoresist layer, and the photoresist layer is subjected to exposure patterning to form small holes corresponding to the positions where the contact holes 310 are to be formed.
  • the interlayer dielectric layer 300 and the doped amorphous silicon layer 251 are respectively etched by an etching method and stopped at the contact faces of the source/drain regions 110 and the doped amorphous silicon layer 251. To form the contact hole 310.
  • the interlayer dielectric layer 300 and the doped amorphous silicon layer 251 may be etched using different etching processes and/or different etchants.
  • the interlayer dielectric layer 300 may be dry-etched and the amorphous silicon layer 251 may be doped using wet etching.
  • the material of the photoresist layer may be an olefinic monomer material, a material containing an azide quinone compound or a polyethylene laurate material. Of course, a suitable material may be selected according to specific manufacturing needs.
  • the contact hole 310 formed after the etching may have a tapered structure which is large in size and small in size. [0040] In an embodiment of the invention, the depth of the etch can be controlled.
  • the etching time can be reduced or increased; the etching time is reduced such that the bottom of the contact hole 310 only reaches the inside of the amorphous silicon layer, and the etching time is increased to make the contact hole
  • the bottom of the 310 enters the inside of the source/drain regions, thereby further increasing the exposed area of the source/drain regions, so that subsequent operations can further reduce the contact resistance between the source/drain regions and the metal silicide layer.
  • a top layer 400 is deposited over the interlayer dielectric layer 300 and the metal gate 280 prior to forming the contact holes 310, with reference to FIG.
  • the material of the top layer 400 may be silicon nitride, oxide or a combination thereof, formed in the interlayer dielectric layer 300 and the metal gate by CVD, plasma enhanced CVD, high density plasma CVD, spin coating or other suitable methods. Above 280.
  • the top layer 400 can be used to protect the metal gate 280 from damage.
  • the top layer material and the interlayer dielectric layer material need to be different.
  • the top layer 400 can effectively prevent the metal gate 280 from being etched when the unreacted metal layer is removed by selective etching.
  • the etching to form the contact holes 310 needs to be adjusted accordingly, for example, the top layer 400 and the interlayer dielectric layer 310 are etched with different etching gases.
  • a contact layer 111 is formed on an exposed region of the source/drain region 110 and a sidewall of the contact hole 310 in the amorphous silicon layer 251.
  • a metal layer may be formed at the bottom of the contact hole 310 by metal sputtering or chemical vapor deposition.
  • the material of the metal layer may be Ni or NiPt, and the thickness is, for example, between 10 nm and 25 nm.
  • the metal silicide layer 111 formed by reacting with silicon after annealing is NiSi or Ni (Pt). Si 2 f In other embodiments, other feasible metals may be employed as the metal layer.
  • the semiconductor structure is annealed, and the annealing may be performed by other suitable methods including rapid annealing, spike annealing, etc., so that the exposed regions of the deposited metal layer and the source/drain regions 110 and the contact holes 310 are in the amorphous silicon layer 251.
  • the portion of the sidewall surface in contact contacts the silicon to form a metal silicide layer 111.
  • the exposed regions of the source/drain regions 110 and the contact holes 310 The metal silicide layer 111 is formed on the sidewall surface in the amorphous silicon layer 251. Different metal layer thicknesses and materials, the metal silicide layer 111 formed at different temperatures is completely different in the resistivity. By analyzing this relationship, the thickness of the metal layer and the thickness of the resulting metal silicide layer are determined. To ensure that the resistivity is at a relatively small level.
  • step S109 is performed to fill the contact hole 310 with a contact metal (also referred to as "second conductive material” herein) to form a contact plug 320.
  • the contact metal may be a metal or alloy such as W, TiAl, Al or the like.
  • a lining (not shown) may be deposited on the entire inner wall and bottom of the contact hole 310 by a deposition process such as ALD, CVD, PVD or the like before the contact hole 310 is filled with the contact metal.
  • the material of the layer may be Ti, TiN, Ta, TaN or a combination thereof, and the thickness thereof ranges from 5 nm to 20 nm, such as 10 nm or 15 nm.
  • the contact metal is subjected to CMP planarization treatment so that the upper surface of the contact metal is flush with the upper surface of the interlayer dielectric layer 300.
  • the formed metal silicide does not need to be subjected to high temperature treatment of the high-k gate dielectric layer, and the thickness thereof can be controlled during formation, and the source/drain regions and metal silicidation are reduced.
  • Contact resistance between the layers In addition to this, the area of the formed contact layer 111 is increased due to the presence of the amorphous silicon layer (not only on the exposed region of the source/drain region 110 but also in the contact hole 310 in the amorphous silicon layer 251).
  • the method of manufacturing the semiconductor structure provided by the present invention can effectively reduce the contact resistance between the source/drain regions and the contact plugs, and is advantageous for improving the performance of the semiconductor device.
  • FIG. 13 is a cross-sectional view of the semiconductor structure finally formed after the steps shown in FIG. 1 are completed.
  • the semiconductor structure includes: a substrate (100); a gate stack structure formed on the substrate (100); formed in the substrate (100), and located in the Source/drain regions (110) on both sides of the gate stack structure; an amorphous silicon layer (251) covering the source/drain regions (110); covering the amorphous silicon layer (251) and the gate stack structure Floor a dielectric layer (300); and a contact plug composed of a second conductive material that penetrates the interlayer dielectric layer (300) and the amorphous silicon layer (251) and is electrically connected to the source/drain region (110) (320). There is a contact layer (111) between the contact plug (320) and the source/drain region (110) and the amorphous silicon layer (251).
  • the contact layer 111 is composed of a metal silicide, including one of NiSi or Ni(Pt)Si 2-y , and may have a thickness ranging from 15 nm to 35 nm.
  • the bottom of the contact plug 320 extends into the source/drain regions to further increase the area of the metal silicide layer 111, reducing contact between the source/drain regions and the metal silicide layer. resistance.
  • the structural composition, the material, the forming method, and the like of the respective portions of the semiconductor structure may be the same as those described in the method embodiment for forming the semiconductor structure, and are not described herein.

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Abstract

本发明提供一种半导体结构的制造方法和相应的半导体器件。在替代栅工艺中通过在源漏区上方形成掺杂多晶硅层，形成贯穿层间介质层（300）和所述非晶硅层（251）的接触孔（310），所述接触孔（310）至少部分暴露所述源/漏区（110），并在所述源/漏区的暴露区域和接触孔在非晶硅层中的侧壁表面形成接触层，降低了所述源/漏区的接触电阻。由于接触层在对高K介质层进行退火后形成，所以避免了金属硅化物层在高温下被破坏。

Description

一种半导体结构及其制造方法
[0001】本申请要求了 2011年 11月 15日提交的、 申请号为 201110362350.9、 发明名称为"一种半导体结构及其制造方法"的中国专利申请的优先权， 其全 部内容通过引用结合在本申请中。 技术领域
[0002】本发明涉及半导体制造技术， 尤其涉及一种半导体结构及其制 造方法。 背景技术
[0003】金属氧化物半导体场效应晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET)是一种可以广泛应用在数字电路和 模拟电路中的晶体管。 当 MOSFET的栅介质层由高 K介质材料构成 时， 可以有效地减小栅极漏电流， 但是在最初形成高 K栅介质层时， 高 K栅介质层的分子结构可能会稍有缺陷。 为了修复该缺陷， 需要在 较高的温度 (600°C -800°C )下对其进行退火。 此外，对高 K栅介质层进 行退火还可以提高晶体管的可靠性。在替代栅工艺中， 沉积高 K栅介 质层通常在去除伪栅之后进行， 例如已经沉积了层间介质层之后。 如 果此时已经形成源漏区的金属硅化物，由于对高 K介质层进行退火需 要高温， 则金属硅化物层在高温下结构会发生变化， 从而导致金属硅 化物层电阻率的增加， 进而降低晶体管的性能。
[0004】在现有技术美国专利申请 US2007/0141798A1 中提出一种在替 代栅工艺中可以对高 K栅介质层进行退火但又不破坏金属硅化物层 的方法， 该方法步骤如下：
[0005】在衬底上形成具有牺牲栅极的晶体管； 在衬底上沉积第一层间 介质层； 移除所述牺牲栅极形成栅沟槽； 在所述栅沟槽中沉积形成高 K介电层；对所述高 K介电层进行退火；在所述栅沟槽中沉积金属层； 在所述第一层间介质层和所述晶体管上沉积第二层间介质层； 刻蚀所 述第一层间介质层和所述第二层间介质层至源极和漏极分别形成第 一接触沟槽和第二接触沟槽； 在所述第一接触沟槽和所述第二接触沟 槽中沉积第二金属层； 对所述第二金属层进行退火， 在所述源极和漏 极形成金属硅化物层； 以及沉积第三金属层填充所述第一接触沟槽和 所述第二接触沟槽。
[0006】由于在对高 K介质层进行退火后形成接触层 （如金属硅化物 层） ， 所以避免了金属硅化物层在高温下被破坏。
[0007】但是， 上述方法虽然能在对高 K栅介质层进行退火时不破坏金 属硅化物层，但是该方法的限制是只能在接触沟槽与源 /漏区之间形成 金属硅化物层，在源 /漏区表面覆盖金属硅化物的区域面积有限， 由此 不能充分地降低该晶体管的金属硅化物层的接触电阻。 因此， 如何降 低接触层 （如金属硅化物层） 的接触电阻， 就成了亟待解决的问题。 发明内容
[0008】本发明的目的之一是提供一种半导体结构及其制造方法， 利于 减小源 /漏区接触层 （如金属硅化物层） 的接触电阻。
[0009】根据本发明的一个方面， 提供一种半导体结构的制造方法， 该方 法包括以下步骤：
a)提供衬底；
b )在所述衬底上形成伪栅堆叠、 附着于所述伪栅堆叠侧壁的侧墙、 以 及位于所述伪栅堆叠两侧的源 /漏区，其中所述伪栅堆叠至少包括第一栅 极介质层和伪栅极；
c) 在所述源 /漏区表面形成与所述源 /漏区同型掺杂的非晶硅层；
d) 形成覆盖所述掺杂非晶硅层以及伪栅堆叠的层间介质层；
e )去除所述层间介质层的一部分以暴露所述伪栅堆叠；
f) 去除所述伪栅堆叠以形成开口， 在所述开口内填充第二栅介质层和所 述第一导电材料， 或者去除所述伪栅堆叠在第一栅极介质层以上的部分 以形成开口，在所述开口内填充所述第一导电材料， 以形成栅堆叠结构； g) 形成贯穿层间介质层和所述非晶硅层的接触孔，所述接触孔至少部分 暴露所述源 /漏区；
h) 在所述源 /漏区的暴露区域和接触孔在非晶硅层中的侧壁表面形成接 触层；
i)在所述接触孔中填充第二导电材料， 形成接触塞。
[0010]本发明另一方面还提出一种半导体结构， 该半导体结构包括： 衬底；
形成于所述衬底之上的栅堆叠结构；
形成于所述衬底之中， 且位于所述栅堆叠结构两侧的源 /漏区；
覆盖所述源 /漏区的非晶硅层；
覆盖所述非晶硅层和所述栅堆叠结构的层间介质层； 以及
贯穿层间介质层以及所述非晶硅层并与所述源 /漏区电连接的， 由第二导 电材料构成的接触塞， 其中：
[0011]在所述接触塞与所述源 /漏区以及所述非晶硅层之间存在接触层。
[0012]本发明在源 /漏区和非晶硅层表面形成接触层， 接触层的金属硅化 物不需要经受对高 K栅介质层的高温处理，所以生成时可以控制其厚度 比需要经受高温处理时的高， 从而降低了源 /漏区金属硅化物层的接触 电阻； 同时可增加在源 /漏区表面覆盖接触层的面积， 也利于减小源 / 漏区接触电阻。 同时由于非晶硅层的存在，使得源 /漏区与接触层的接 触面积增大， 可以进一步降低接触电阻。 与现有技术相比， 有明显的 进步和提高。 附图说明
[0013]通过阅读参照以下附图所作的对非限制性实施例所作的详细描 述， 本发明的其它特征、 目的和优点将会变得更明显：
[0014】图 1为根据本发明的半导体结构制造方法的流程图；
[0015】图 2至图 13为才艮据本发明的一个优选实施例按照图 1所示流程 制造半导体结构的各个阶段的剖面示意图。 [0016]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0017]下面详细描述本发明的实施例， 所述实施例的示例在附图中示 出。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明， 而不能解释为对本发明的限制。
[ 0018] 下文的公开提供了许多不同的实施例或例子用来实现本发 明的不同结构。 为了简化本发明的公开， 下文中对特定例子的部件和 设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种重复 是为了简化和清楚的目的， 其本身不指示所讨论各种实施例和 /或设 置之间的关系。 此外， 本发明提供了各种特定的工艺和材料的例子， 但是本领域技术人员可以意识到其他工艺的可应用性和 /或其他材料 的使用。 应当注意， 在附图中所图示的部件不一定按比例绘制。 本发 明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制 本发明。
[0019】下面，将结合图 2至图 13对图 1中形成半导体结构的方法进行 具体地描述。
[0020】参考图 1和图 2， 在步骤 S101中， 提供衬底 100。
[0021】在本实施例中， 衬底 100 包括硅衬底 (例如硅晶片）。 根据现有 技术公知的设计要求 (例如 P型衬底或者 N型衬底）， 衬底 100可以包 括各种掺杂配置。其他实施例中衬底 100还可以包括其他基本半导体， 例如锗。 或者， 衬底 100可以包括化合物半导体 （如 III- V族材料）， 例如碳化硅、 砷化镓、 砷化铟。 典型地， 衬底 100可以具有但不限于 约几百微米的厚度， 例如可以在 400um-800um的厚度范围内。
[0022】特别地， 可以在衬底 100中形成隔离区， 例如浅沟槽隔离（STI) 结构 120， 以便电隔离相邻的场效应晶体管器件。
[0023】参考图 1和图 2，在步骤 S102中，在衬底 100上形成伪栅堆叠、 在所述伪栅堆叠侧壁形成侧墙 240、 以及位于所述伪栅堆叠两侧的源 / 漏区 110， 其中所述伪栅堆叠包括第一栅介质层 210、 伪栅极 220和 覆盖层 230。
[0024】在本实施例中， 在形成伪栅堆叠时， 首先在衬底 100上形成第 一栅介质层 210， 在本实施例中， 所述第一栅介质层 210的材料可以 是氧化硅、 氮化硅或其组合形成， 在其他实施例中， 也可以是高 K介 质， 例如， Hf02、 HfSiO、 HfSiON、 HfTaO, HfTiO, HfZrO、 A1203、 La203、 Zr02、 LaAlO中的一种或其组合， 其厚度可以为 2-10nm。 而 后， 在所述第一栅介质层 210上通过沉积例如 Poly-Si、 Poly-SiGe, 非晶硅，和 /或，掺杂或未掺杂的氧化硅及氮化硅、氮氧化硅、碳化硅， 甚至金属形成伪栅极 220， 其厚度可以为 10-80nm。 最后， 在伪栅极 220上形成覆盖层 230， 例如通过沉积氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合形成， 用以保护伪栅极 220的顶部区域， 防止伪栅极 220 的顶部区域在后续形成接触层的工艺中与沉积的金属层发生反 应。 在其他实施例中， 也可以不形成覆盖层 230。 通过光刻工艺构图， 并利用刻蚀工艺刻蚀上述沉积的多层结构后， 形成伪栅堆叠。 在另一 个实施例中， 伪栅堆叠也可以没有第一栅介质层 210， 而是在后续的 替代栅工艺中除去伪栅堆叠后形成栅介质层。
[0025】形成所述伪栅堆叠后， 在所述伪栅堆叠的侧壁上形成侧墙 240， 用于将栅极隔离。 侧墙 240可以由氮化硅、 氧化硅、 氮氧化硅、 碳化 硅及其组合，和 /或其他合适的材料形成。侧墙 240可以具有多层结构， 且对于相邻的两层， 其材料可以不同。 侧墙 240可以通过包括沉积刻 蚀工艺形成，其厚度范围可以是 10nm-l 00nm，如 30nm、 50nm或 80nm。
[0026】源 /漏区 110位于伪栅堆叠两侧， 可以通过向衬底 100中注入 P 型或 N型掺杂物或杂质而形成， 例如， 对于 PMOS来说， 源 /漏区 110 可以是 P型掺杂的 SiGe; 对于 NMOS来说， 源 /漏区 110可以是 N型 掺杂的 Si。 源 /漏区 110可以由包括光刻、 离子注入、 扩散和 /或其他 合适工艺的方法形成， 利用通常的半导体加工工艺和步骤， 对所述半 导体结构进行退火， 以激活源 /漏区 110中的掺杂， 退火可以采用包括 快速退火、 尖峰退火等其他合适的方法形成。 在本实施例中， 源 /漏区 110在衬底 100内部， 在其他一些实施例中， 源 /漏区 110可以是通过 选择性外延生长所形成的提升的源漏极结构， 其外延部分的顶部高于 伪栅堆叠底部（本说明书中所指的伪栅堆叠底部意指伪栅堆叠与衬底
100的交界面）。
[0027】参考图 1、 图 3和图 4， 在步骤 S103中， 在所述源 /漏区 110表 面形成与所述源 /漏区同型掺杂的非晶硅层 251。具体地，如图 3所示， 首先沉积一层非晶硅层 250均勾覆盖所述衬底 100表面， 如图所示覆 盖了伪栅堆叠、 侧墙 240以及源 /漏区 110。 非晶硅层 250可以通过化 学气相沉积（Chemical vapor deposition, CVD )、 等离子体增强 CVD、 高密度等离子体 CVD、 ALD (原子层淀积）、 等离子体增强原子层淀 积 （PEALD )、 脉冲激光沉积 （PLD ) 或其他合适的方法形成。 非晶 硅层 250的厚度可以是几纳米到几十纳米。之后对非晶硅层 250进行 掺杂， 如果源 /漏区是 P型掺杂， 那么非晶硅层 250也进行 P型掺杂， 如果源 /漏区是 N型掺杂， 那么非晶硅层 250也进行 N型掺杂， 保持 非晶硅层 250与源 /漏区掺杂类型的一致。最后在非晶硅层 250上覆盖 光刻胶， 光刻构图后刻蚀去除源 /漏区 110上方以外的非晶硅层 250， 得到如图 4所示的仅存在于源 /漏区 110上方的掺杂非晶硅层 251。
[0028】需强调的是， 此时， 在覆盖非晶硅层 250之前， 还可以去除至少 部分所述侧墙 240。 如图 13所示， 在后续步骤中制作接触塞时， 可以增 大接触孔的可选择范围。 接触孔越大， 源 /漏区与接触层 111的接触面积 就越大， 相应可以减小源 /漏区与接触层 111的接触电阻。
[0029】参考图 1和图 4， 在步骤 S104中， 形成覆盖所述掺杂非晶硅层 (251)以及伪栅堆叠的层间介质层 300。 所述层间介质层 300可以通过 化学气相沉淀 (CVD)、 等离子体增强 CVD、 高密度等离子体 CVD、 旋涂和 /或其他合适的工艺等方法形成。所述层间介质层 300的材料可 以包括氧化硅 (USG)、 掺杂的氧化硅 (如氟硅玻璃、 硼硅玻璃、 磷硅玻 璃、硼磷硅玻璃）、低 k电介质材料 (如黑钻石、 coral等）中的一种或其 组合。所述层间介质层 300的厚度范围可以是 40nm-150nm,如 80nm、 lOOnm或 120nm，且可以具有多层结构（相邻两层间，材料可以不同）。 [0030】参考图 1和图 5， 在步骤 S105中， 去除所述层间介质层 300的 一部分以暴露所述伪栅堆叠。
[0031】在本实施例中， 执行替代栅工艺。 参考图 5， 对层间介质层 300 和伪栅堆叠进行平坦化处理以暴露伪栅极 220的上表面。 例如， 可以 通过化学机械抛光 (CMP)的方法去除层间介质层 300，并使伪栅极 220 和层间介质层 300 的上表面齐平 (本文件内， 术语 "齐平" 意指两者 之间的高度差在工艺误差允许的范围内）。
[0032】参考图 1， 图 6至图 9， 在步骤 S106中， 去除所述伪栅堆叠以 形成开口 260， 在所述开口 260内填充第二栅介质层和所述第一导电 材料， 或者去除所述伪栅堆叠在第一栅极介质层以上的部分以形成开 口， 在所述开口内填充所述第一导电材料， 以形成栅堆叠结构。
[0033】在本实施例中， 一并去除伪栅极 220和第一栅介质层 210， 暴 露栅衬底 100 以形成开口 260， 参考图 6(b)。 可以使用湿法刻蚀和 / 或干法刻蚀的方式去除伪栅极 220和第一栅介质层 210。 湿法刻蚀工 艺包括四甲基氢氧化铵 (TMAH)、 氢氧化钾 (KOH)或者其他合适刻蚀 的溶液；干法刻蚀工艺包括六氟化硫 (SF6)、淡化氢 (HBr)、碘化氢 (HI)、 氯、 氩、 氦、 甲烷 （及氯代甲烷）、 乙炔、 乙烯等碳的氢化物及其组 合， 和 /或其他合适的材料。
[0034】沉积栅介质层 270， 覆盖开口 260的底部以及侧墙 240的内壁， 参考图 7。 所述栅介质层 270的材料可以是高 K介质， 例如， Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 魔 rO、 A1203、 La203、 Zr02、 LaAlO 中的一种或其組合， 其厚度可以为 2nm-10nm， 如 5nm或 8nm。 所述 栅介质层 270可以通过 CVD或者原子层沉积 (ALD)的工艺来形成。 所述栅介质层 270还可以具有多层结构， 包括具有上述材料的两个以 上的层。
[0035】形成所述栅介质层 270后， 进一步进行退火， 以提高半导体结 构的性能， 退火的温度范围为 600°C至 800°C。 退火后， 在所述栅介 质层 270上通过沉积第一导电材料的方式形成金属栅极 280， 参考图 8。 对于 NMOS， 所述第一导电材料可以是 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax中的一种或其组合， 对 于 PM0S，所述第一导电材料可以是 MoNx, TiSiN, TiCN, TaAlC, TiAlN: TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuOx ; 其厚度可以为 10nm-80nm, 如 30nm或 50nm。 其中， 金属栅极 280也可以具有多层 结构， 包括具有上述材料的两个以上的层。
[0036】在其他实施例中， 当所述第一栅介质层 210的材料为高 K介质 时， 例如， Hf02、 HfSiO、 HfSiON、 HfTaO, HfTiO, HfZrO、 A1203、 La203、 Zr02、 LaAlO 中的一种或其组合， 也可以只去除所述伪栅极 220 以形成开口 260， 参考图 6(a)。 接着， 对所述第一栅介质层 210 进行高温退火， 以修整在形成第一导电材料之前已形成的结构， 然后再 形成金属栅极 280， 其中， 高温退火与形成金属栅极的工艺与上述形 成所述栅介质层 270后所执行的工艺相同， 在此不再赘述。
[0037】最后，执行 CMP平坦化处理，使所述金属栅极 280与层间介质 层 300的上表面齐平， 形成栅堆叠结构， 参考图 9。
[0038】参考图 1和图 11， 在步骤 S107中， 形成贯穿层间介质层 300 和所述非晶硅层 251的接触孔 310， 所述接触孔 310至少部分暴露所 述源 /漏区 110; 在本实施例中， 先刻蚀层间介质层 300， 再蚀刻掺杂 非晶硅层 251， 直至暴露源 /漏区 110， 形成接触孔 310。
[0039】刻蚀之前先在层间介质层 300和金属栅极 280上覆盖一层光刻 胶层， 对所述光刻胶层进行曝光构图， 形成小孔， 对应要形成接触孔 310的位置。 在本实施例中， 使用刻蚀的方法对层间介质层 300和掺 杂非晶硅层 251 分别进行刻蚀并停止于源 /漏区 110与掺杂非晶硅层 251 的接触面上， 以形成接触孔 310。 其中可以使用不同的刻蚀工艺 和 /或不同的刻蚀剂来刻蚀层间介质层 300和掺杂非晶硅层 251。例如， 在非晶硅层较薄的情况下， 可以使用干法刻蚀层间介质层 300并使用 湿法刻蚀掺杂非晶硅层 251。 光刻胶层的材料可以是烯类单体材料、 含有叠氮醌类化合物的材料或聚乙烯月桂酸酯材料， 当然也可以根据具 体的制造需要选择合适的材料。 刻蚀后形成的接触孔 310可以具有上 大下小的锥形结构。 [0040】在本发明的实施例中， 可以对刻蚀的深度进行控制。 具体地， 在刻蚀掺杂非晶硅层 251时， 可以减少或者加大刻蚀时间； 减少刻蚀 时间使得接触孔 310的底部仅仅到达非晶硅层内部， 加大刻蚀时间使 得接触孔 310的底部进入所述源 /漏区的内部， 从而进一步增大了源 / 漏区的暴露面积，使得后续操作能够进一步减小源 /漏区与金属硅化物 层之间的接触电阻。
[0041】可选地， 在形成接触孔 310之前， 在层间介质层 300和金属栅极 280上沉积顶层 400， 参考图 10。 所述顶层 400的材料可以是氮化硅、 氧化物或其组合，通过 CVD、等离子体增强 CVD、高密度等离子体 CVD、 旋涂或其他合适的方法形成在层间介质层 300和金属栅极 280之上。 在 该半导体结构形成的后续过程中， 顶层 400可以用来保护金属栅极 280 不受到破坏。此时， 所述顶层材料与所述层间介质层材料需不同。例如， 在后续工序中， 向接触孔 310内沉积金属层形成金属硅化物层后， 通 过选择性刻蚀去除未反应的金属层时， 顶层 400可以有效地防止金属 栅极 280被刻蚀。
[0042】在本发明的实施例中， 如果沉积了顶层 400， 则形成接触孔 310 的刻蚀需要进行相应调整， 例如， 用不同的刻蚀气体刻蚀顶层 400和 层间介质层 310。
[0043】参考图 1和图 12， 在步骤 S108中， 在所述源 /漏区 110的暴露 区域和接触孔 310在非晶硅层 251中的侧壁表面形成接触层 111。 可 以通过金属溅镀方式或化学气相沉积法， 在接触孔 310的底部形成金 属层。 在本实施例中， 所述金属层的材料可以是 Ni或者 NiPt， 厚度 例如在 10nm至 25nm之间， 经过退火与硅发生反应后所形成的所述 金属硅化物层 111为 NiSi或者 Ni(Pt)Si2f 在其他实施例中， 可以采 用其他可行的金属作为金属层。 然后， 对该半导体结构进行退火， 退 火可以采用包括快速退火、 尖峰退火等其他合适的方法实施， 使沉积 的金属层的与源 /漏区 110 的暴露区域和接触孔 310在非晶硅层 251 中的侧壁表面相接触的部分与硅反应形成金属硅化物层 111。
[0044】如图 12所示， 在所述源 /漏区 110的暴露区域以及接触孔 310 在非晶硅层 251 中的侧壁表面形成了所述金属硅化物层 111。 不同的 金属层厚度和材料， 在不同温度下形成的金属硅化物层 111在电阻率 的表现上截然不同， 通过分析这种关系， 确定出金属层的厚度以及生 成的金属硅化物层的厚度， 以保证电阻率处于相对较小的水平上。
[0045】参考图 1 和图 13， 最后， 执行步骤 S109， 在所述接触孔 310 中填充接触金属 （文中也称为 "第二导电材料"）， 形成接触塞 320。 所述接触金属可以是 W、 TiAl、 A1等金属或合金。 可选地， 在向所述 接触孔 310中填充接触金属之前， 可以通过 ALD、 CVD、 PVD等沉 积工艺先在接触孔 310整个内壁和底部沉积一层衬层 (未示出）， 所述 衬层的材料可以是 Ti、 TiN、 Ta、 TaN 或其组合， 其厚度的范围是 5nm-20nm, 如 10nm或 15nm。 填充接触金属后， 对所述接触金属进 行 CMP平坦化处理， 使接触金属的上表面与层间介质层 300的上表 面齐平。
[0046】随后按照常规半导体制造工艺的步骤完成该半导体器件的制 造。
[0047】在上述步骤完成后， 在所述半导体结构中， 形成的金属硅化物 不需要经受对高 K栅介质层的高温处理， 生成时可以控制其厚度， 降 低了源 /漏区与金属硅化物层之间的接触电阻。 除此之外， 由于非晶硅 层的存在，使得所形成的接触层 111的面积增大（不仅存在于源 /漏区 110的暴露区域上， 而且存在于接触孔 310在非晶硅层 251中的侧壁 表面上）， 所以本发明提供的半导体结构的制造方法， 可以有效地减 小源 /漏区与接触塞之间的接触电阻， 利于提高半导体器件的性能。
[0048】为了更清楚地理解根据上述半导体结构的制造方法所形成的半 导体结构， 下面根据图 13对所述半导体结构进行说明。
[0049】参考图 13， 图 13为完成图 1 中所示的步骤后最终形成的半导体 结构的剖面图。 在本实施例中， 所述半导体结构包括： 衬底（100 ) ； 形成于所述衬底 ( 100 )之上的栅堆叠结构； 形成于所述衬底（ 100 )之 中，且位于所述栅堆叠结构两侧的源 /漏区（ 110 );覆盖所述源 /漏区（ 110 ) 的非晶硅层 ( 251 ) ； 覆盖所述非晶硅层（251 )和所述栅堆叠结构的层 间介质层（ 300 )； 以及贯穿层间介质层（ 300 )以及所述非晶硅层 ( 251 ) 并与所述源 /漏区（ 110 )电连接的，由第二导电材料构成的接触塞（ 320 )。 其中在所述接触塞（ 320 )与所述源 /漏区（ 110 )以及所述非晶硅层（ 251 ) 之间存在接触层（111 ) 。
[0050]所述接触层 111由金属硅化物组成， 包括 NiSi或者 Ni(Pt)Si2-y中 的一种， 其厚度的范围可以在 15nm-35nm之间。
[0051】在又一个实施例中， 接触塞 320的底部延伸至源 /漏区内， 从而进 一步增大金属硅化物层 111的面积，减小源 /漏区与金属硅化物层之间的 接触电阻。
[0052】其中， 对半导体结构各实施例中各部分的结构组成、 材料及形 成方法等均可与前述半导体结构形成的方法实施例中描述的相同， 不 在赘述。
[0053】虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱 离本发明的精神和所附权利要求限定的保护范围的情况下， 可以对这 些实施例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通 技术人员应当容易理解在保持本发明保护范围内的同时， 工艺步骤的 次序可以变化。
[0054】此外， 本发明的应用范围不局限于说明书中描述的特定实施例 的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公 开内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在 或者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或 步骤， 其中它们执行与本发明描述的对应实施例大体相同的功能或者 获得大体相同的结果， 依照本发明可以对它们进行应用。 因此， 本发 明所附权利要求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方 法或步骤包含在其保护范围内。

Claims

权 利 要 求
1. 一种半导体结构的制造方法， 该方法包括以下步骤：
a)提供衬底（ 100 ) ；
b)在所述衬底 (100)上形成伪栅堆叠、 附着于所述伪栅堆叠侧壁 的侧墙（240) 、 以及位于所述伪栅堆叠两侧的源 /漏区 （110) ， 其中所 述伪栅堆叠至少包括第一栅极介质层和伪栅极 (220) ； 层（251) ；
d) 形成覆盖所述掺杂非晶硅层（251) 以及伪栅堆叠的层间介质层 (300) ；
e)去除所述层间介质层（300) 的一部分以暴露所述伪栅堆叠； f) 去除所述伪栅堆叠以形成开口， 在所述开口 （260) 内填充第二 栅介质层和所述第一导电材料（280) ， 以形成栅堆叠结构， 或者去除 所述伪栅堆叠在第一栅极介质层以上的部分以形成开口， 在所述开口
(260) 内填充所述第一导电材料（280) ， 以形成栅堆叠结构；
g) 形成贯穿层间介质层 （ 300)和所述非晶硅层 （251 ) 的接触孔 (310) ， 所述接触孔（310)至少部分暴露所述源 /漏区 （110) ；
h) 在所述源 /漏区 （110) 的暴露区域和接触孔（310)在非晶硅层 (251) 中的侧壁表面形成接触层（111) ；
i)在所述接触孔中填充第二导电材料， 形成接触塞（320) 。
2.根据权利要求 1所述的方法， 其中：
在所述步骤 c) 中， 形成所述掺杂非晶硅层 (251)的步骤包括， 形成非晶硅层 (250)， 覆盖伪栅堆叠、 附着于所述伪栅堆叠侧壁的侧 墙 (240)、 以及位于所述伪栅堆叠两侧的源 /漏区（110);
对所述非晶硅层 (250)进行掺杂， 其掺杂类型与源 /漏区的相同； 对所述非晶硅层 (250)进行构图，保留源 /漏区上方的非晶硅层，去除 其余部分的非晶硅层， 形成所述掺杂非晶硅层 (251)。 3.根据权利要求 1所述的方法， 其中， 在所述步骤 f)和所述步骤 g) 之间还执行：
j) 形成覆盖所述栅堆叠结构和所述层间介质层 (301)的顶层 (400)，所
4.根据权利要求 1 所述的方法， 其中， 所述接触层 (111)包括 NiSi 或者 Ni(Pt)Si2 中的一种。
5.根据权利要求 1所述的方法， 其中， 所述步骤 h)包括：
形成覆盖所述源 /漏区（110 )的暴露区域和接触孔（310 )的侧壁的 金属层；
执行第一退火操作， 使所述金属层与所述源 /漏区 （110 ) 的暴露区 域和接触孔（310 )在非晶硅层 ( 251 ) 中的侧壁表面反应， 形成接触层 ( 111 ) ；
去除未反应的所述金属层。
6.根据权利要求 5所述的方法， 其中：
所述金属层的材料包括 Ni或者 NiPt中的一种。
7根据权利要求 5所述的方法， 其中：
如果所述金属层的材料为 NiPt， 则 NiPt中 Pt的含量小于 5%。
8.根据权利要求 5或 6所述的方法， 其中：
所述金属层的厚度在 10nm至 25nm的范围内。
9.根据权利要求 5或 6所述的方法， 其中：
所述退火温度在 500°C〜600°C之间。
10. 根据权利要求 5 所述的方法， 其中所述接触层 (111)的厚度在 15nm至 35nm的范围内。
11. 根据权利要求 1所述的方法， 其中， 在所述步骤 f)中， 在填充 所述第一导电材料（280 )之前还包括：
进行第二退火操作， 以修整在填充第一导电材料之前已形成的结 构。
12. 一种半导体结构， 该半导体结构包括：
衬底（ 100 ) ； 形成于所述衬底 ( 100)之上的栅堆叠结构；
形成于所述衬底（100)之中， 且位于所述栅堆叠结构两侧的源 /漏 区 （ 110) ；
覆盖所述源 /漏区 （110) 的掺杂非晶硅层（251) ；
覆盖所述掺杂非晶硅层 （251 ) 和所述栅堆叠结构的层间介质层 (300) ； 以及
贯穿层间介质层（300)以及所述非晶硅层（251)并与所述源 /漏区 (110) 电连接的， 由第二导电材料构成的接触塞（320) ， 其中：
在所述接触塞（ 320 )与所述源 /漏区（ 110 )以及所述非晶硅层 (251) 之间存在接触层（111) 。
13.根据权利要求 12所述的半导体结构， 其中：
所述接触层 (111)包括 NiSi或者 Ni(Pt)Si2-y中的一种。
14.根据权利要求 12所述的半导体结构， 其中：
所述接触层 (111)的厚度在 15nm至 35nm的范围内。
15.根据权利要求 12所述的半导体结构， 其中：
所述接触塞 (320)延伸至所述源 /漏区（110)内部。
PCT/CN2011/083331 2011-11-15 2011-12-02 一种半导体结构及其制造方法 WO2013071656A1 (zh)

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Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137488B (zh) * 2011-12-01 2015-09-30 中国科学院微电子研究所 半导体器件及其制造方法
US9034701B2 (en) 2012-01-20 2015-05-19 International Business Machines Corporation Semiconductor device with a low-k spacer and method of forming the same
US9601630B2 (en) * 2012-09-25 2017-03-21 Stmicroelectronics, Inc. Transistors incorporating metal quantum dots into doped source and drain regions
US9748356B2 (en) 2012-09-25 2017-08-29 Stmicroelectronics, Inc. Threshold adjustment for quantum dot array devices with metal source and drain
CN104217935B (zh) * 2013-06-05 2017-06-13 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN104253047B (zh) * 2013-06-26 2017-08-25 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN104347418B (zh) * 2013-08-05 2019-11-01 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
US10002938B2 (en) 2013-08-20 2018-06-19 Stmicroelectronics, Inc. Atomic layer deposition of selected molecular clusters
CN104681428A (zh) * 2013-11-26 2015-06-03 中芯国际集成电路制造(上海)有限公司 晶体管结构及其形成方法
US9449827B2 (en) * 2014-02-04 2016-09-20 International Business Machines Corporation Metal semiconductor alloy contact resistance improvement
US10032876B2 (en) 2014-03-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide having a non-angular profile
US9190489B1 (en) * 2014-09-08 2015-11-17 Lam Research Corporation Sacrificial pre-metal dielectric for self-aligned contact scheme
TWI578538B (zh) * 2014-11-28 2017-04-11 美光科技公司 半導體結構
US9685434B2 (en) * 2014-12-10 2017-06-20 International Business Machines Corporation Inter-level dielectric layer in replacement metal gates and resistor fabrication
KR102224386B1 (ko) 2014-12-18 2021-03-08 삼성전자주식회사 집적 회로 장치의 제조 방법
CN105789112B (zh) * 2014-12-26 2019-12-27 中芯国际集成电路制造(上海)有限公司 半导体器件及其制备方法
US9570578B2 (en) * 2015-02-11 2017-02-14 United Microelectronics Corp. Gate and gate forming process
US9484431B1 (en) * 2015-07-29 2016-11-01 International Business Machines Corporation Pure boron for silicide contact
US9496283B1 (en) 2015-08-10 2016-11-15 Stmicroelectronics, Inc. Transistor with self-aligned source and drain contacts and method of making same
US9793204B2 (en) 2015-11-17 2017-10-17 Taiwan Semiconductor Manufacturing Company Limited Method of manufacturing semiconductor structure comprising plurality of through holes using metal hard mask
CN106935646B (zh) * 2015-12-30 2020-10-30 中芯国际集成电路制造(北京)有限公司 埋藏沟道晶体管及其形成方法
CN108074813A (zh) * 2016-11-10 2018-05-25 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US20190273133A1 (en) * 2016-12-14 2019-09-05 Intel Corporation Transistor source/drain amorphous interlayer arrangements
CN108573862B (zh) * 2017-03-07 2020-09-08 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10665450B2 (en) * 2017-08-18 2020-05-26 Applied Materials, Inc. Methods and apparatus for doping engineering and threshold voltage tuning by integrated deposition of titanium nitride and aluminum films
CN109427653B (zh) 2017-08-31 2020-10-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN110571188B (zh) * 2018-06-05 2021-10-01 中芯国际集成电路制造(上海)有限公司 接触插塞、半导体器件及其制造方法
US10438850B1 (en) 2018-07-23 2019-10-08 International Business Machines Corporation Semiconductor device with local connection
US10431495B1 (en) * 2018-07-23 2019-10-01 International Business Machines Corporation Semiconductor device with local connection
CN109950317A (zh) * 2019-03-27 2019-06-28 厦门市三安集成电路有限公司 半导体器件及制作方法
CN112397531A (zh) * 2019-08-13 2021-02-23 联华电子股份有限公司 半导体元件及其制造方法
US11393718B2 (en) * 2020-01-30 2022-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for forming the same
CN111627927A (zh) * 2020-05-19 2020-09-04 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制作方法
CN114639732A (zh) 2020-12-15 2022-06-17 联华电子股份有限公司 半导体元件及其制作方法
CN112786439A (zh) * 2021-01-19 2021-05-11 长鑫存储技术有限公司 半导体结构的制造方法、半导体结构、晶体管及存储器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355002A (en) * 1993-01-19 1994-10-11 Industrial Technology Research Institute Structure of high yield thin film transistors
US6033963A (en) * 1999-08-30 2000-03-07 Taiwan Semiconductor Manufacturing Company Method of forming a metal gate for CMOS devices using a replacement gate process
CN102024744A (zh) * 2009-09-16 2011-04-20 中国科学院微电子研究所 半导体器件及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020192914A1 (en) * 2001-06-15 2002-12-19 Kizilyalli Isik C. CMOS device fabrication utilizing selective laser anneal to form raised source/drain areas
US7105889B2 (en) * 2004-06-04 2006-09-12 International Business Machines Corporation Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics
US20070141798A1 (en) * 2005-12-20 2007-06-21 Intel Corporation Silicide layers in contacts for high-k/metal gate transistors
US20090315120A1 (en) * 2008-06-24 2009-12-24 Lucian Shifren Raised facet- and non-facet 3d source/drain contacts in mosfets
US8456011B2 (en) * 2011-01-14 2013-06-04 International Business Machines Corporation Method to control metal semiconductor micro-structure
US8466493B2 (en) * 2011-03-29 2013-06-18 International Business Machines Corporation Self-aligned III-V field effect transistor (FET), integrated circuit (IC) chip with self-aligned III-V FETS and method of manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355002A (en) * 1993-01-19 1994-10-11 Industrial Technology Research Institute Structure of high yield thin film transistors
US6033963A (en) * 1999-08-30 2000-03-07 Taiwan Semiconductor Manufacturing Company Method of forming a metal gate for CMOS devices using a replacement gate process
CN102024744A (zh) * 2009-09-16 2011-04-20 中国科学院微电子研究所 半导体器件及其制造方法

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