WO2012071843A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2012071843A1
WO2012071843A1 PCT/CN2011/072917 CN2011072917W WO2012071843A1 WO 2012071843 A1 WO2012071843 A1 WO 2012071843A1 CN 2011072917 W CN2011072917 W CN 2011072917W WO 2012071843 A1 WO2012071843 A1 WO 2012071843A1
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Prior art keywords
source
drain
thickness
layer
drain extension
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PCT/CN2011/072917
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English (en)
French (fr)
Inventor
尹海洲
罗军
骆志炯
朱慧珑
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中国科学院微电子研究所
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Priority to US13/380,612 priority Critical patent/US8822334B2/en
Priority to CN201190000068.XU priority patent/CN202487541U/zh
Publication of WO2012071843A1 publication Critical patent/WO2012071843A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the present invention relates to semiconductor fabrication techniques, and more particularly to a semiconductor structure and method of fabricating the same. Background technique
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the MOSFET includes: a substrate 100, source/drain regions 110, source/drain extensions 111, dummy gate stacks, and Side wall 240.
  • the dummy gate stack is formed on the substrate 100, and includes a gate dielectric layer 210, a dummy gate 220, and a cap layer 230.
  • the source/drain regions 110 are formed in the substrate 100,
  • the source/drain extension region 111 extends from the source/drain region 110 to below the dummy gate stack, and has a thickness smaller than the source/drain region 110; the sidewall spacer 240 is located
  • the source/drain extension region 111 is covered on the sidewall of the dummy gate stack; the contact layer 112 is present on the source/drain region 110 (to reduce the contact resistance), and is formed for the silicon-containing substrate Metal silicide layer.
  • a silicon-containing substrate will be described as an example, and the contact layer will be referred to as a metal silicide layer.
  • the method can reduce the contact resistance between the source/drain regions and the metal silicide layer, the method is limited to forming a metal silicide layer on the source/drain regions without being located under the sidewall spacers.
  • a metal silicide layer is formed on the source/drain extension region, and the contact resistance between the source/drain extension region and the metal silicide layer cannot be further reduced, thereby improving the performance of the MOSFET;
  • the gate process it is necessary to remove the dummy gate stack after forming the metal silicide layer 112 and the interlayer dielectric layer covering the source/drain regions 110, and then forming a gate dielectric layer of a MOSFET composed of a high-k dielectric material, thereby effectively reducing Gate leakage current.
  • the molecular structure of the high-k gate dielectric layer may be slightly defective. In order to repair this defect, it needs to be annealed at a higher temperature (600 ° C - 800 ° C).
  • the metal or alloy used in the metal silicide layer in the MOSFET cannot withstand the high temperatures required to anneal the high-k dielectric layer, and its structure changes at high temperatures, resulting in an increase in the resistivity of the metal silicide, which in turn reduces the transistor. Performance.
  • An object of the present invention is to provide a semiconductor structure and a method of fabricating the same that can reduce contact resistance and maintain the performance of a semiconductor structure in a high temperature process.
  • a method of fabricating a semiconductor structure comprising the steps of:
  • the contact layer Forming a contact layer on the source/drain region and the exposed source/drain extension region, the contact layer being one or a combination of CoSi 2 , NiSi or Ni(Pt)Si 2 _y and The thickness of the contact layer is less than
  • Another aspect of the invention also provides a semiconductor structure including a substrate, a source/drain region, a source/drain extension region, and a gate, wherein:
  • the source/drain regions and the source/drain extension regions are formed in the substrate, and a thickness of the source/drain extension regions is smaller than a thickness of the source/drain regions;
  • a contact layer is present on the source/drain regions and at least a portion of the upper surface of the source/drain extension regions, and the contact layer (112) is in CoSi 2 , NiSi or Ni(Pt)Si ⁇ y One or a combination thereof
  • the thickness of the contact layer (112) is less than 10 nm.
  • the present invention has the following advantages:
  • a contact layer is formed on the source/drain regions, but also a contact layer is formed on some or even all of the source/drain extension regions, and the contact layer is made of CoSi 2 , NiSi or One or a combination of Ni(Pt)Si 2 —y and the thickness of the contact layer being less than 10 nm may cause an annealing temperature of the contact layer when subsequently removing the dummy gate stack and forming a gate stack (eg, 700° C. It is still thermally stable at 800 ° C) and can maintain low resistance up to 850 ° C, which reduces contact resistance and reduces the degradation of semiconductor structure performance.
  • the thickness of the contact layer formed thereon is very thin, and when a part of the sidewall spacer is removed, a PN junction between the contact layer and the source/drain extension region and the substrate may also have a certain distance, which is not easy Aggravating the short channel effect also helps to suppress the generation of large leakage currents.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2 through 5 are cross-sectional views showing various stages of fabricating a semiconductor structure in accordance with the flow of FIG. 1 in accordance with a preferred embodiment of the present invention.
  • FIG. 6 is a graph showing the resistivity of nickel-silicide formed at different temperatures by depositing Ni layers of different thicknesses
  • FIG. 7 is a resistivity of nickel platinum-silicide formed by depositing NiPt layers of different thicknesses and compositions at different temperatures;
  • FIG. 8 is a schematic cross-sectional view of a conventional metal oxide semiconductor field effect transistor device. detailed description
  • FIG. 1 a method of forming a semiconductor structure in FIG. 1 will be specifically described with reference to FIGS. 2 to 5.
  • step S101 a substrate 100 is provided, a dummy gate stack is formed on the substrate 100, sidewalls 240 are formed on sidewalls of the dummy gate stack, and the dummy gate is formed A source/drain region 110 and a source/drain extension region 111 are formed on both sides of the stack, wherein the dummy gate stack includes a gate dielectric layer 210, a dummy gate 220, and a cap layer 230.
  • the substrate 100 includes a silicon substrate (e.g., a silicon wafer).
  • the substrate 100 can include various doped configurations in accordance with design requirements well known in the art (e.g., a P-type substrate or an N-type substrate).
  • the substrate 100 in other embodiments may also include other basic semiconductors (e.g., Group III-V materials) such as germanium.
  • the substrate 100 may include a compound semiconductor such as silicon carbide, gallium arsenide, or indium arsenide.
  • substrate 100 can have, but is not limited to, a thickness of about a few hundred microns, such as can range from 400 ⁇ m to 800 ⁇ m.
  • isolation regions such as shallow trench isolation (STI) structures 120, may be formed in substrate 100 to electrically isolate the continuous field effect transistor devices.
  • STI shallow trench isolation
  • the gate dielectric layer 210 is first formed on the substrate 100.
  • the gate dielectric layer 210 may be formed of silicon oxide, silicon nitride, or a combination thereof, in other implementations.
  • it may be a high K medium, for example, one of Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO or a combination thereof, and the thickness thereof may be 2-10 nm; then, on the gate dielectric layer 210, by depositing, for example, polysilicon, polycrystalline SiGe, amorphous silicon, and/or doped or undoped silicon oxide and silicon nitride, silicon oxynitride, Silicon carbide, or even metal, forms a dummy gate 220, which may have a thickness of 10-80 nm; finally, a cap layer 230 is formed on the dummy gate 220, for example, by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and The combination is formed to protect the top region of the dummy gate 220 to
  • a shallower source/drain extension region 111 is first formed in the substrate 100 by low energy implantation.
  • P-type or N-type dopants or impurities may be implanted into the substrate 100, for example, for PMOS, the source/drain extension region 111 may be P-type doped SiGe; for NMOS, source/drain extension regions 111 may be N-doped Si.
  • the semiconductor structure is then annealed to activate doping in the source/drain extension 111, which may be formed by other suitable methods including rapid annealing, spike annealing, and the like. Since the thickness of the source/drain extension region 111 is shallow, the short channel effect can be effectively suppressed. Alternatively, source/drain extensions 111 may also be formed later in source/drain regions 110.
  • sidewall spacers 240 are formed on sidewalls of the dummy gate stack for spacing the gates.
  • the sidewall spacers 240 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 240 may have a multi-layered structure.
  • the sidewall spacers 240 may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • source/drain regions 110 are implanted into the substrate 100, thereby forming source/drain regions 110 on both sides of the dummy gate stack, for example,
  • source/drain regions 110 may be P-type doped SiGe; for NMOS, source/drain regions 110 may be N-type doped Si.
  • the energy injected into the source/drain region 110 is greater than the energy implanted in the source/drain extension region 111, so that the thickness of the source/drain region 110 is formed to be greater than the thickness of the source/drain extension region 111, and
  • the source/drain extension region 111 has a ladder profile.
  • the semiconductor structure is then annealed to activate doping in source/drain regions 110, which may be formed by other suitable methods including rapid annealing, spike annealing, and the like.
  • step S102 at least a portion of the sidewall spacers 240 are removed to expose at least a portion of the source/drain extension regions 111.
  • wet etching and/or drying may be employed. The etch process removes some or all of the sidewall spacers 240 and exposes some or all of the source/drain extension regions 111 under the sidewall spacers 240.
  • the wet etching process includes tetrakis ammonium hydroxide (TMAH), potassium hydroxide (KOH) or other suitable etching solution; the dry etching process includes sulfur hexafluoride (SF 6 ), hydrogen bromide (HBr), hydrogen iodide (HI), chlorine, argon, helium, decane (and chlorodecane), hydrides of carbon such as acetylene, ethylene, and combinations thereof, and/or other suitable materials.
  • TMAH tetrakis ammonium hydroxide
  • KOH potassium hydroxide
  • etching solution includes sulfur hexafluoride (SF 6 ), hydrogen bromide (HBr), hydrogen iodide (HI), chlorine, argon, helium, decane (and chlorodecane), hydrides of carbon such as acetylene, ethylene, and combinations thereof, and/or other suitable materials.
  • the material of the dummy gate 220 is made of Si or metal, in order to prevent the metal used to form the metal silicide layer and the metal as the dummy gate from being affected in the subsequent process, the size of the dummy gate stack is affected, thereby affecting It is not appropriate to remove the sidewall spacers 240 until the size of the gate stack structure formed after the replacement gate process is performed; if the dummy gate 220 is made of a material that does not react with the deposited metal layer, the sidewall spacers 240 may all be removed. The region where the source/drain extension region 111 reacts with the deposited metal is maximized, thereby reducing the contact resistance between the source/drain extension region and the metal silicide layer.
  • a thin metal layer is formed on the upper surface of the source/drain region 110 and the source/drain extension region 111 exposed after removing at least a portion of the sidewall spacer 240.
  • the formed metal silicide layer 112 can be made thermally stable at a relatively high temperature (e.g., 850 ° C), and can maintain a low resistivity. It is advantageous to reduce the increase in the resistivity of the metal silicide layer 112 caused by the high temperature annealing in the subsequent semiconductor structure fabrication process.
  • the material of the metal layer 250 includes one or a combination of Co, Ni, NiPt.
  • the thickness of the metal layer 250 formed of Co is less than 5 nm.
  • the thickness of the metal layer 250 formed of Ni is less than 4 nm, preferably between 2-3 nm, with reference to FIG. Figure 6 shows the resistance of nickel-silicide formed by depositing Ni layers of different thicknesses at different temperatures.
  • the abscissa indicates the temperature at which rapid thermal processing (PRT) is performed, and the ordinate indicates the resistance of nickel-silicide. Different curves indicate Ni layers of different thickness deposited when nickel-silicide is formed. D 6 It can be seen that when the temperature of the rapid thermal processing process reaches 700 ° C or higher, the resistance of the nickel-silicide formed by depositing the metal Ni layer to a thickness of 2-3 nm is relatively low.
  • the thickness of the metal silicide layer 112 is approximately twice that of the metal layer 250, for example, the thickness of the NiSi formed when the thickness of the deposited Ni layer is 4 nm. About 8nm.
  • the thickness of the metal layer 250 formed of NiPt is less than 3 nm, and the content of Pt in NiPt is less than 5%
  • Figure 7 shows the resistance of nickel-platinum-silicide formed by depositing NiPt layers of different thicknesses at different temperatures.
  • Figure 7 consists of three graphs of upper, middle and lower, and the abscissa indicates the temperature at which the rapid thermal processing is performed. The coordinates represent the resistance of nickel platinum-silicide.
  • the different curves in the above figure indicate that the metal layer 250 is NiPt, and the content of Ni is 86%, and the content of Pt is 14%, the NiPt layer of different thickness;
  • the different curves in the figure indicate that the metal layer 250 is NiPt, and the content of Ni is 92%, and the content of Pt is 8%, the NiPt layers of different thicknesses;
  • the different curves in the following figure indicate that the metal layer 250 is NiPt When the content of Ni is 96% and the content of Pt is 4%, the NiPt layer of different thickness is used.
  • Figure 7 when the temperature of the rapid thermal processing process reaches 700!
  • the resistivity of the formed nickel platinum-silicide is relatively low, that is, the thermal stability is good. Therefore, if the material of the metal layer 250 is NiPt, the thickness of the metal layer 250 formed of NiPt is less than 3 nm, and preferably, the content of Pt in the NiPt is less than 5%.
  • the semiconductor structure is annealed, and after annealing, a metal silicide layer 112 is formed on the upper surface of the source/drain region 110 and the exposed region of the source/drain extension region 111, the metal
  • the silicide layer 112 includes one or a combination of CoSi 2 , NiSi or Ni(Pt)Si 2- y having a thickness of less than 10 nm.
  • the residual metal layer 250 that does not participate in the reaction to form the metal silicide layer 112 is removed by selective etching.
  • the fabrication of the semiconductor structure is then completed in accordance with the steps of a conventional semiconductor fabrication process. For example, depositing an interlayer dielectric layer on a substrate of the semiconductor structure; then performing a replacement gate process to anneal the high-k gate dielectric layer; and etching the interlayer dielectric layer to form a contact hole and filling the contact hole The metal is contacted to form a contact plug. Since the above conventional manufacturing processes are well known to those skilled in the art, they will not be described herein. [0041] After the above steps are completed, in the semiconductor structure, not only the source/drain region 110 but also the metal silicide layer 112 is formed on the source/drain extension region 111, which lowers the contact resistance, thereby improving The performance of the semiconductor structure.
  • the metal silicide layer 112 is also thermally stable, and can maintain a low electrical resistance up to 850 ° C, so even if there is high temperature treatment in the subsequent process, such as high temperature annealing of the high K gate dielectric layer in the replacement gate process
  • the resistance of the metal silicide layer 112 is also not increased, thereby facilitating a reduction in the performance of the semiconductor structure.
  • the thickness of the metal silicide layer 112 is less than 10 nm, a certain distance may exist between the bonding surface of the source/drain extension region and the substrate, so that the short channel effect is not easily aggravated, and the suppression is also suppressed. Large junction leakage current generation.
  • the semiconductor structure will be described below with reference to FIG.
  • FIG. 5 is a cross-sectional view of the semiconductor structure finally formed after the steps shown in FIG. 1 are completed.
  • the semiconductor structure includes: a substrate 100, source/drain regions 110, and source/drain extension regions 111.
  • the source/drain region 110 and the source/drain extension region 111 are both formed in the substrate 100; the source/drain extension region 111 has a thickness smaller than the source/drain region 110, and
  • the source/drain regions 110 have a ladder-like profile; since the thickness of the source/drain extension regions 111 is thin, d and short channel effects can be effectively reduced.
  • the presence of the metal silicide layer 112 on the source/drain regions 110 and at least a portion of the upper surface of the source/drain extension regions 111 reduces contact resistance, thereby improving the performance of the semiconductor structure.
  • the layer 112 comprises a metal silicide CoSi 2, NiSi or Ni (Pt) Si 2 ⁇ or a combination of one having a thickness of less than 10nm.
  • the metal silicide layer 112 is thermally stable, it can maintain a low electrical resistance at up to 850 ° C, so even if there is high temperature treatment in the subsequent process, such as high temperature annealing of the high K gate dielectric layer in the replacement gate process The resistance of the metal silicide layer 112 is also not increased, thereby contributing to a reduction in the performance of the semiconductor structure.
  • the thickness of the metal silicide layer 112 is thin, and there is a certain distance from the bonding surface between the source/drain extension region and the substrate, the short channel effect is not easily aggravated, and the suppression is also facilitated. Large junction leakage current generation.
  • the dummy gate 220 may be formed using a material that does not react with the deposited metal layer 250, including but not limited to oxides, nitrides, and any combination thereof.
  • the dummy gate 220 does not need special protection, so all the sidewall spacers 240 can be removed to maximize the exposure of the source/drain extension region 111, thereby increasing the region where the source/drain extension region 111 reacts with the metal layer 250, thereby The contact resistance between the source/drain extension region and the metal silicide layer is lowered, and the performance of the semiconductor structure is improved.
  • each part in each embodiment of the semiconductor structure may be the same as those described in the method embodiment of the foregoing semiconductor structure, and are not described herein.

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Description

一种半导体结构及其制造方法
[0001]本申请要求了 2010年 12月 3 日提交的、 申请号为 201010572616.8、 发明名称为 "一种半导体结构及其制造方法" 的中国专利申请的优选权， 其 全部内容通过引用结合在本申请中。
技术领域
[0002]本发明涉及半导体制造技术，尤其涉及一种半导体结构及其制造方 法。 背景技术
[0003]金属氧化物半导体场效应晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET)是一种可以广泛应用在数字电路和模拟 电路中的晶体管。
[0004]图 8为常规金属氧化物半导体场效应晶体管器件的剖面示意图，如 图 8所示， 该 MOSFET包括： 衬底 100、 源 /漏区 110、 源 /漏延伸区 111、 伪栅堆叠以及侧墙 240。 其中， 所述伪栅堆叠形成于所述衬底 100之上， 包括栅介质层 210、 伪栅极 220以及覆盖层 230; 所述源 /漏区 110形成于 所述衬底 100之中， 位于所述伪栅堆叠两侧； 所述源 /漏延伸区 111从所 述源 /漏区 110延伸至所述伪栅堆叠以下， 其厚度小于所述源 /漏区 110; 所述侧墙 240位于所述伪栅堆叠的侧壁上， 覆盖所述源 /漏延伸区 111 ; 在所述源 /漏区 110上存在接触层 112 (利于减小接触电阻）， 对于含硅衬 底来说是形成金属硅化物层。 在下文中以含硅衬底为例进行描述， 将接 触层称为金属硅化物层。
[0005]上述方法虽然可以降低源 /漏区与金属硅化物层之间的接触电阻， 但该方法只是限定于在源 /漏区上形成金属硅化物层， 而没有在位于侧墙 之下的源 /漏延伸区上形成金属硅化物层， 无法进一步降低源 /漏延伸区与 金属硅化物层之间的接触电阻， 提高该 MOSFET的性能； 此外， 在替代 栅工艺中， 需要在形成金属硅化物层 112以及覆盖源 /漏区 110的层间介 质层之后除去伪栅堆叠， 然后形成由高 K介质材料构成的 MOSFET的栅 介质层， 从而有效地减小栅极漏电流。 但在最初形成高 K栅介质层时， 高 K栅介质层的分子结构可能会稍有缺陷。 为了修复该缺陷， 需要在较 高的温度 (600°C -800°C )下对其进行退火。 但是， MOSFET 中金属硅化物 层中使用的金属或合金不能承受对高 K介质层进行退火所需的高温， 在 高温下其结构会发生变化， 从而导致金属硅化物电阻率的增加， 进而降 低晶体管的性能。
[0006]因此， 如何既可以有效地降低半导体结构中的接触电阻， 又可以使 半导体结构在后续的高温工艺中维持良好的性能， 是一个亟待解决的问 题。 发明内容
[0007]本发明的目的是提供一种半导体结构及其制造方法，既可以减小接 触电阻， 又可以在高温工艺中保持半导体结构的性能。
[0008]根据本发明的一个方面， 提供一种半导体结构的制造方法， 该方法 包括以下步骤：
[0009]提供一个衬底， 在所述衬底上形成伪栅堆叠、 在所述伪栅堆叠侧壁形 成侧墙、 在所述伪栅堆叠两侧形成源 /漏区以及源 /漏延伸区；
[0010]去除至少部分所述侧墙， 以暴露至少部分所述源 /漏延伸区；
[0011]在所述源 /漏区以及暴露的所述源 /漏延伸区上形成接触层， 所述接触 层为 CoSi2、NiSi或者 Ni(Pt)Si2_y中的一种或其组合且所述接触层的厚度小于
10nm„
[0012]本发明另一方面还提出一种半导体结构， 包括衬底、 源 /漏区、 源 /漏 延伸区和栅极， 其中：
[0013]所述源 /漏区和所述源 /漏延伸区形成于所述衬底之中， 所述源 /漏延伸 区的厚度小于所述源 /漏区的厚度；
[0014]在所述源 /漏区、以及至少部分所述源 /漏延伸区的上表面存在接触层， 所述接触层 (112)为 CoSi2、 NiSi或者 Ni(Pt)Si^y中的一种或其组合且所述接 触层（112)的厚度小于 10nm。
[0015]与现有技术相比， 本发明具有以下优点：
[0016]采用本发明提供的技术方案， 不但在源 /漏区上形成接触层，还在部分 甚至是全部源 /漏延伸区上形成接触层， 且使所述接触层为 CoSi2、 NiSi或者 Ni(Pt)Si2_y中的一种或其组合以及所述接触层的厚度小于 10nm, 可使所述接 触层在后续去除伪栅堆叠并形成栅堆叠时的退火温度（如 700°C-800°C ) 下 仍具有热稳定性， 可在高达 850°C时仍可保持较低的电阻， 既降低了接触 电阻， 又利于减少半导体结构性能的下降； 此外， 由于在源 /漏延伸区上形 成的接触层的厚度非常薄，且在去除部分侧墙时，所述接触层与所述源 /漏延 伸区和衬底之间的 PN结 (junction)还可存在一定的距离， 从而不易加重短沟 道效应， 也利于抑制较大漏电流的产生。 附图说明
[0017]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本 发明的其它特征、 目的和优点将会变得更明显：
[0018]图 1为根据本发明的半导体结构制造方法的流程图；
[0019]图 2至图 5为根据本发明的一个优选实施例按照图 1所示流程制造 半导体结构的各个阶段的剖面示意图。
[0020]图 6为沉积不同厚度的 Ni层所形成的镍-硅化物在不同温度下的电 阻率；
[0021]图 7为沉积不同厚度和成分的 NiPt层所形成的镍铂-硅化物在不同 温度下的电阻率； 以及
[0022]图 8为常规金属氧化物半导体场效应晶体管器件的剖面示意图。 具体实施方式
[0023]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不 能解释为对本发明的限制。 [0024]下文的公开提供了许多不同的实施例或例子用来实现本发明的不 同结构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行 描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本 发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了筒化和 清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此 夕卜， 本发明提供了各种特定的工艺和材料的例子， 但是本领域技术人员 可以意识到其他工艺的可应用于性和 /或其他材料的使用。 应当注意， 在 附图中所图示的部件不一定按比例绘制。 本发明省略了对公知组件和处 理技术及工艺的描述以避免不必要地限制本发明。
[0025]下面，将结合图 2至图 5对图 1中形成半导体结构的方法进行具体 地描述。
[0026]参考图 1和图 2, 在步骤 S101中， 提供衬底 100, 在所述衬底 100 上形成伪栅堆叠、 在所述伪栅堆叠侧壁形成侧墙 240、 在所述伪栅堆叠两 侧形成源 /漏区 110以及源 /漏延伸区 111 , 其中所述伪栅堆叠包括栅介质 层 210、 伪栅极 220和覆盖层 230。
[0027]在本实施例中， 衬底 100包括硅衬底 (例如硅晶片）。 根据现有技术 公知的设计要求 (例如 P型衬底或者 N型衬底），衬底 100可以包括各种掺 杂配置。 其他实施例中衬底 100还可以包括其他基本半导体（如 III-V族 材料）， 例如锗。 或者， 衬底 100可以包括化合物半导体， 例如碳化硅、 砷化镓、 砷化铟。 典型地， 衬底 100 可以具有但不限于约几百微米的厚 度， 例如可以在 400 μ m-800 μ m的厚度范围内。
[0028]特别地， 可以在衬底 100 中形成隔离区， 例如浅沟槽隔离（STI)结 构 120, 以便电隔离连续的场效应晶体管器件。
[0029]在形成伪栅堆叠时， 首先在衬底 100上形成栅介质层 210, 在本实 施例中， 所述栅介质层 210 可以为氧化硅、 氮化硅及其组合形成， 在其 他实施例中， 也可以是高 K介质， 例如， Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO, A1203、 La203、 Zr02、 LaAlO 中的一种或其组合， 其厚 度可以为 2-10nm; 而后， 在所述栅介质层 210上通过沉积例如多晶硅、 多晶 SiGe、 非晶硅， 和 /或， 掺杂或未掺杂的氧化硅及氮化硅、 氮氧化硅、 碳化硅， 甚至金属形成伪栅极 220, 其厚度可以为 10-80nm; 最后， 在伪 栅极 220上形成覆盖层 230, 例如通过沉积氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合形成， 用以保护伪栅极 220的顶部区域， 防止伪栅极 220 的顶部区域在后续形成金属硅化物层的工艺中与沉积的金属层发生反 应。 在另一个实施例中， 伪栅堆叠也可以没有栅介质层 210, 而是在后续 的替代栅工艺中除去伪栅堆叠后形成栅介质层。
[0030]在形成伪栅堆叠之后，首先通过低能注入的方式在衬底 100中形成 较浅的源 /漏延伸区 111。 可以向衬底 100中注入 P型或 N型掺杂物或杂 质， 例如， 对于 PMOS来说， 源 /漏延伸区 111可以是 P型掺杂的 SiGe; 对于 NMOS来说， 源 /漏延伸区 111可以是 N型掺杂的 Si。 然后对所述半 导体结构进行退火， 以激活源 /漏延伸区 111 中的掺杂， 退火可以采用包 括快速退火、 尖峰退火等其他合适的方法形成。 由于源 /漏延伸区 111 的 厚度较浅， 可以有效地抑制短沟道效应。 可选地， 源 /漏延伸区 111也可 以后于源 /漏区 110形成。
[0031]接着， 在所述伪栅堆叠的侧壁上形成侧墙 240, 用于将栅极隔开。 侧墙 240可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其 他合适的材料形成。 侧墙 240可以具有多层结构。 侧墙 240可以通过包 括沉积刻蚀工艺形成， 其厚度范围可以是 lOnm-lOOnm, 如 30nm、 50nm 或 80nm。
[0032]随后， 以所述侧墙 240为掩膜， 向衬底 100中注入 P型或 N型掺 杂物或杂质，进而在所述伪栅堆叠两侧形成源 /漏区 110,例如，对于 PMOS 来说， 源 /漏区 110可以是 P型掺杂的 SiGe; 对于 NMOS来说， 源 /漏区 110可以是 N型掺杂的 Si。 形成源 /漏区 110所注入的能量要大于形成源 / 漏延伸区 111所注入的能量， 从而形成的所述源 /漏区 110的厚度大于所 述源 /漏延伸区 111的厚度， 并与所述源 /漏延伸区 111呈梯状轮廓。 然后 对所述半导体结构进行退火， 以激活源 /漏区 110中的掺杂， 退火可以采 用包括快速退火、 尖峰退火等其他合适的方法形成。
[0033]参考图 1和图 3 , 在步骤 S102中， 去除至少部分侧墙 240, 以暴露 至少部分所述源 /漏延伸区 111。 具体地， 可以采用包括湿法刻蚀和 /或干 法刻蚀的工艺去除部分或者全部侧墙 240,暴露在所述侧墙 240下的部分 或者全部源 /漏延伸区 111。 其中， 湿法刻蚀工艺包括四曱基氢氧化铵 (TMAH)、 氢氧化钾 (KOH)或者其他合适刻蚀的溶液； 干法刻蚀工艺包括 六氟化硫 (SF6)、 溴化氢 (HBr)、 碘化氢 (HI)、 氯、 氩、 氦、 曱烷 （及氯代 曱烷）、 乙炔、 乙烯等碳的氢化物及其组合， 和 /或其他合适的材料。
[0034]如果伪栅极 220的材料采用 Si或者金属，为了防止在后续工艺中， 难以分离用以形成金属硅化物层的金属与作为伪栅极的金属而影响伪栅 堆叠的尺寸， 进而影响到执行替代栅工艺后所形成的栅堆叠结构的尺寸， 则不宜将侧墙 240全部去除； 如果伪栅极 220采用不会与沉积金属层发 生反应的材料， 则可以全部将侧墙 240去除， 最大限度地增大源 /漏延伸 区 111 与沉积金属产生反应的区域， 从而降低源 /漏延伸区与金属硅化物 层之间的接触电阻。
[0035]参考图 1和图 4, 在步骤 S103中， 在所述源 /漏区 110、 以及在去 除至少部分侧墙 240后所暴露的源 /漏延伸区 111上表面形成一层薄的金 属硅化物层 112。 具体地， 沉积一层薄的金属层 250以均勾覆盖所述衬底 100、 伪栅堆叠， 退火后在所述源 /漏区 110 以及所述源 /漏延伸区 111 的 暴露区域的上表面形成一层薄的金属硅化物层 112。通过选择沉积的金属 层 250的厚度和材料， 可以使得所形成的所述金属硅化物层 112在较高 温度（如 850°C )下， 仍具有热稳定性， 能保持较低的电阻率， 利于减少 在后续的半导体结构制造过程中高温退火所导致的金属硅化物层 112 电 阻率的变大。 其中， 所述金属层 250的材料包括 Co、 Ni、 NiPt中的一种 或者任意组合。
[0036]如果所述金属层 250的材料为 Co, 则由 Co所形成的金属层 250 的厚度小于 5nm。
[0037]如果所述金属层 250的材料为 Ni, 则由 Ni所形成的金属层 250的 厚度小于 4nm, 优选为 2-3nm之间， 参考图 6。 图 6为沉积不同厚度的 Ni层所形成的镍-硅化物在不同温度下的电阻， 其横坐标表示执行快速热 处理工艺（rapid thermal processing, PRT)的温度， 纵坐标表示镍-硅化物的 电阻， 不同的曲线表示形成镍-硅化物时所沉积的不同厚度的 Ni层。从图 6 可以看出， 当快速热处理工艺的温度达到 700 °C以上时， 沉积金属 Ni 层的厚度为 2-3nm所形成的镍 -硅化物的电阻相对较低。当所述金属层 250 的材料为 Ni时，形成所述金属硅化物层 112的厚度大概是所述金属层 250 的 2倍， 例如， 当沉积 Ni层的厚度为 4nm时， 形成的 NiSi的厚度大概 为 8nm。
[0038]如果所述金属层 250的材料为 NiPt,则由 NiPt所形成的金属层 250 的厚度小于 3nm, 且 NiPt中 Pt的含量小于 5%, 参考图 7。 图 7为沉积 不同厚度的 NiPt层所形成的镍铂-硅化物在不同温度下的电阻，图 7由上、 中、 下三个图构成， 其横坐标都表示执行快速热处理工艺的温度， 纵坐 标表示镍铂-硅化物的电阻， 上图中的不同曲线表示所述金属层 250 为 NiPt, 且 Ni的含量为 86%、 Pt的含量为 14%的时候， 不同厚度的 NiPt 层； 中图中的不同曲线表示所述金属层 250为 NiPt、且 Ni的含量为 92%、 Pt的含量为 8%的时候， 不同厚度的 NiPt层； 下图中的不同曲线表示所 述金属层 250为 NiPt、 且 Ni的含量为 96%、 Pt的含量为 4%的时候， 不 同厚度的 NiPt层。从图 7中可以看出， 当快速热处理工艺的温度达到 700 ！以上时， 沉积的 NiPt层中 Pt含量为 4%、且 NiPt层厚度为 2nm的情况 下， 所形成的镍铂-硅化物的电阻率相对较低， 即热稳定性较好。 因此， 如果所述金属层 250的材料选用 NiPt时， 则由 NiPt所形成的金属层 250 的厚度小于 3nm, 优选地， NiPt中 Pt的含量小于 5%。
[0039]沉积金属层 250后， 对该半导体结构进行退火， 退火后在源 /漏区 110、 以及所述源 /漏延伸区 111 的暴露区域的上表面形成金属硅化物层 112, 所述金属硅化物层 112包括 CoSi2、 NiSi或者 Ni(Pt)Si2-y中的一种或 其组合， 其厚度小于 10nm。 最后通过选择性刻蚀的方式去除未参加反应 形成金属硅化物层 112的残留的金属层 250。
[0040]随后按照常规半导体制造工艺的步骤完成该半导体结构的制造。例 如， 在该半导体结构的衬底上沉积层间介质层； 然后进行替代栅工艺， 并对高 K栅介质层进行退火； 以及刻蚀层间介质层以形成接触孔， 并在 接触孔中填充接触金属以形成接触塞。 由于上述常规制造工艺为本领域 人员所公知， 所以在此不再赘述。 [0041]在上述步骤完成后， 在所述半导体结构中， 不但在源 /漏区 110上， 还在源 /漏延伸区 111上形成了金属硅化物层 112 , 降低了接触电阻，从而 提高了该半导体结构的性能。 所述金属硅化物层 112 还具有热稳定性， 在高达 850 °C时仍可保持较低的电阻， 所以即使后续工艺中存在高温处 理， 比如替代栅工艺中对高 K栅介质层进行高温退火， 所述金属硅化物 层 112的电阻也不会升高， 从而利于减小半导体结构性能的下降。 此外， 由于所述金属硅化物层 112的厚度小于 10nm,与所述源 /漏延伸区和衬底 之间的结合面还可存在一定的距离， 从而不易加重短沟道效应， 也利于 抑制了较大结漏电流的产生。 为了更清楚地理解根据上述半导体结构的 制造方法所形成的半导体结构， 下面根据图 5 对所述半导体结构进行说 明。
[0042]参考图 5 , 图 5为完成图 1中所示的步骤后最终形成的半导体结构 的剖面图。 在本实施例中， 所述半导体结构包括： 衬底 100、 源 /漏区 110 以及源 /漏延伸区 111。 其中， 所述源 /漏区 110和所述源 /漏延伸区 111均 形成于所述衬底 100之中； 所述源 /漏延伸区 111的厚度小于所述源 /漏区 110, 与所述源 /漏区 110呈梯状轮廓； 由于所述源 /漏延伸区 111的厚度较 薄， 所以可以有效地减 d、短沟道效应。
[0043]在所述源 /漏区 110以及至少部分所述源 /漏延伸区 111的上表面存 在金属硅化物层 112 , 降低了接触电阻， 从而提高该半导体结构的性能。 所述金属硅化物层 112包括 CoSi2、 NiSi或者 Ni(Pt)Si2^中的一种或其组 合， 其厚度小于 10nm。 由于所述金属硅化物层 112具有热稳定性， 在高 达 850°C时仍可保持较低的电阻， 所以即使后续工艺中存在高温处理， 比 如替代栅工艺中对高 K栅介质层进行高温退火， 所述金属硅化物层 112 的电阻也不会升高， 从而利于减少半导体结构性能的下降。 此外， 由于 所述金属硅化物层 112的厚度较薄， 且与所述源 /漏延伸区和衬底之间的 结合面还可存在一定的距离， 从而不易加重短沟道效应， 也利于抑制较 大结漏电流的产生。
[0044]优选地，所述伪栅极 220可以采用与沉积金属层 250不发生反应的 材料来生成， 所述材料包括但不限于氧化物、 氮化物及其任意组合， 在 这种情况下， 伪栅极 220无需特别保护， 所以可以去除全部侧墙 240以 最大限度地暴露源 /漏延伸区 111 , 增加了源 /漏延伸区 111 与金属层 250 发生反应的区域， 从而降低了源 /漏延伸区与金属硅化物层之间的接触电 阻， 提高了该半导体结构的性能。
[0045]其中， 对半导体结构各实施例中各部分的结构组成、材料及形成方 法等均可与前述半导体结构形成的方法实施例中描述的相同， 不在赘述。
[0046]虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本 发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施 例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员 应当容易理解在保持本发明保护范围内的同时， 工艺步骤的次序可以变 化。
[0047]此外，本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或者以后即 将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它 们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的 结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要求旨 在将这些工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含在其保 护范围内。

Claims

权 利 要 求
1. 一种半导体结构的制造方法， 该方法包括以下步骤：
a)提供衬底 (100), 在所述衬底 (100)上形成伪栅堆叠、 在所述伪栅堆叠 侧壁形成侧墙 (240)、 在所述伪栅堆叠两侧形成源 /漏区（110)以及源 /漏延伸区
(111)；
b) 去除至少部分所述侧墙 (240) , 以暴露至少部分所述源 /漏延伸区 (111)；
c) 在所述源 /漏区（110)以及暴露的所述源 /漏延伸区（111)上形成接触层 (112), 所述接触层（112)为 CoSi2、 NiSi或者 Ni(Pt)Si2-y中的一种或其组合且 所述接触层 (112)的厚度小于 10nm。
2. 根据权利要求 1所述的方法， 其中， 所述步骤 c)包括：
形成金属层 (250)以覆盖所述衬底（100)、 伪栅堆叠以及侧墙 (240), 所述 金属层 (250)的材料包括 Co、 Ni、 NiPt中的一种或其组合；
执行退火操作， 以使所述金属层 (250)与所述源 /漏区（110)以及暴露的所 述源 /漏延伸区（111)表面反应；
去除未反应的所述金属层 (250)。
3. 根据权利要求 2述的方法， 其中：
如果所述金属层 (250)的材料为 Co, 则 Co的厚度小于 5nm;
如果所述金属层 (250)的材料为 Ni, 则 Ni的厚度小于 4nm; 以及 如果所述金属层 (250)的材料为 NiPt, 则 NiPt的厚度小于 3nm。
4. 根据权利要求 2所述的方法， 其中：
如果所述金属层 (250)的材料为 NiPt, 则 NiPt中 Pt的含量小于 5%。
5. 根据权利要求 1述的方法， 其中：
所述接触层 (112)的厚度小于 6nm。
6. 一种半导体结构， 该半导体结构包括衬底 (100)、 源 /漏区（110)、 源 / 漏延伸区（111)和栅极， 其中： 述源 /漏延伸区（111)的厚度小于所述源 /漏区（110)的厚度， 其特征在于： 在所述源 /漏区（110)以及至少部分所述源 /漏延伸区（111)的上表面存在 接触层 (112) , 所述接触层 (112)为 CoSi2、 NiSi或者 Ni(Pt)Si2-y中的一种或其 组合且所述接触层 (112)的厚度小于 10nm。
7. 根据权利要求 6所述的半导体结构， 其中：
所述接触层 (112)的厚度小于 6nm。
PCT/CN2011/072917 2010-12-03 2011-04-18 一种半导体结构及其制造方法 WO2012071843A1 (zh)

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