CN103779212B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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CN103779212B
CN103779212B CN201210397791.7A CN201210397791A CN103779212B CN 103779212 B CN103779212 B CN 103779212B CN 201210397791 A CN201210397791 A CN 201210397791A CN 103779212 B CN103779212 B CN 103779212B
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conducting material
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CN103779212A (zh
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尹海洲
蒋葳
朱慧珑
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Institute of Microelectronics of CAS
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Abstract

本发明提供一种半导体结构的制造方法，包括：提供SOI衬底(200)，所述衬底从下至上依次包括基底层(201)、绝缘埋层(202)和表面有源层(203)；在所述衬底上形成栅堆叠；去除所述栅堆叠两侧的表面有源层(203)以及部分绝缘埋层(202)，形成开口(240)；在所述开口(240)中填充半导体材料，形成源/漏区(250)。相应地，本发明还提供了一种半导体结构。本发明通过将源/漏区延伸至衬底绝缘埋层中，在降低源漏串联电阻的同时，不会造成栅极和源漏之间的寄生电容增大。

Description

半导体结构及其制造方法
技术领域
本发明涉及半导体制造技术，尤其涉及一种半导体结构及其制造方法。
背景技术
减小源漏结深是抑制短沟道效应与穿通效应以及改善阈值特性的有效措施之一，通过较小的源漏结深可使MOSFET的短沟道效应及穿通效应得以改善，亚阈值特性较好。UTBSOI器件的衬底是超薄的SOI层，可以很好的控制源漏杂质扩散，形成浅结。但较小的源漏结深将引起源漏串联电阻增大，器件的输出电流和跨导减小，使器件及其电路的驱动能力和速度降低。另外较浅的源漏结也带来源漏接触的可靠性问题。抑制短沟道效应和避免源漏穿通及获得较好的亚阈值特性要求源漏结深尽可能小，而提高跨导和速度则要求源漏结深尽可能大，这是小尺寸MOSFET器件中需要解决的一个矛盾。解决这一矛盾的方法是采用抬高源漏的结构。
抬高源漏MOSFET可以降低源漏串联电阻，从而获得更好的器件特性。但是抬高源漏MOSFET减小了栅极与源漏之间的距离，从而造成栅极和源漏之间的寄生电容增大。图1为抬高源漏MOSFET的剖面示意图，其中源漏区130的上表面高于栅堆叠的下表面。
发明内容
针对上述抬高源漏MOSFET造成寄生电容增大的问题，本发明提供一种半导体结构及其制造方法，将源/漏区延伸至衬底绝缘埋层中，在降低源漏串联电阻的同时，不会造成栅极和源漏之间的寄生电容增大。
根据本发明的一个方面，提供一种半导体结构的制造方法，该方法包括以下步骤：
a)提供SOI衬底，所述衬底从下至上依次包括基底层、绝缘埋层和表面有源层；
b)在所述衬底上形成栅堆叠；
c)去除所述栅堆叠两侧的表面有源层以及部分绝缘埋层，形成开口；
d)在所述开口中填充半导体材料，形成源/漏区。
根据本发明的另一个方面，提供一种半导体结构，包括SOI衬底、栅堆叠和源/漏区，其中：
所述SOI衬底从下至上依次包括基底层、绝缘埋层和表面有源层；
所述栅堆叠位于所述表面有源层之上；
所述源/漏区位于所述栅堆叠的两侧，并延伸至绝缘埋层中。
本发明通过将源/漏区延伸至衬底绝缘埋层中，在降低源漏串联电阻的同时，不会造成栅极和源漏之间的寄生电容增大。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为现有技术的抬高源漏M OSFET的剖面示意图；
图2为根据本发明的半导体结构制造方法的流程图；
图3至图8为根据本发明按照图2所示流程制造半导体结构的各个阶段的剖面示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了各种特定的工艺和材料的例子，但是本领域技术人员可以意识到其他工艺的可应用性和/或其他材料的使用。应当注意，在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
下面，将结合图3至图8对图2中形成半导体结构的方法进行具体地描述。
参考图2和图3，在步骤S101中，提供SOI衬底200，所述衬底从下至上依次包括基底层201、绝缘埋层202和表面有源层203。
在本实施例中，所述基底层201为单晶硅。在其他实施例中，所述基底层201还可以包括其他基本半导体，例如锗。或者，所述基底层201还可以包括化合物半导体，例如，碳化硅、砷化镓、砷化铟或者磷化铟。典型地，所述基底层201的厚度可以约为但不限于几百微米，例如从0.1mm-1.5mm的厚度范围。
所述绝缘埋层202可以为氧化硅、氮化硅或者其他任何适当的绝缘材料，典型地，所述绝缘埋层202的厚度范围为100nm-300nm。
所述表面有源层203可以为所述基底层201包括的半导体材料中的任何一种。在本实施例中，所述表面有源层203为单晶硅。在其他实施例中，所述表面有源层203还可以包括其他基本半导体或者化合物半导体。根据现有技术公知的设计要求（例如P型衬底或者N型衬底），表面有源层203可以包括各种掺杂配置。对于N MOS，所述表面有源层203的掺杂类型为P型；对于PMOS，所述表面有源层203的掺杂类型为N型，其掺杂浓度为1015～1018cm-3。典型地，所述表面有源层203的厚度为10nm～100nm。
特别地，在步骤S101中，还包括在所述衬底中形成隔离区204，例如浅沟槽隔离(STI)结构，以便电隔离连续的半导体器件。所述浅沟槽隔离(STI)结构贯穿所述表面有源层203，与所述绝缘埋层202相接，也可以贯穿所述绝缘埋层202。
参考图2和图3，在步骤S102中，在所述衬底上形成栅堆叠。所述栅堆叠包括栅介质层210和栅极211。可选地，所述栅堆叠还可以包括覆盖在所述栅极211上的覆盖层212，例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成，用以保护栅极211的顶部区域，防止其在后续的工艺中受到破坏。所述栅介质层210位于所述衬底的表面有源层203之上，可以为高K介质，例如，HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合。在另一个实施例中，还可以是热氧化层，包括氧化硅、氮氧化硅；所述栅极介质层210的厚度可以为1nm～10nm，如5n m或8n m。而后在所述栅介质层210上形成栅极211，所述栅极211可以是通过沉积形成的重掺杂多晶硅，或是先形成功函数金属层（对于NMOS，例如TaC，TiN，TaTbN，TaErN，TaYbN，TaSiN，HfSiN，MoSiN，RuTax，NiTax等，对于PMOS，例如MoNx，TiSiN，TiCN，TaAlC，TiAlN，TaN，PtSix，Ni3Si，Pt，Ru，Ir，Mo，HfRu，RuOx），其厚度可以为1nm-20nm，如3nm、5nm、8nm、10nm、12nm或15nm，再在所述功函数金属层上形成重掺杂多晶硅、Ti、Co、Ni、Al、W或其合金等而形成栅极211。
在本发明的另外一些实施例中，也可采用后栅工艺（gate last），此时，栅堆叠包括栅极211（此时为伪栅）和承载所述栅极的栅介质层210。在所述栅介质层210上通过沉积例如多晶硅、多晶SiGe、非晶硅，掺杂或未掺杂的氧化硅及氮化硅、氮氧化硅、碳化硅，甚至金属形成栅极211（此时为伪栅），其厚度可以为10nm-80nm。可选地，还包括在所述栅极211（此时为伪栅）上形成覆盖层，例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成，用以保护伪栅极211的顶部区域，防止栅极211（此时为伪栅）的顶部区域在后续形成接触层的工艺中与沉积的金属层发生反应。在另一个采用后栅工艺实施例中，栅堆叠也可以没有栅介质层210，而是后续工艺步骤中，除去所述伪栅后，在填充功函数金属层之前形成栅介质层210。
可选地，如图4所示，形成所述栅堆叠之后，还包括以所述栅堆叠为掩模，向表面有源层203中注入P型或N型掺杂物或杂质，进而在所述栅堆叠两侧形成源/漏延伸区220。对于PMOS来说，源/漏延伸区220可以是P型掺杂的Si；对于N MOS来说，源/漏延伸区220可以是N型掺杂的Si。然后对所述半导体结构进行退火，以激活源/漏延伸区220中的杂质，退火可以采用包括快速退火、尖峰退火等其他合适的方法形成。
之后，可以形成附着于所述栅堆叠侧壁的侧墙。如图5所示，所述侧墙230形成于所述栅堆叠的侧壁上，用于将栅堆叠隔开。侧墙230可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙230可以具有多层结构。侧墙230可以通过包括沉积-刻蚀工艺形成，其厚度范围可以是10nm～100nm，如30nm、50nm或80nm。
参考图2和图6，在步骤S103中，去除所述栅堆叠两侧的表面有源层203以及部分绝缘埋层202，形成开口240。在本实施例中，先刻蚀表面有源层203，再刻蚀绝缘埋层202，并停止在绝缘埋层202中。以所述栅堆叠为掩模，采用等离子刻蚀等干法刻蚀，各向异性地刻蚀表面有源层203和绝缘埋层202。干法刻蚀工艺气体包括六氟化硫(SF6)、溴化氢(HBr)、碘化氢(Hl)、氯、氩、氦、甲烷（及氯代甲烷）、乙炔、乙烯等碳的氢化物及其组合，和/或其他合适的材料。
参考图2和图7，在步骤S104中，在所述开口240中填充半导体材料。所述半导体材料可以为掺杂的多晶硅或单晶硅。在本实施例中，通过沉积非晶硅并退火的方法形成多晶硅或单晶硅。可以通过离子注入和退火的方式进行掺杂，掺杂浓度为可以为1019～1021cm-3。对于N MOS，所述半导体材料可以为N型掺杂；对于PMOS，所述半导体材料可以为P型掺杂。退火可以采用包括快速退火、尖峰退火等其他合适的方法实施。填充所述半导体材料后，可以对所述半导体材料进行化学机械抛光(CM P)，使所述半导体材料的上表面与栅堆叠结构的上表面齐平(本文件内，术语“齐平”意指两者之间的高度差在工艺误差允许的范围内)。
如图8所示，去除部分所述半导体材料，使所述半导体材料的上表面与栅堆叠的下表面齐平，形成源/漏区250。可以使用湿法刻蚀和/或干法刻蚀的方式去除所述半导体材料。湿法刻蚀工艺包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)或者其他合适刻蚀的溶液；干法刻蚀工艺包括六氟化硫(SF6)、溴化氢(HBr)、碘化氢(Hl)、氯、氩、氦、甲烷（及氯代甲烷）、乙炔、乙烯等碳的氢化物及其组合，和/或其他合适的材料。可以通过控制刻蚀时间的长短，来控制刻蚀停止，使所述半导体材料的上表面与栅堆叠的下表面齐平。
本发明还提供了一种半导体结构，如图8所示，包括SOI衬底、栅堆叠、和源/漏区250，其中：所述SOI衬底从下至上依次包括基底层201、绝缘埋层202和表面有源层203；所述栅堆叠位于所述表面有源层203之上；所述源/漏区250位于所述栅堆叠的两侧，并延伸至绝缘埋层202中。所述半导体结构还可以包括侧墙，所述侧墙位于所述栅堆叠的侧壁上。所述源/漏区250的材料可以为掺杂的多晶硅或单晶硅，掺杂浓度为可以为1019～1021cm-3。对于NMOS，所述源/漏区250的掺杂类型为N型；对于PMOS，所述源/漏区250的掺杂类型为P型。所述源/漏区250的下表面低于绝缘埋层202的上表面，其相差范围可以为100nm-200nm。通过将源/漏区延伸至衬底绝缘埋层中，在降低源漏串联电阻的同时，不会造成栅极和源漏之间的寄生电容增大。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (7)

1.一种半导体结构的制造方法，该方法包括以下步骤：
a)提供SOI衬底(200)，所述衬底从下至上依次包括基底层(201)、绝缘埋层(202)和表面有源层(203)；
b)在所述衬底上形成栅堆叠；
c)去除所述栅堆叠两侧的表面有源层(203)以及部分绝缘埋层(202)，形成开口(240)，其中，先刻蚀表面有源层(203)，再刻蚀绝缘埋层(202)，并停止在绝缘埋层(202)中；
d)在所述开口(240)中填充半导体材料，形成源/漏区(250)。
2.根据权利要求1所述的方法，其中，在所述步骤b)中，还包括形成附着于所述栅堆叠侧壁的侧墙(230)。
3.根据权利要求1所述的方法，其中，在所述步骤d)中，所述半导体材料为掺杂的多晶硅或单晶硅，掺杂浓度为为1019～1021cm-3。
4.根据权利要求1所述的方法，其中，对于NMOS，所述半导体材料为N型掺杂；对于PMOS，所述半导体材料为P型掺杂。
5.根据权利要求3所述的方法，其中，通过沉积非晶硅并退火形成多晶硅或单晶硅。
6.根据权利要求5所述的方法，其中，还包括在退火之后去除部分所述半导体材料，使所述半导体材料的上表面与栅堆叠的下表面齐平。
7.根据权利要求6所述的方法，其中，通过化学机械抛光加刻蚀的方法去除部分所述半导体材料，并通过控制刻蚀时间的长短，来控制刻蚀停止。
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