WO2014059687A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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WO2014059687A1
WO2014059687A1 PCT/CN2012/083478 CN2012083478W WO2014059687A1 WO 2014059687 A1 WO2014059687 A1 WO 2014059687A1 CN 2012083478 W CN2012083478 W CN 2012083478W WO 2014059687 A1 WO2014059687 A1 WO 2014059687A1
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source
layer
gate stack
semiconductor structure
surface active
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PCT/CN2012/083478
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English (en)
French (fr)
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尹海洲
蒋葳
朱慧珑
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中国科学院微电子研究所
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Priority to US14/435,616 priority Critical patent/US20150287808A1/en
Publication of WO2014059687A1 publication Critical patent/WO2014059687A1/zh

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Abstract

本发明提供一种半导体结构的制造方法，包括：提供SOI衬底（200），所述衬底从下至上依次包括基底层（201）、绝缘埋层（202）和表面有源层（203）；在所述衬底上形成栅堆叠；去除所述栅堆叠两侧的表面有源层（203）以及部分绝缘埋层（202），形成开口（240）；在所述开口（240）中填充半导体材料，形成源/漏区（250）。相应地，本发明还提供了一种半导体结构。本发明通过将源/漏区延伸至衬底绝缘埋层中，在降低源漏串联电阻的同时，不会造成栅极和源漏之间的寄生电容增大。

Description

半导体结构及其制造方法
[0001]本申请要求了 2012年 10月 18日提交的、 申请号为 201210397791.7、 发明名称为"半导体结构及其制造方法"的中国专利申请的优先权， 其全部内 容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体制造技术，尤其涉及一种半导体结构及其制造方 法。 背景技术
[0003]减小源漏结深是抑制短沟道效应与穿通效应以及改善阈值特性的 有效措施之一， 通过较小的源漏结深可使 MOSFET的短沟道效应及穿通 效应得以改善， 亚阈值特性较好。 UTBSOI器件的衬底是超薄的 SOI层， 可以很好的控制源漏杂质扩散， 形成浅结。 但较小的源漏结深将引起源 漏串联电阻增大， 器件的输出电流和跨导减小， 使器件及其电路的驱动 能力和速度降低。 另外较浅的源漏结也带来源漏接触的可靠性问题。 抑 制短沟道效应和避免源漏穿通及获得较好的亚阈值特性要求源漏结深尽 可能小， 而提高跨导和速度则要求源漏结深尽可能大， 这是小尺寸 MOSFET 器件中需要解决的一个矛盾。 解决这一矛盾的方法是采用抬高 源漏的结构。
[0004】抬高源漏 MOSFET可以降低源漏串联电阻， 从而获得更好的器件 特性。 但是抬高源漏 MOSFET减小了栅极与源漏之间的距离， 从而造成 栅极和源漏之间的寄生电容增大。 图 1为抬高源漏 MOSFET的剖面示意 图， 其中源漏区 130的上表面高于栅堆叠的下表面。 发明内容
[0005】针对上述抬高源漏 MOSFET造成寄生电容增大的问题， 本发明提 供一种半导体结构及其制造方法， 将源 /漏区延伸至衬底绝缘埋层中， 在 降低源漏串联电阻的同时， 不会造成栅极和源漏之间的寄生电容增大。
[0006】根据本发明的一个方面，提供一种半导体结构的制造方法， 该方法 包括以下步骤：
a) 提供 SOI衬底， 所述衬底从下至上依次包括基底层、 绝缘埋层和表面 有源层；
b) 在所述衬底上形成栅堆叠；
c) 去除所述栅堆叠两侧的表面有源层以及部分绝缘埋层， 形成开口； d) 在所述开口中填充半导体材料， 形成源 /漏区。
[0007】根据本发明的另一个方面， 提供一种半导体结构， 包括 SOI衬底、 栅堆叠和源 /漏区， 其中：
[0008]所述 SOI衬底从下至上依次包括基底层、 绝缘埋层和表面有源层；
[0009]所述栅堆叠位于所述表面有源层之上；
[0010]所述源 /漏区位于所述栅堆叠的两侧， 并延伸至绝缘埋层中。
[0011]本发明通过将源 /漏区延伸至衬底绝缘埋层中， 在降低源漏串联电 阻的同时， 不会造成栅极和源漏之间的寄生电容增大。 附图说明
[0012]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本发明的其它特征、 目的和优点将会变得更明显：
[0013]图 1为现有技术的抬高源漏 MOSFET的剖面示意图；
[0014]图 2为根据本发明的半导体结构制造方法的流程图；
[0015]图 3至图 8为根据本发明按照图 2所示流程制造半导体结构的各个 阶段的剖面示意图。
[0016]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0017]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不 能解释为对本发明的限制。 [0018】下文的公开提供了许多不同的实施例或例子用来实现本发明的不 同结构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行 描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本 发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了筒化和 清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此 外， 本发明提供了各种特定的工艺和材料的例子， 但是本领域技术人员 可以意识到其他工艺的可应用性和 /或其他材料的使用。 应当注意， 在附 图中所图示的部件不一定按比例绘制。 本发明省略了对公知组件和处理 技术及工艺的描述以避免不必要地限制本发明。
[0019]下面，将结合图 3至图 8对图 2中形成半导体结构的方法进行具体 地描述。
[0020]参考图 2和图 3 , 在步骤 S101 中， 提供 SOI衬底 200 , 所述衬底 从下至上依次包括基底层 201、 绝缘埋层 202和表面有源层 203。
[0021】在本实施例中， 所述基底层 201为单晶硅。 在其他实施例中， 所述 基底层 201还可以包括其他基本半导体， 例如锗。 或者， 所述基底层 201 还可以包括化合物半导体， 例如， 碳化硅、 砷化镓、 砷化铟或者磷化铟。 典型地， 所述基底层 201 的厚度可以约为但不限于几百微米， 例如从 0.1 mm- 1.5 mm的厚度范围。
[0022]所述绝缘埋层 202可以为氧化硅、氮化硅或者其他任何适当的绝缘 材料， 典型地， 所述绝缘埋层 202的厚度范围为 100nm-300nm。
[0023]所述表面有源层 203可以为所述基底层 201包括的半导体材料中的 任何一种。 在本实施例中， 所述表面有源层 203 为单晶硅。 在其他实施 例中， 所述表面有源层 203 还可以包括其他基本半导体或者化合物半导 体。 根据现有技术公知的设计要求 （例如 P型衬底或者 N型衬底） ， 表 面有源层 203可以包括各种掺杂配置。 对于 NMOS , 所述表面有源层 203 的掺杂类型为 P型； 对于 PMOS , 所述表面有源层 203的掺杂类型为 N 型， 其掺杂浓度为 1015 ~ 1018cm-3。 典型地， 所述表面有源层 203的厚度 为 10nm~100nm。
[0024】特别地， 在步骤 S 101 中， 还包括在所述衬底中形成隔离区 204, 例如浅沟槽隔离（STI)结构， 以便电隔离连续的半导体器件。 所述浅沟槽 隔离（STI)结构贯穿所述表面有源层 203 , 与所述绝缘埋层 202相接，也可 以贯穿所述绝缘埋层 202。
[0025】参考图 2和图 3 , 在步骤 S102中， 在所述衬底上形成栅堆叠。 所 述栅堆叠包括栅介质层 210和栅极 211。 可选地， 所述栅堆叠还可以包括 覆盖在所述栅极 211上的覆盖层 212 , 例如通过沉积氮化硅、 氧化硅、 氮 氧化硅、 碳化硅及其组合形成， 用以保护栅极 211 的顶部区域， 防止其 在后续的工艺中受到破坏。 所述栅介质层 210 位于所述衬底的表面有源 层 203之上， 可以为高 K介质， 例如， Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO, A1203、 La203、 Zr02、 LaAlO 中的一种或其组合。 在另 一个实施例中， 还可以是热氧化层， 包括氧化硅、 氮氧化硅； 所述栅极 介质层 210的厚度可以为 lnm~10nm, 如 5nm或 8nm。 而后在所述栅介 质层 210上形成栅极 211 ,所述栅极 211可以是通过沉积形成的重掺杂多 晶硅， 或是先形成功函数金属层 （对于 NMOS , 例如 TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax等， 对于 PMOS , 例 如 MoNx, TiSiN, TiCN, TaAlC, TiAIN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuOx ) , 其厚度可以为 lnm-20nm, 如 3nm、 5nm、 8nm、 10nm、 12nm或 15nm, 再在所述功函数金属层上形成重掺杂多晶硅、 Ti、 Co、 Ni、 Al、 W或其合金等而形成栅极 21 1。
[0026】在本发明的另外一些实施例中， 也可采用后栅工艺 （gate last ) , 此时， 栅堆叠包括栅极 211 (此时为伪栅） 和承载所述栅极的栅介质层 210。 在所述栅介质层 210上通过沉积例如多晶硅、 多晶 SiGe、 非晶硅， 掺杂或未掺杂的氧化硅及氮化硅、 氮氧化硅、 碳化硅， 甚至金属形成栅 极 211 (此时为伪栅） ， 其厚度可以为 10nm -80nm。 可选地， 还包括在 所述栅极 211 (此时为伪栅）上形成覆盖层， 例如通过沉积氮化硅、 氧化 硅、 氮氧化硅、 碳化硅及其组合形成， 用以保护伪栅极 211的顶部区域， 防止栅极 211 (此时为伪栅）的顶部区域在后续形成接触层的工艺中与沉 积的金属层发生反应。 在另一个采用后栅工艺实施例中， 栅堆叠也可以 没有栅介质层 210, 而是后续工艺步骤中， 除去所述伪栅后， 在填充功函 数金属层之前形成栅介质层 210。
[0027】可选地， 如图 4所示， 形成所述栅堆叠之后， 还包括以所述栅堆叠 为掩模， 向表面有源层 203中注入 P型或 N型掺杂物或杂质， 进而在所 述栅堆叠两侧形成源 /漏延伸区 220。 对于 PMOS来说， 源 /漏延伸区 220 可以是 P型掺杂的 Si; 对于 NMOS来说， 源 /漏延伸区 220可以是 N型 掺杂的 Si。 然后对所述半导体结构进行退火， 以激活源 /漏延伸区 220中 的杂质， 退火可以采用包括快速退火、 尖峰退火等其他合适的方法形成。
[0028】之后， 可以形成附着于所述栅堆叠侧壁的侧墙。 如图 5所示， 所述 侧墙 230形成于所述栅堆叠的侧壁上， 用于将栅堆叠隔开。 侧墙 230可 以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的材 料形成。 侧墙 230可以具有多层结构。 侧墙 230可以通过包括沉积 -刻蚀 工艺形成， 其厚度范围可以是 10nm ~100nm, 如 30nm、 50nm或 80nm。
[0029】参考图 2和图 6, 在步骤 S 103 中， 去除所述栅堆叠两侧的表面有 源层 203以及部分绝缘埋层 202 , 形成开口 240。 在本实施例中， 先刻蚀 表面有源层 203 , 再刻蚀绝缘埋层 202 , 并停止在绝缘埋层 202中。 以所 述栅堆叠为掩模， 采用等离子刻蚀等干法刻蚀， 各向异性地刻蚀表面有 源层 203和绝缘埋层 202。 干法刻蚀工艺气体包括六氟化硫 (SF6)、 溴化氢 (HBr)、 碘化氢 (ΗΙ)、 氯、 氩、 氦、 曱烷 （及氯代曱烷） 、 乙炔、 乙烯等 碳的氢化物及其组合， 和 /或其他合适的材料。
[0030】参考图 2和图 7, 在步骤 S 104中， 在所述开口 240中填充半导体 材料。 所述半导体材料可以为掺杂的多晶硅或单晶硅。 在本实施例中， 通过沉积非晶硅并退火的方法形成多晶硅或单晶硅。 可以通过离子注入 和退火的方式进行掺杂，掺杂浓度为可以为 1019 ~ 1021cm-3。对于 NMOS , 所述半导体材料可以为 N型掺杂； 对于 PMOS ,所述半导体材料可以为 P 型掺杂。 退火可以采用包括快速退火、 尖峰退火等其他合适的方法实施。 填充所述半导体材料后， 可以对所述半导体材料进行化学机械抛光 (CMP) , 使所述半导体材料的上表面与栅堆叠结构的上表面齐平（本文件 内， 术语"齐平"意指两者之间的高度差在工艺误差允许的范围内）。
[0031】如图 8所示， 去除部分所述半导体材料，使所述半导体材料的上表 面与栅堆叠的下表面齐平， 形成源 /漏区 250。 可以使用湿法刻蚀和 /或干 法刻蚀的方式去除所述半导体材料。 湿法刻蚀工艺包括四曱基氢氧化铵 (TMAH)、 氢氧化钾 (KOH)或者其他合适刻蚀的溶液； 干法刻蚀工艺包括 六氟化硫 (SF6)、 溴化氢 (HBr)、 碘化氢 (HI)、 氯、 氩、 氦、 曱烷 （及氯代 曱烷） 、 乙炔、 乙烯等碳的氢化物及其组合， 和 /或其他合适的材料。 可 以通过控制刻蚀时间的长短， 来控制刻蚀停止， 使所述半导体材料的上 表面与栅堆叠的下表面齐平。
[0032】本发明还提供了一种半导体结构， 如图 8所示， 包括 SOI衬底、 栅堆叠、 和源 /漏区 250 , 其中： 所述 SOI衬底从下至上依次包括基底层 201、 绝缘埋层 202和表面有源层 203 ; 所述栅堆叠位于所述表面有源层 203之上； 所述源 /漏区 250位于所述栅堆叠的两侧， 并延伸至绝缘埋层 202中。 所述半导体结构还可以包括侧墙， 所述侧墙位于所述栅堆叠的侧 壁上。 所述源 /漏区 250的材料可以为掺杂的多晶硅或单晶硅， 掺杂浓度 为可以为 1019 ~ 1021cm-3。 对于 NMOS , 所述源 /漏区 250的掺杂类型为 N 型； 对于 PMOS , 所述源 /漏区 250的掺杂类型为 P型。 所述源 /漏区 250 的下表面低于绝缘埋层 202的上表面， 其相差范围可以为 100nm-200nm。 通过将源 /漏区延伸至衬底绝缘埋层中， 在降低源漏串联电阻的同时， 不 会造成栅极和源漏之间的寄生电容增大。
[0033]虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本 发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施 例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员 应当容易理解在保持本发明保护范围内的同时， 工艺步骤的次序可以变 化。
[0034】此外，本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或者以后即 将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它 们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的 结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要求旨 在将这些工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含在其保 护范围内。

Claims

权 利 要 求
1. 一种半导体结构的制造方法， 该方法包括以下步骤：
a) 提供 SOI衬底 (200), 所述衬底从下至上依次包括基底层 (201)、 绝 缘埋层 (202)和表面有源层 (203);
b) 在所述衬底上形成栅堆叠；
c) 去除所述栅堆叠两侧的表面有源层 (203)以及部分绝缘埋层 (202), 形成开口（240);
d) 在所述开口（240)中填充半导体材料， 形成源 /漏区（250)。
2. 根据权利要求 1 所述的方法， 其中， 在所述步骤 b ) 中， 还包括 形成附着于所述栅堆叠侧壁的侧墙 ( 230 )。
3. 根据权利要求 1 所述的方法， 其中， 在所述步骤 c ) 中， 先刻蚀 表面有源层 (203), 再刻蚀绝缘埋层 (202), 并停止在绝缘埋层 (202)中。
4. 根据权利要求 1 所述的方法， 其中， 在所述步骤 d ) 中， 所述半 导体材料为掺杂的多晶硅或单晶硅， 掺杂浓度为为 1019 ~ 1021cm—3。
5. 根据权利要求 1所述的方法， 其中， 对于 NMOS , 所述半导体材 料为 N型掺杂； 对于 PMOS , 所述半导体材料为 P型掺杂。
6. 根据权利要求 4所述的方法， 其中， 通过沉积非晶硅并退火形成 多晶硅或单晶硅。
7. 根据权利要求 6所述的方法， 其中， 还包括在退火之后去除部分 所述半导体材料， 使所述半导体材料的上表面与栅堆叠的下表面齐平。
8. 根据权利要求 7所述的方法， 其中， 通过化学机械抛光加刻蚀的 方法去除部分所述半导体材料， 并通过控制刻蚀时间的长短， 来控制刻 蚀停止。
9. 一种半导体结构， 包括 SOI衬底 (200)、 栅堆叠和源 /漏区（250), 其中：
所述 SOI衬底从下至上依次包括基底层 (201)、 绝缘埋层 (202)和表面 有源层 (203); 所述栅堆叠位于所述表面有源层 (203)之上；
所述源 /漏区（250)位于所述栅堆叠的两侧， 并延伸至绝缘埋层 (202) 中。
10. 根据权利要求 9 所述的半导体结构， 还包括侧墙 (230), 所述侧 墙 (230)位于所述栅堆叠的侧壁上。
11. 根据权利要求 9所述的半导体结构， 其中， 源 /漏区（250)的下表 面低于绝缘埋层 (202)的上表面， 其相差范围为 100nm-200nm。
12. 根据权利要求 9所述的半导体结构， 其中， 源 /漏区（250)的材料 为掺杂的多晶硅或单晶硅， 掺杂浓度为为 1019 ~ 1021cm—3。
13. 根据权利要求 9所述的半导体结构， 其中， 对于 NMOS , 所述源 /漏区（250)的掺杂类型为 N型； 对于 PMOS , 所述源 /漏区（250)的掺杂类 型为 P型。
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