WO2011127634A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2011127634A1
WO2011127634A1 PCT/CN2010/001482 CN2010001482W WO2011127634A1 WO 2011127634 A1 WO2011127634 A1 WO 2011127634A1 CN 2010001482 W CN2010001482 W CN 2010001482W WO 2011127634 A1 WO2011127634 A1 WO 2011127634A1
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layer
semiconductor
semiconductor layer
gate
semiconductor device
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PCT/CN2010/001482
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English (en)
French (fr)
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朱慧珑
梁擎擎
骆志炯
尹海洲
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中国科学院微电子研究所
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Priority to US13/060,468 priority Critical patent/US9018739B2/en
Publication of WO2011127634A1 publication Critical patent/WO2011127634A1/zh

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    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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Definitions

  • the present application relates generally to semiconductor devices and methods of fabricating the same, and more particularly to MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structures including trenches of high mobility materials and methods of making the same.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • a trend in integrated circuits is to integrate as many MOSFETs as possible on a single chip area.
  • the gate length is reduced to less than 32 nm.
  • the small gate length impairs the gate's ability to control the channel, resulting in a short channel effect that degrades the performance of the MOSFET, particularly the threshold voltage.
  • the poor conductivity of polysilicon causes the voltage applied to the gate to create a partial voltage drop in the polysilicon gate, further reducing the actual gate voltage applied to the channel region.
  • a metal gate instead of a polysilicon gate, which can reduce the adverse effects of polysilicon depletion by virtue of the good electrical conductivity of the metal.
  • a replacement gate process is generally employed, in which a dummy gate conductor, for example made of polysilicon, is first formed, and then the dummy gate conductor is removed by selective etching to form a gate. Opening, finally depositing the desired gate metal in the gate opening.
  • Metal gate MOS devices formed using a replacement gate process can improve gate-to-channel control.
  • An object of the present invention is to provide a MOSFET with high output current, high operating speed and low power consumption and a method of fabricating the same.
  • a semiconductor device comprising: a semiconductor substrate; a first semiconductor layer formed on the semiconductor substrate; and a second semiconductor layer formed around the first semiconductor layer; the first semiconductor a high-k gate dielectric layer and a gate conductor formed on the layer; a source/drain region formed on the second semiconductor layer; wherein sidewalls of the first semiconductor layer and the second semiconductor layer are in inclined contact.
  • a method of fabricating a semiconductor device comprising: a) forming a second semiconductor layer on the semiconductor substrate;
  • the oblique contact facilitates epitaxial growth of the first semiconductor layer on the sidewall of the second semiconductor layer, forming a first semiconductor layer of good quality, improving the performance of the device channel; using a high mobility material
  • the first semiconductor layer forms a channel region, which can increase the output current and the operating frequency while reducing power consumption.
  • the most appropriate semiconductor material can be selected for the source/drain and channel regions, respectively, to optimize source/drain and channel region performance.
  • the first semiconductor layer is an epitaxially grown layer, the upper surface and the lower surface of which match the ⁇ 100 ⁇ crystal plane of Si, and the side in contact with the second semiconductor layer matches the ⁇ 111 ⁇ crystal of Si surface.
  • the interface between the first semiconductor layer and the second semiconductor layer i.e., the side in contact with each other) substantially maintains crystallographic integrity and continuity, thereby reducing the number of defects introduced by the interface. Epitaxial growth in this direction facilitates the achievement of a flat surface, ensuring uniformity of channel thickness.
  • a doping step for forming source/drain regions is performed before forming a channel region, which can prevent dopants of source/drain regions from diffusing into the channel region and reducing channel Defects in the zone, which effectively improve the performance of the device.
  • FIG. 1 to 15 schematically show cross-sectional views of various stages of a method of fabricating a semiconductor device in accordance with the present invention. detailed description
  • the semiconductor substrate as the initial structure includes, for example, a group IV semiconductor such as Si or Ge, a III-V semiconductor such as GaAs, InP, GaN, SiC.
  • the gate conductor can be a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer.
  • the material of the metal layer is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu , RuOx and a combination of the various metallic materials described.
  • the gate dielectric may be composed of SiO 2 or a material having a dielectric constant greater than SiO 2 , and includes, for example, an oxide, a nitride, an oxynitride, a silicate, an aluminate, a titanate, wherein the oxide includes, for example, Si0 2 . , Hf0 2. Zr0 2, ⁇ 1 ⁇ > Ti0 2, La 2 0 3, e.g. nitrides include Si, including silicates such as HfSiOx, e.g. aluminates including LaA10 3, titanates include, for example SrTi0 3, oxynitride, e.g. Includes SiON. Also, the gate dielectric can be formed not only by materials known to those skilled in the art, but also materials developed for the gate dielectric in the future.
  • the following steps of fabricating a MOSFET are performed in the order of Figures 1 through 15.
  • the process for fabricating a MOSFET of the present invention begins with a semiconductor substrate 10 comprising shallow trench isolation regions (STI regions) 11.
  • the semiconductor substrate 10 is preferably a single crystal silicon substrate.
  • the STI region 11 preferably includes an oxide for electrically isolating the active region on the semiconductor substrate 10.
  • the surface of the semiconductor substrate 10 is exposed between the STI regions 11.
  • a thickness of about 10-20 nm is selectively epitaxially grown on the exposed surface of the semiconductor substrate 10 by a conventional deposition process such as PVD, CVD, atomic layer deposition, sputtering, or the like, and the Ge content is about 5_15% of the SiGe layer 12 and the Si layer 13 having a thickness of about 3 to 10 nm.
  • the SiGe layer 12 and the Si layer 13 are not formed in the STI region 11.
  • a portion of the Si layer 13 is converted into Si0 2 by, for example, a thermal oxidation process to form the dummy gate dielectric layer 14.
  • a polysilicon layer 15 having a thickness of about 30 to 60 nm, an oxide layer 16 having a thickness of about 10 to 20 nm, and a nitride layer having a thickness of about 20 to 50 nm are sequentially formed on the entire surface of the semiconductor structure by the above-described conventional deposition process. 17.
  • the oxide layer 16 and the nitride layer 17 serve as a barrier layer in the etching step and a protective layer in chemical mechanical planarization (CMP), respectively.
  • CMP chemical mechanical planarization
  • a photoresist layer 18 is formed on the surface of the nitride layer 17, and then a patterned photoresist layer 18 is formed as a mask by a photolithography process including exposure and development.
  • the unobstructed portions of the nitride layer 17, the oxide layer 16, and the polysilicon layer 15 are removed from top to bottom by dry etching such as ion milling etching, plasma etching, reactive ion etching (RIE), and laser ablation.
  • RIE reactive ion etching
  • the photoresist mask is removed by dissolving or ashing in a solvent.
  • a lightly doped source/drain region (including an extension region if necessary) and a sidewall spacer are formed in the epitaxial Si layer 13.
  • Impurity is implanted into the epitaxial Si layer 13 by using a stack of the nitride layer 17, the oxide layer 16, and the dummy gate conductor 15 as a hard mask.
  • the dopant used may be As or P; for p-type MOSFETs, the dopant used may be B or BF 2 .
  • a nitride layer is formed on the entire surface of the semiconductor structure by the above-described conventional deposition process.
  • a portion of the nitride layer is removed by dry etching as described above using a photoresist mask (not shown) such that it is located on the side of the stack of nitride layer 17, oxide layer 16, and dummy gate conductor 15.
  • the nitride layer remains, thereby forming the sidewall 19 of the gate.
  • the formed semiconductor structure is annealed, for example, a spike anneal at a temperature of about 1000-1080 ⁇ to activate the dopant implanted by the previous implantation step and to eliminate the damage caused by the implantation.
  • the line indicated by reference numeral 20 in Fig. 4 indicates the outline of the source/drain region.
  • the etching is stopped at a position of a proper depth below the upper surface of the semiconductor substrate 10, for example, by controlling the etching time.
  • a SiGe layer having a Ge content of about 20 - 70% is epitaxially grown on the exposed surface of the semiconductor substrate 10 as a contact region 21 which is connected to the source/drain regions on the side.
  • the contact region 21 may have a thickness such that its upper surface is higher than the upper surface of the epitaxial Si layer 13, and its lower surface is lower than the lower surface of the epitaxial Si layer 13.
  • a conformal nitride layer 22 having a thickness of about 10 to 20 nm and a capping oxide layer 23 having a thickness of about 100 to 150 nm are formed on the entire surface of the semiconductor structure by the above-described conventional deposition process.
  • CMP is performed on the semiconductor structure, thereby obtaining a flat semiconductor structure.
  • the CMP removes a portion of the oxide layer 23 such that a portion of the nitride layer 22 above the nitride layer 17, the oxide layer 16 and the dummy gate conductor 15 is exposed, and the remainder is located below the oxide layer 23.
  • the oxide layer 23 is etched back to further selectively remove a portion of the oxide with respect to the nitride.
  • the exposed portion of the nitride layer 22 forms a cap.
  • the cap of the nitride is selectively removed relative to the oxide by conventional wet etching in which an etchant solution is used, wherein the oxide layer 23 provides the mask required for the etching step.
  • This etching step removes the exposed portions of the sidewall spacer 19 and the nitride layer 22 of the gate, and then completely removes the nitride layer 17 at the top of the laminate.
  • the oxide layer 16 and the polysilicon layer 15 serving as a dummy gate conductor are completely removed by the above-described dry etching process, and the exposed portion of the dummy gate dielectric layer 14 is also removed, forming the side of the gate.
  • Si is selectively removed with respect to SiGe by conventional wet etching in which an etchant solution is used.
  • the etching step is anisotropic, so that only the portion of the epitaxial Si layer 13 exposed through the gate opening 24 is removed, and the upper surface of the epitaxial SiGe layer 12 is exposed at the bottom of the gate opening 24.
  • An anisotropic etchant for Si which is well known in the art can be used in the present invention, and includes, for example, K0H (potassium hydroxide), TMAH (tetramethylammonium hydroxide), EDP (ethylenediamine-o-phenylene). Phenol), N2H4 ⁇ H20 (hydrated hydrazine), etc.
  • the etching speed on the ⁇ 111 ⁇ crystal plane of Si is at least one order of magnitude smaller than that of the other crystal faces, and thus the facet of the epitaxial Si layer 13 exposed on the side in the gate opening 24 is formed. It is the ⁇ 111 ⁇ crystal plane of Si. The facet is inclined relative to the surface of the substrate.
  • the semiconductor substrate 10 and the epitaxial Si layer 13 are composed of different semiconductor materials, and the semiconductor substrate 10 can serve as a barrier layer for the etching step, the epitaxial Si layer 13 can be omitted in the semiconductor device of the present invention.
  • an implantation step for channel doping is performed.
  • the dopant used may be As or P, the implantation energy is about 1-20 keV, and the dopant concentration is about 2 X 10' 8 - l X 10 2 7 cm 3 ;
  • the dopant may be B or BF 2 , the implantation energy is about 0.2-20 keV, and the concentration of the dopant is about 2 X 10' 8 - IX 10 2 °/cm 3 .
  • the implanting step forms a square-shaped ultra-steep back-off island (SSRI) 25 below the gate opening 24.
  • SSRI square-shaped ultra-steep back-off island
  • the steep doping profile of SSRI is advantageous for reducing short channel effects. of.
  • the SSRI 25 is located below the bottom of the gate opening 24 (i.e., the distance from the bottom of the gate dielectric layer to be formed) by about 5 to 20 nm.
  • the doped channel region may be laser annealed to activate the dopant therein.
  • U.S. Patent No. 6,214,654 issued to U.S. Patent No. 6,214, the entire disclosure of which is incorporated herein by reference in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire disclosure in.
  • a channel material layer 26 is epitaxially grown on the epitaxial SiGe layer by a conventional deposition process as described above, and has a thickness of about 2-7 nm. Then, in order to form a high quality gate dielectric layer in the subsequent step, a Si layer 27 having a thickness of about 2 to 5 nm is further epitaxially grown on the channel material layer 26.
  • the channel material layer 26 replaces a portion of the epitaxial Si layer 13 and is composed of a semiconductor material having a carrier mobility higher than that of the latter.
  • the Si content of the high Ge content has a Ge content of about 2 (TlOO%).
  • the channel material layer may also be selected from Group III-V semiconductor materials such as InP, InSb, InGaAs, and InAs.
  • the crystal structure of the channel material layer 26 is matched in the vertical direction to the epitaxial SiGe layer 12 formed in the step shown in FIG. 2 located below it, and in the lateral direction and at the side thereof as shown in FIG.
  • the facet of the epitaxial Si layer 13 exposed in the step is matched.
  • epitaxial growth of the channel material layer 26 in the vertical direction occurs on the ⁇ 110 ⁇ crystal plane of Si, and epitaxial growth in the horizontal direction occurs on the ⁇ 111 ⁇ crystal plane of Si.
  • the interface between the channel material layer 26 and the epitaxial Si layer 13 substantially maintains crystallographic integrity and continuity, thereby reducing the number of defects of pinning. Moreover, epitaxial growth in both directions facilitates obtaining a flat surface, ensuring uniformity of channel thickness.
  • a portion of the Si layer 27 is converted into SiO 2 by a thermal oxidation process to form a SiO 2 layer (not shown) having a thickness of about 0.5-lnm.
  • a conformal high-k dielectric layer (e.g., Hf0 2 ) having a thickness of about 2-5 nm is formed over the entire surface of the semiconductor structure by the conventional deposition process described above as the gate dielectric layer 28 of the final MOSFET.
  • a gate conductor 29 (e.g., metal such as ⁇ , TiN, etc.) is filled in the gate opening 24 by the above-described conventional deposition process.
  • This step can include first depositing a capping metal layer and then patterning the metal layer to retain material in the gate opening 24.
  • the etch back may be performed after depositing the capping metal layer first, by controlling the etching time such that the material outside the gate opening 24 is completely removed, and only a small portion of the material located inside the gate port 24 is removed or not Was removed.
  • a nitride layer 30 is formed on the entire surface of the semiconductor structure by the above-described conventional deposition process, and a flat surface is obtained after CMP treatment.
  • the nitride layer 30 serves as an interlayer isolation layer (ILD) such that an interconnection can be formed over the nitride layer 30 in a subsequent step.
  • ILD interlayer isolation layer
  • the nitride layer 30, the oxide layer 23 and the nitride layer 22 over the contact region 21 are removed from the top to the bottom by a dry etching using a photoresist mask (not shown). In part, a contact hole 31 is formed to the contact region 21.
  • a silicide region 32 is formed in the upper surface of the contact region 21 exposed at the bottom of the contact hole 31 to reduce the contact resistance between the via conductor to be formed and the contact region 21.
  • the step includes first depositing a conformal Ni layer on the entire surface of the semiconductor structure, and then annealing at a temperature of about 300-500 ° C to cause Ni to react with Si in the contact region 21 to form a silicide, and finally, for example, utilize Wet etching selectively removes excess Ni that is not involved in the reaction relative to the silicide.
  • a metal contact 33 is formed in the contact hole 31.
  • This step includes first depositing a conformal barrier layer (e.g., TiN, not shown) over the entire surface of the semiconductor structure (including the sidewalls and bottom of the contact hole 31) by the conventional deposition method described above, and then further depositing a metal layer (for example, W) is to fill the contact hole 31, and finally the material of the barrier layer and the metal layer outside the contact hole 31 is removed by CMP treatment.
  • a conformal barrier layer e.g., TiN, not shown
  • a metal layer For example, W

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Description

半导体器件及其制造方法 技术领域
本申请一般地涉及半导体器件及其制造方法， 更具体地， 涉及包含高迁移率材料 的沟道的 M0SFET (金属氧化物半导体场效应晶体管） 结构及其制作方法。 背景技术
集成电路的一个发展趋势是在单位芯片面积上集成尽可能多的 M0SFET。 随着 M0SFET的按比例缩小， 栅极长度减小到小于 32nm。 然而， 小的栅极长度削弱了栅极 对沟道的控制能力， 导致了使得 M0SFET性能恶化、 特别是阈值电压减小的短沟道效 应。 此外， 多晶硅的不良导电性使得施加在栅极上的电压在多晶硅栅极中产生一部分 电压降， 进一步使得作用在沟道区上的实际栅极电压减小。
利用双栅器件和超薄 S0I器件可以增强栅极对沟道的控制能力，从而有效地抑制 短沟道效应。
另一趋势是采用金属栅极代替多晶硅栅极，利用金属的良好导电性可以减小多晶 硅耗尽的不利影响。 在器件的制造过程中， 为了准确地控制栅极的长度， 通常采用替 代栅极工艺， 其中首先形成例如由多晶硅构成的假栅极导体， 然后通过选择性蚀刻去 除假栅极导体以形成栅极开口， 最后在栅极幵口中沉积所需的栅极金属。采用替代栅 极工艺形成的金属栅 M0S器件可以改善栅极对沟道的控制能力。
然而， 诸如双栅器件、 超薄体 S0I器件、 金属栅 M0S器件等的上述新型器件仍然 采用传统的沟道材料， 结果在器件的最大输出电流、 功耗和工作频率等方面并没有得 到改善。 发明内容
本发明的目的是提供一种高输出电流、 高工作速度和低功耗的 M0SFET及其制造 方法。 根据本发明， 提供一种半导体器件， 包括： 半导体衬底； 形成于所述半导体衬 底上的第一半导体层， 以及环绕所述第一半导体层形成的第二半导体层； 所述第一半 导体层上形成的高 k栅介质层和栅极导体； 所述第二半导体层上形成的源 /漏区； 其 中， 所述第一半导体层和第二半导体层的侧壁为倾斜接触。
根据本发明的另一方面， 提供一种制造半导体器件的方法， 包括： a)在半导体衬底上形成第二半导体层；
b)在所述第二半导体层上形成假栅极， 以及所述假栅极两侧的源 /漏区； c)去除所述假栅极， 以形成栅极开口；
d)通过湿法蚀刻选择性去除所述第二半导体层在所述栅极开口中的部分； e)通过所述栅极开口， 在半导体衬底上外延生长第一半导体层
f)在所述栅极幵口中形成栅介质层以及栅极导体。
在本发明的半导体器件中，倾斜接触有利于第一半导体层在第二半导体层侧壁上 的外延生长， 形成质量良好的第一半导体层， 改善器件沟道的性能； 使用高迁移率材 料的第一半导体层形成沟道区， 可以提高输出电流和工作频率， 同时降低功耗。 可以 分别针对源 /漏区和沟道区的需求选择最适当的半导体材料，分别优化源 /漏区和沟道 区的性能。
在优选的实施例中， 第一半导体层是外延生长的层， 其上表面和下表面匹配 Si 的 { 100}晶面， 其与所述第二半导体层接触的侧面匹配 Si 的 { 111}晶面。 第一半导体 层与第二半导体层之间的界面（即相接触的侧面）基本上保持了晶体学上的完整性和 连续性， 从而减少了由于界面引入的缺陷数量。 在这个方向上进行的外延生长有利于 获得平整的表面， 保证了沟道厚度的均匀性。
在本发明的方法中， 优选地， 在形成沟道区之前执行用于形成源 /漏区的掺杂步 骤， 这可以避免源 /漏区的掺杂剂向沟道区扩散， 并减少沟道区中的缺陷， 从而有效 地改善了器件的性能。 附图说明
图 1至 15示意性地示出了制造根据本发明的半导体器件的方法的各个阶段的截 面图。 具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中， 相同的元件采用类似的附 图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。
应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另一层、 另一个 区域 "上面"或 "上方" 时， 可以指直接位于另一层、 另一个区域上面， 或者在其与 另一层、 另一个区域之间还包含其它的层或区域。 并且， 如果将器件翻转， 该一层、 一个区域将位于另一层、 另一个区域 "下面"或 "下方" 。
如果为了描述直接位于另一层、 另一个区域上面的情形， 本文将采用 "直接 在……上面"或 "在……上面并与之邻接" 的表述方式。
在下文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处理 工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员能够理解的那样， 可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知 的材料构成。 作为初始结构的半导体衬底例如包括 IV族半导体， 如 Si或 Ge, III-V 族半导体， 如 GaAs、 InP、 GaN、 SiC。 栅极导体可以是金属层、 掺杂多晶硅层、 或包 括金属层和掺杂多晶硅层的叠层栅极导体。金属层的材料为 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax, MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx和所述各种金属材料的组合。 栅 极电介质可以由 Si02或介电常数大于 Si02的材料构成， 例如包括氧化物、氮化物、氧 氮化物、 硅酸盐、 铝酸盐、 钛酸盐， 其中， 氧化物例如包括 Si02、 Hf02. Zr02、 Α1Λ> Ti02、 La203，氮化物例如包括 Si ，硅酸盐例如包括 HfSiOx,铝酸盐例如包括 LaA103， 钛酸盐例如包括 SrTi03， 氧氮化物例如包括 SiON。并且， 栅极电介质不仅可以由本领 域的技术人员已知的材料形成， 也可以采用将来开发的用于栅极电介质的材料。
根据本发明的优选实施例， 按照图 1至 15的顺序执行制造 M0SFET的以下步骤。 参见图 1， 本发明的制造 M0SFET的工艺开始于包含浅沟隔离区（STI区） 11的半 导体衬底 10。 该半导体衬底 10优选为单晶硅衬底。 STI区 11优选地包含氧化物， 用 于电隔离半导体衬底 10上的有源区。 在 STI区 11之间露出半导体衬底 10的表面。
参见图 2， 通过常规的沉积工艺， 如 PVD、 CVD、 原子层沉积、 溅射等， 在半导体 衬底 10的露出表面上按顺序选择性地外延生长厚度约为 10- 20nm、Ge含量约为 5_15% 的 SiGe层 12以及厚度约为 3- 10nm的 Si层 13。
由于外延生长的选择性， 在 STI区 11没有形成 SiGe层 12和 Si层 13。
然后，例如通过热氧化工艺将 Si层 13的一部分转变为 Si02，形成假栅介质层 14。 通过上述常规的沉积工艺， 在半导体结构的整个表面上依次形成厚度约为 30-60nm的多晶硅层 15、 厚度约为 10- 20nm的氧化物层 16、 以及厚度约为 20- 50nm 的氮化物层 17。在随后的步骤中，氧化物层 16和氮化物层 17分别用作蚀刻步骤中的 阻挡层和化学机械平面化 （CMP) 中的保护层。 参见图 3, 对多晶硅层 15进行图案化以形成假栅极导体。
首先， 在氮化物层 17的表面上形成光致抗蚀剂层 18， 然后通过包含曝光和显影 的光刻工艺， 形成含有图案的光致抗蚀剂层 18作为掩模。 通过干法蚀刻， 如离子铣 蚀刻、 等离子蚀刻、 反应离子蚀刻（RIE)、 激光烧蚀， 从上至下去除氮化物层 17、 氧 化物层 16和多晶硅层 15的未被遮挡的部分。 该蚀刻停止在假栅介质层 14的顶部。 最后， 通过在溶剂中溶解或灰化去除光抗蚀剂掩模。
参见图 4，在外延的 Si层 13中形成轻掺杂的源 /漏区（如果需要，还包括延伸区） 以及栅极的侧墙。
利用氮化物层 17、 氧化物层 16和假栅极导体 15的叠层作为硬掩模， 在外延的 Si层 13中注入杂质。对于 n型 M0SFET,采用的掺杂剂可以是 As或 P;对于 p型 M0SFET, 采用的掺杂剂可以是 B或 BF2。
然后， 通过上述常规的沉积工艺， 在半导体结构的整个表面上形成氮化物层。 利 用光致抗蚀剂掩模 （未示出）， 通过上述干法蚀刻， 去除氮化物层的一部分， 使得位 于氮化物层 17、氧化物层 16和假栅极导体 15的叠层的侧面的氮化物层保留，从而形 成栅极的侧墙 19。
如果需要， 对所形成的半导体结构进行退火处理， 例如在约 1000-1080Ό的温度 下的尖峰退火 （spike anneal ), 以激活通过先前的注入步骤而注入的掺杂剂并消除 注入导致的损伤。 图 4中的附图标记 20指示的线表示源 /漏区的轮廓。
参见图 5， 利用氮化物层 17、 氧化物层 16和假栅极导体 15的叠层、 位于该叠层 的侧面的侧墙 19、 以及 STI区 11作为硬掩模， 通过上述干法蚀刻， 从上至下地去除 假栅介质层 14、 外延 Si层 13、 外延 SiGe层 12和半导体衬底 10的暴露的部分。 例 如通过控制蚀刻的时间， 使得该蚀刻停止在半导体衬底 10的上表面下方的适当深度 的位置。
通过上述常规的沉积工艺，在半导体衬底 10的露出表面上外延生长 Ge含量约为 20 - 70%的 SiGe层， 作为与源 /漏区在侧面上相连接的接触区 21。
优选地， 接触区 21的厚度可以使其上表面高于外延 Si层 13的上表面， 其下表 面低于外延 Si层 13的下表面。
参见图 6， 通过上述常规的沉积工艺， 在半导体结构的整个表面上形成厚度约为 10-20nm的共形氮化物层 22、 以及厚度约为 100- 150nm的覆盖氧化物层 23。
以氮化物层 22作为保护层，对半导体结构进行 CMP，从而获得了半导体结构的平 整表面。 CMP去除了氧化物层 23的一部分， 使得氮化物层 22位于氮化物层 17、 氧化 物层 16和假栅极导体 15的叠层上方的一部分露出， 其余部分则位于氧化物层 23的 下方。
然后， 对氧化物层 23进行回蚀刻， 相对于氮化物进一步地选择性地去除一部分 氧化物。 氮化物层 22的暴露部分形成帽盖。
参见图 7， 通过其中使用蚀刻剂溶液的常规湿法蚀刻， 相对于氧化物选择性地去 除氮化物的帽盖， 其中氧化物层 23提供了该蚀刻步骤所需的掩模。 该蚀刻步骤去除 了栅极的侧墙 19和氮化物层 22的暴露部分，并且接着完全去除了叠层顶部的氮化物 层 17。
参见图 8，进一步地，通过上述干法蚀刻工艺完全去除氧化物层 16和用作假栅极 导体的多晶硅层 15， 并且， 还去除了假栅介质层 14的暴露部分， 形成由栅极的侧墙 19包围的栅极幵口 24。
然后，通过其中使用蚀刻剂溶液的常规湿法蚀刻，相对于 SiGe选择性地去除 Si。 该蚀刻步骤是各向异性的， 从而仅仅去除外延 Si层 13的通过栅极幵口 24露出的部 分， 并在栅极幵口 24的底部露出外延 SiGe层 12的上表面。
可以将本领域所熟知的用于 Si 的各向异性蚀刻剂用在本发明中， 例如包括 K0H (氢氧化钾）、 TMAH (四甲基氢氧化铵）、 EDP (乙二胺-邻苯二酚）、 N2H4 · H20 (水合 肼)等。
由于各向异性蚀刻剂的作用，在 Si的 {111}晶面上的蚀刻速度比其他晶面小至少 一个数量级， 因此外延 Si层 13在栅极开口 24中的侧面露出的刻面 （facet ) 是 Si 的 { 111}晶面。 该刻面相对于衬底表面是倾斜的。
代替地， 如果半导体衬底 10与外延 Si层 13由不同的半导体材料构成， 并且半 导体衬底 10可以作为该蚀刻步骤的阻挡层， 则在本发明的半导体器件中可以省去外 延 Si层 13。
参见图 9， 穿过栅极幵口 24, 进行用于沟道掺杂的注入步骤。
对于 n型 M0SFET, 采用的掺杂剂可以是 As或 P, 注入能量约为 l-20keV， 掺杂剂 的浓度约为 2 X 10'8- l X 1027cm3; 对于 p型 M0SFET, 采用的掺杂剂可以是 B或 BF2， 注 入能量约为 0. 2- 20keV, 掺杂剂的浓度约为 2 X 10'8- I X 102°/cm3。
优选地， 该注入步骤在栅极开口 24的下方形成方块形状的超陡后退岛 （SSRI ) 25。正如本领域已经熟知的那样， SSRI的陡峭的掺杂分布对于减小短沟道效应是有利 的。 SSRI25位于栅极开口 24的底部下方 （即与将形成的栅介质层底部之间的距离） 大约 5〜20nm。
在注入步骤之后， 可以对掺杂的沟道区进行激光退火， 以激活其中的掺杂剂。 在于斌（音译） 等人的美国专利 US6， 214， 654B1公开了利用牺牲栅（对应于本 申请中的假栅）形成有关超陡后退沟道的上述步骤， 其全文内容以引用方式包含在本 文中。
参见图 10，通过上述常规的沉积工艺，在外延 SiGe层上外延生长沟道材料层 26, 其厚度约为 2-7nm。 然后， 为了在随后的步骤中形成高质量的栅介质层， 进一步在沟 道材料层 26上外延生长厚度约为 2-5nm的 Si层 27。
沟道材料层 26替代了外延 Si层 13的一部分， 由载流子迁移率高于后者的半导 体材料构成， 在本实施例中为高 Ge含量的 SiGe， 其 Ge含量约为 2(Tl00%。 此外， 沟 道材料层也可以选自 III- V族半导体材料， 如 InP、 InSb、 InGaAs和 InAs。
沟道材料层 26的晶体结构在垂直方向上与位于其下方的在图 2所示的步骤中形 成的外延 SiGe层 12匹配， 并且， 在横向方向上与位于其侧面的在图 8所示的步骤中 暴露的外延 Si层 13的刻面 ( facet ) 匹配。
在优选的实施例中， 沟道材料层 26在垂直方向上的外延生长发生在 Si的 { 110} 晶面上， 在水平方向上的外延生长发生在 Si的 { 111}晶面上。
因此， 沟道材料层 26与外延 Si层 13之间的界面基本上保持了晶体学上的完整 性和连续性， 从而减少了钉扎的缺陷数量。 并且， 在两个方向上的外延生长有利于获 得平整的表面， 保证了沟道厚度的均匀性。
例如通过热氧化工艺将 Si层 27的一部分转变为 Si02，形成厚度约为 0. 5-lnm的 Si02层 （未示出）。
通过上述常规的沉积工艺，在半导体结构的整个表面上形成共形的高 k电介质层 (例如 Hf02)， 其厚度约为 2-5nm， 作为最终的 M0SFET的栅介质层 28。
参见图 11 , 通过上述常规的沉积工艺， 在栅极开口 24中填充栅极导体 29 (如\¥、 TiN等金属）。
该步骤可包括首先沉积覆盖金属层， 然后对该金属层进行图案化， 以保留位于栅 极开口 24中的材料。 优选地， 可以在首先沉积覆盖金属层之后进行回蚀刻， 通过控 制蚀刻时间， 使得位于栅极开口 24外部的材料完全去除， 而位于栅极幵口 24内部的 材料仅有一小部分被去除或者未被去除。 参见图 12，通过上述常规的沉积工艺，在半导体结构的整个表面上形成氮化物层 30, 并经过 CMP处理后获得平整的表面。 该氮化物层 30作为层间隔离层 （ILD)， 使 得在随后的步骤中， 可以在氮化物层 30的上方形成互连。
参见图 13， 利用光致抗蚀剂掩模 （未示出）， 通过上述干法蚀刻， 从上至下去除 位于接触区 21上方的氮化物层 30、 氧化物层 23和氮化物层 22的一部分， 形成至接 触区 21的接触孔 31。
参见图 14， 在接触孔 31的底部暴露的接触区 21的上表面中形成硅化物区 32， 以减小将要形成的通道导体与接触区 21之间的接触电阻。
该步骤包括首先在半导体结构的整个表面上沉积共形的 Ni 层， 然后在大约 300- 500°C的温度下进行退火， 使得 Ni与接触区 21中的 Si反应而形成硅化物， 最后 例如利用湿法蚀刻， 相对于硅化物选择性地去除未参与反应的多余的 Ni。
参见图 15， 在接触孔 31中形成金属接触 33。
该步骤包括首先通过上述常规的沉积方法， 在半导体结构的整个表面（包括接触 孔 31的侧壁和底部） 上沉积共形的阻挡层 （例如 TiN， 未示出）， 然后进一步沉积金 属层 （例如 W) 以填充接触孔 31， 最后通过 CMP处理去除接触孔 31外部的阻挡层和 金属层的材料。 在接触孔 31内的金属层的材料形成了金属接触 33。
以上描述只是为了示例说明和描述本发明， 而非意图穷举和限制本发明。 因此， 本发明不局限于所描述的实施例。 对于本领域的技术人员明显可知的变型或更改， 均 在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种半导体器件， 包括：
半导体衬底；
形成于所述半导体衬底上的第一半导体层， 以及环绕所述第一半导体层形成的第 二半导体层；
所述第一半导体层上形成的高 k栅介质层和栅极导体；
所述第二半导体层上形成的源 /漏区；
其中， 所述第一半导体层和第二半导体层的侧壁为倾斜接触。
2、 根据权利要求 1所述的半导体器件， 其中所述第一半导体层包括选自以下的 一种或多种材料的组合： SiGe、 InP、 InSb、 InGaAs和 InAs。
3、 根据权利要求 2所述的半导体器件， 所述第一半导体层由 SiGe形成， 其中的 Ge含量为 20-100%。
4、 根据权利要求 1所述的半导体器件， 其中所述第一半导体层下方通过刻蚀阻 挡层与所述半导体衬底接触。
5、 根据权利要求 4所述的半导体器件， 其中所述刻蚀阻挡层为 SiGe层。
6、 根据权利要求 1所述的半导体器件， 其中所述栅介质层的下方形成有 P型掺 杂或 N型掺杂的超陡后退岛。
7、根据权利要求 6所述的半导体器件，其中超陡后退岛与栅介质层底部相距 5〜 20nm 。
8、 根据权利要求 1所述的半导体器件， 所述源 /漏区通过掺杂的 SiGe形成。
9、 根据权利要求 1至 8中任一项所述的半导体器件， 所述第一半导体层的载流 子迁移率大于第二半导体层。
10、 根据权利要求 1至 8中任一项所述的半导体器件， 其中所述第一半导体层的 上表面和下表面匹配 Si的 {100}晶面，与所述第二半导体层接触的侧面匹配 Si的 { 111} 晶面。
11、 一种制造半导体器件的方法， 包括：
a)在半导体衬底上形成第二半导体层；
b)在所述第二半导体层上形成假栅极， 以及所述假栅极两侧的源 /漏区； c)去除所述假栅极， 以形成栅极开口； d)通过湿法蚀刻选择性去除所述第二半导体层在所述栅极开口中的部分； e)通过所述栅极开口， 在半导体衬底上外延生长第一半导体层
f)在所述栅极开口中形成栅介质层以及栅极导体。
12、 根据权利要求 11所述的方法， 其中所述第二半导体层包括选自以下的一种 或多种材料： SiGe、 InP、 InSb、 InGaAs和 InAs。
13、 根据权利要求 12所述的方法， 其中所述第二半导体层由 SiGe形成， SiGe 中的 Ge含量为 20-100%。
14、 根据权利要求 10所述的方法， 在步骤 a之前， 所述方法进一步包括： 在所 述半导体衬底上淀积刻蚀阻挡层。
15、 根据权利要求 14所述的方法， 其中所述刻蚀阻挡层为 SiGe层。
16、根据权利要求 11所述的方法， 在步骤 d )和步骤 e )之间， 所述方法还包括： 通过栅极开口注入 N型或 P型杂质， 以在所述栅极开口下方形成掺杂的超陡后退 岛。
17、 根据权利要求 11至 16中任一项所述的方法， 其中所述第一半导体层的载流 子迁移率高于第二半导体层。 '
18、 根据权利要求 11至 16中任一项所述的方法， 其中步骤 d) 湿法刻蚀第二导 体层， 使得所述第二半导体层在所述栅极幵口内形成匹配 Si的 { 111}晶面的侧壁。
PCT/CN2010/001482 2010-04-14 2010-09-25 半导体器件及其制造方法 WO2011127634A1 (zh)

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