CN102222692A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN102222692A
CN102222692A CN2010101476017A CN201010147601A CN102222692A CN 102222692 A CN102222692 A CN 102222692A CN 2010101476017 A CN2010101476017 A CN 2010101476017A CN 201010147601 A CN201010147601 A CN 201010147601A CN 102222692 A CN102222692 A CN 102222692A
Authority
CN
China
Prior art keywords
layer
semiconductor layer
semiconductor
semiconductor device
sige
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010101476017A
Other languages
English (en)
Other versions
CN102222692B (zh
Inventor
朱慧珑
梁擎擎
骆志炯
尹海洲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN 201010147601 priority Critical patent/CN102222692B/zh
Priority to US13/060,468 priority patent/US9018739B2/en
Priority to PCT/CN2010/001482 priority patent/WO2011127634A1/zh
Publication of CN102222692A publication Critical patent/CN102222692A/zh
Application granted granted Critical
Publication of CN102222692B publication Critical patent/CN102222692B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本申请公开了一种半导体器件及其制造方法，该半导体器件包括：半导体衬底；形成于所述半导体衬底上的第一半导体层，以及环绕所述第一半导体层形成的第二半导体层；所述第一半导体层上形成的高k栅介质层和栅极导体；所述第二半导体层上形成的源/漏区；其中，所述第一半导体层和第二半导体层的侧壁为倾斜接触。该半导体器件可以利用高迁移率的沟道区提供高输出电流和高工作速度，同时降低功耗。

Description

半导体器件及其制造方法
技术领域
本申请一般地涉及半导体器件及其制造方法，更具体地，涉及包含高迁移率材料的沟道的MOSFET(金属氧化物半导体场效应晶体管)结构及其制作方法。
背景技术
集成电路的一个发展趋势是在单位芯片面积上集成尽可能多的MOSFET。随着MOSFET的按比例缩小，栅极长度减小到小于32nm。然而，小的栅极长度削弱了栅极对沟道的控制能力，导致了使得MOSFET性能恶化、特别是阈值电压减小的短沟道效应。此外，多晶硅的不良导电性使得施加在栅极上的电压在多晶硅栅极中产生一部分电压降，进一步使得作用在沟道区上的实际栅极电压减小。
利用双栅器件和超薄SOI器件可以增强栅极对沟道的控制能力，从而有效地抑制短沟道效应。
另一趋势是采用金属栅极代替多晶硅栅极，利用金属的良好导电性可以减小多晶硅耗尽的不利影响。在器件的制造过程中，为了准确地控制栅极的长度，通常采用替代栅极工艺，其中首先形成例如由多晶硅构成的假栅极导体，然后通过选择性蚀刻去除假栅极导体以形成栅极开口，最后在栅极开口中沉积所需的栅极金属。采用替代栅极工艺形成的金属栅MOS器件可以改善栅极对沟道的控制能力。
然而，诸如双栅器件、超薄体SOI器件、金属栅MOS器件等的上述新型器件仍然采用传统的沟道材料，结果在器件的最大输出电流、功耗和工作频率等方面并没有得到改善。
发明内容
本发明的目的是提供一种高输出电流、高工作速度和低功耗的MOSFET及其制造方法。根据本发明，提供一种半导体器件，包括：半导体衬底；形成于所述半导体衬底上的第一半导体层，以及环绕所述第一半导体层形成的第二半导体层；所述第一半导体层上形成的高k栅介质层和栅极导体；所述第二半导体层上形成的源/漏区；其中，所述第一半导体层和第二半导体层的侧壁为倾斜接触。
根据本发明的另一方面，提供一种制造半导体器件的方法，包括：
a)在半导体衬底上形成第二半导体层；
b)在所述第二半导体层上形成假栅极，以及所述假栅极两侧的源/漏区；
c)去除所述假栅极，以形成栅极开口；
d)通过湿法蚀刻选择性去除所述第二半导体层在所述栅极开口中的部分；
e)通过所述栅极开口，在半导体衬底上外延生长第一半导体层
f)在所述栅极开口中形成栅介质层以及栅极导体。
在本发明的半导体器件中，倾斜接触有利于第一半导体层在第二半导体层侧壁上的外延生长，形成质量良好的第一半导体层，改善器件沟道的性能；使用高迁移率材料的第一半导体层形成沟道区，可以提高输出电流和工作频率，同时降低功耗。可以分别针对源/漏区和沟道区的需求选择最适当的半导体材料，分别优化源/漏区和沟道区的性能。
在优选的实施例中，第一半导体层是外延生长的层，其上表面和下表面匹配Si的{100}晶面，其与所述第二半导体层接触的侧面匹配Si的{111}晶面。第一半导体层与第二半导体层之间的界面(即相接触的侧面)基本上保持了晶体学上的完整性和连续性，从而减少了由于界面引入的缺陷数量。在这个方向上进行的外延生长有利于获得平整的表面，保证了沟道厚度的均匀性。
在本发明的方法中，优选地，在形成沟道区之前执行用于形成源/漏区的掺杂步骤，这可以避免源/漏区的掺杂剂向沟道区扩散，并减少沟道区中的缺陷，从而有效地改善了器件的性能。
附图说明
图1至15示意性地示出了制造根据本发明的半导体器件的方法的各个阶段的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“直接在......上面”或“在......上面并与之邻接”的表述方式。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知的材料构成。作为初始结构的半导体衬底例如包括IV族半导体，如Si或Ge，III-V族半导体，如GaAs、InP、GaN、SiC。栅极导体可以是金属层、掺杂多晶硅层、或包括金属层和掺杂多晶硅层的叠层栅极导体。金属层的材料为TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax，MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx和所述各种金属材料的组合。栅极电介质可以由SiO2或介电常数大于SiO2的材料构成，例如包括氧化物、氮化物、氧氮化物、硅酸盐、铝酸盐、钛酸盐，其中，氧化物例如包括SiO2、HfO2、ZrO2、Al2O3、TiO2、La2O3，氮化物例如包括Si3N4，硅酸盐例如包括HfSiOx，铝酸盐例如包括LaAlO3，钛酸盐例如包括SrTiO3，氧氮化物例如包括SiON。并且，栅极电介质不仅可以由本领域的技术人员已知的材料形成，也可以采用将来开发的用于栅极电介质的材料。
根据本发明的优选实施例，按照图1至15的顺序执行制造MOSFET的以下步骤。
参见图1，本发明的制造MOSFET的工艺开始于包含浅沟隔离区(STI区)11的半导体衬底10。该半导体衬底10优选为单晶硅衬底。STI区11优选地包含氧化物，用于电隔离半导体衬底10上的有源区。在STI区11之间露出半导体衬底10的表面。
参见图2，通过常规的沉积工艺，如PVD、CVD、原子层沉积、溅射等，在半导体衬底10的露出表面上按顺序选择性地外延生长厚度约为10-20nm、Ge含量约为5-15％的SiGe层12以及厚度约为3-10nm的Si层13。
由于外延生长的选择性，在STI区11没有形成SiGe层12和Si层13。
然后，例如通过热氧化工艺将Si层13的一部分转变为SiO2，形成假栅介质层14。
通过上述常规的沉积工艺，在半导体结构的整个表面上依次形成厚度约为30-60nm的多晶硅层15、厚度约为10-20nm的氧化物层16、以及厚度约为20-50nm的氮化物层17。在随后的步骤中，氧化物层16和氮化物层17分别用作蚀刻步骤中的阻挡层和化学机械平面化(CMP)中的保护层。
参见图3，对多晶硅层15进行图案化以形成假栅极导体。
首先，在氮化物层17的表面上形成光致抗蚀剂层18，然后通过包含曝光和显影的光刻工艺，形成含有图案的光致抗蚀剂层18作为掩模。通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻(RIE)、激光烧蚀，从上至下去除氮化物层17、氧化物层16和多晶硅层15的未被遮挡的部分。该蚀刻停止在假栅介质层14的顶部。最后，通过在溶剂中溶解或灰化去除光抗蚀剂掩模。
参见图4，在外延的Si层13中形成轻掺杂的源/漏区(如果需要，还包括延伸区)以及栅极的侧墙。
利用氮化物层17、氧化物层16和假栅极导体15的叠层作为硬掩模，在外延的Si层13中注入杂质。对于n型MOSFET，采用的掺杂剂可以是As或P；对于p型MOSFET，采用的掺杂剂可以是B或BF2。
然后，通过上述常规的沉积工艺，在半导体结构的整个表面上形成氮化物层。利用光致抗蚀剂掩模(未示出)，通过上述干法蚀刻，去除氮化物层的一部分，使得位于氮化物层17、氧化物层16和假栅极导体15的叠层的侧面的氮化物层保留，从而形成栅极的侧墙19。
如果需要，对所形成的半导体结构进行退火处理，例如在约1000-1080℃的温度下的尖峰退火(spike anneal)，以激活通过先前的注入步骤而注入的掺杂剂并消除注入导致的损伤。图4中的附图标记20指示的线表示源/漏区的轮廓。
参见图5，利用氮化物层17、氧化物层16和假栅极导体15的叠层、位于该叠层的侧面的侧墙19、以及STI区11作为硬掩模，通过上述干法蚀刻，从上至下地去除假栅介质层14、外延Si层13、外延SiGe层12和半导体衬底10的暴露的部分。例如通过控制蚀刻的时间，使得该蚀刻停止在半导体衬底10的上表面下方的适当深度的位置。
通过上述常规的沉积工艺，在半导体衬底10的露出表面上外延生长Ge含量约为20-70％的SiGe层，作为与源/漏区在侧面上相连接的接触区21。
优选地，接触区21的厚度可以使其上表面高于外延Si层13的上表面，其下表面低于外延Si层13的下表面。
参见图6，通过上述常规的沉积工艺，在半导体结构的整个表面上形成厚度约为10-20nm的共形氮化物层22、以及厚度约为100-150nm的覆盖氧化物层23。
以氮化物层22作为保护层，对半导体结构进行CMP，从而获得了半导体结构的平整表面。CMP去除了氧化物层23的一部分，使得氮化物层22位于氮化物层17、氧化物层16和假栅极导体15的叠层上方的一部分露出，其余部分则位于氧化物层23的下方。
然后，对氧化物层23进行回蚀刻，相对于氮化物进一步地选择性地去除一部分氧化物。氮化物层22的暴露部分形成帽盖。
参见图7，通过其中使用蚀刻剂溶液的常规湿法蚀刻，相对于氧化物选择性地去除氮化物的帽盖，其中氧化物层23提供了该蚀刻步骤所需的掩模。该蚀刻步骤去除了栅极的侧墙19和氮化物层22的暴露部分，并且接着完全去除了叠层顶部的氮化物层17。
参见图8，进一步地，通过上述干法蚀刻工艺完全去除氧化物层16和用作假栅极导体的多晶硅层15，并且，还去除了假栅介质层14的暴露部分，形成由栅极的侧墙19包围的栅极开口24。
然后，通过其中使用蚀刻剂溶液的常规湿法蚀刻，相对于SiGe选择性地去除Si。该蚀刻步骤是各向异性的，从而仅仅去除外延Si层13的通过栅极开口24露出的部分，并在栅极开口24的底部露出外延SiGe层12的上表面。
可以将本领域所熟知的用于Si的各向异性蚀刻剂用在本发明中，例如包括KOH(氢氧化钾)、TMAH(四甲基氢氧化铵)、EDP(乙二胺-邻苯二酚)、N2H4·H2O(水合肼)等。
由于各向异性蚀刻剂的作用，在Si的{111}晶面上的蚀刻速度比其他晶面小至少一个数量级，因此外延Si层13在栅极开口24中的侧面露出的刻面(facet)是Si的{111}晶面。该刻面相对于衬底表面是倾斜的。
代替地，如果半导体衬底10与外延Si层13由不同的半导体材料构成，并且半导体衬底10可以作为该蚀刻步骤的阻挡层，则在本发明的半导体器件中可以省去外延Si层13。
参见图9，穿过栅极开口24，进行用于沟道掺杂的注入步骤。
对于n型MOSFET，采用的掺杂剂可以是As或P，注入能量约为1-20keV，掺杂剂的浓度约为2×1018-1×1020/cm3；对于p型MOSFET，采用的掺杂剂可以是B或BF2，注入能量约为0.2-20keV，掺杂剂的浓度约为2×1018-1×1020/cm3。
优选地，该注入步骤在栅极开口24的下方形成方块形状的超陡后退岛(SSRI)25。正如本领域已经熟知的那样，SSRI的陡峭的掺杂分布对于减小短沟道效应是有利的。SSRI25位于栅极开口24的底部下方(即与将形成的栅介质层底部之间的距离)大约5～20nm。
在注入步骤之后，可以对掺杂的沟道区进行激光退火，以激活其中的掺杂剂。
在于斌(音译)等人的美国专利US6,214,654B1公开了利用牺牲栅(对应于本申请中的假栅)形成有关超陡后退沟道的上述步骤，其全文内容以引用方式包含在本文中。
参见图10，通过上述常规的沉积工艺，在外延SiGe层上外延生长沟道材料层26，其厚度约为2-7nm。然后，为了在随后的步骤中形成高质量的栅介质层，进一步在沟道材料层26上外延生长厚度约为2-5nm的Si层27。
沟道材料层26替代了外延Si层13的一部分，由载流子迁移率高于后者的半导体材料构成，在本实施例中为高Ge含量的SiGe，其Ge含量约为20～100％。此外，沟道材料层也可以选自III-V族半导体材料，如InP、InSb、InGaAs和InAs。
沟道材料层26的晶体结构在垂直方向上与位于其下方的在图2所示的步骤中形成的外延SiGe层12匹配，并且，在横向方向上与位于其侧面的在图8所示的步骤中暴露的外延Si层13的刻面(facet)匹配。
在优选的实施例中，沟道材料层26在垂直方向上的外延生长发生在Si的{110}晶面上，在水平方向上的外延生长发生在Si的{111}晶面上。
因此，沟道材料层26与外延Si层13之间的界面基本上保持了晶体学上的完整性和连续性，从而减少了钉扎的缺陷数量。并且，在两个方向上的外延生长有利于获得平整的表面，保证了沟道厚度的均匀性。
例如通过热氧化工艺将Si层27的一部分转变为SiO2，形成厚度约为0.5-1nm的SiO2层(未示出)。
通过上述常规的沉积工艺，在半导体结构的整个表面上形成共形的高k电介质层(例如HfO2)，其厚度约为2-5nm，作为最终的MOSFET的栅介质层28。
参见图11，通过上述常规的沉积工艺，在栅极开口24中填充栅极导体29(如W、TiN等金属)。
该步骤可包括首先沉积覆盖金属层，然后对该金属层进行图案化，以保留位于栅极开口24中的材料。优选地，可以在首先沉积覆盖金属层之后进行回蚀刻，通过控制蚀刻时间，使得位于栅极开口24外部的材料完全去除，而位于栅极开口24内部的材料仅有一小部分被去除或者未被去除。
参见图12，通过上述常规的沉积工艺，在半导体结构的整个表面上形成氮化物层30，并经过CMP处理后获得平整的表面。该氮化物层30作为层间隔离层(ILD)，使得在随后的步骤中，可以在氮化物层30的上方形成互连。
参见图13，利用光致抗蚀剂掩模(未示出)，通过上述干法蚀刻，从上至下去除位于接触区21上方的氮化物层30、氧化物层23和氮化物层22的一部分，形成至接触区21的接触孔31。
参见图14，在接触孔31的底部暴露的接触区21的上表面中形成硅化物区32，以减小将要形成的通道导体与接触区21之间的接触电阻。
该步骤包括首先在半导体结构的整个表面上沉积共形的Ni层，然后在大约300-500℃的温度下进行退火，使得Ni与接触区21中的Si反应而形成硅化物，最后例如利用湿法蚀刻，相对于硅化物选择性地去除未参与反应的多余的Ni。
参见图15，在接触孔31中形成金属接触33。
该步骤包括首先通过上述常规的沉积方法，在半导体结构的整个表面(包括接触孔31的侧壁和底部)上沉积共形的阻挡层(例如TiN，未示出)，然后进一步沉积金属层(例如W)以填充接触孔31，最后通过CMP处理去除接触孔31外部的阻挡层和金属层的材料。在接触孔31内的金属层的材料形成了金属接触33。
以上描述只是为了示例说明和描述本发明，而非意图穷举和限制本发明。因此，本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改，均在本发明的保护范围之内。

Claims (18)

1.一种半导体器件，包括：
半导体衬底；
形成于所述半导体衬底上的第一半导体层，以及环绕所述第一半导体层形成的第二半导体层；
所述第一半导体层上形成的高k栅介质层和栅极导体；
所述第二半导体层上形成的源/漏区；
其中，所述第一半导体层和第二半导体层的侧壁为倾斜接触。
2.根据权利要求1所述的半导体器件，其中所述第一半导体层包括选自以下的一种或多种材料的组合：SiGe、InP、InSb、InGaAs和InAs。
3.根据权利要求2所述的半导体器件，所述第一半导体层由SiGe形成，其中的Ge含量为20-100％。
4.根据权利要求1所述的半导体器件，其中所述第一半导体层下方通过刻蚀阻挡层与所述半导体衬底接触。
5.根据权利要求4所述的半导体器件，其中所述刻蚀阻挡层为SiGe层。
6.根据权利要求1所述的半导体器件，其中所述栅介质层的下方形成有P型掺杂或N型掺杂的超陡后退岛。
7.根据权利要求6所述的半导体器件，其中超陡后退岛与栅介质层底部相距5～20nm。
8.根据权利要求1所述的半导体器件，所述源/漏区通过掺杂的SiGe形成。
9.根据权利要求1至8中任一项所述的半导体器件，所述第一半导体层的载流子迁移率大于第二半导体层。
10.根据权利要求1至8中任一项所述的半导体器件，其中所述第一半导体层的上表面和下表面匹配Si的{100}晶面，与所述第二半导体层接触的侧面匹配Si的{111}晶面。
11.一种制造半导体器件的方法，包括：
a)在半导体衬底上形成第二半导体层；
b)在所述第二半导体层上形成假栅极，以及所述假栅极两侧的源/漏区；
c)去除所述假栅极，以形成栅极开口；
d)通过湿法蚀刻选择性去除所述第二半导体层在所述栅极开口中的部分；
e)通过所述栅极开口，在半导体衬底上外延生长第一半导体层
f)在所述栅极开口中形成栅介质层以及栅极导体。
12.根据权利要求11所述的方法，其中所述第二半导体层包括选自以下的一种或多种材料：SiGe、InP、InSb、InGaAs和InAs。
13.根据权利要求12所述的方法，其中所述第二半导体层由SiGe形成，SiGe中的Ge含量为20-100％。
14.根据权利要求10所述的方法，在步骤a之前，所述方法进一步包括：在所述半导体衬底上淀积刻蚀阻挡层。
15.根据权利要求14所述的方法，其中所述刻蚀阻挡层为SiGe层。
16.根据权利要求11所述的方法，在步骤d)和步骤e)之间，所述方法还包括：
通过栅极开口注入N型或P型杂质，以在所述栅极开口下方形成掺杂的超陡后退岛。
17.根据权利要求11至16中任一项所述的方法，其中所述第一半导体层的载流子迁移率高于第二半导体层。
18.根据权利要求11至16中任一项所述的方法，其中步骤d)湿法刻蚀第二导体层，使得所述第二半导体层在所述栅极开口内形成匹配Si的{111}晶面的侧壁。
CN 201010147601 2010-04-14 2010-04-14 半导体器件及其制造方法 Active CN102222692B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN 201010147601 CN102222692B (zh) 2010-04-14 2010-04-14 半导体器件及其制造方法
US13/060,468 US9018739B2 (en) 2010-04-14 2010-09-25 Semiconductor device and method of fabricating the same
PCT/CN2010/001482 WO2011127634A1 (zh) 2010-04-14 2010-09-25 半导体器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201010147601 CN102222692B (zh) 2010-04-14 2010-04-14 半导体器件及其制造方法

Publications (2)

Publication Number Publication Date
CN102222692A true CN102222692A (zh) 2011-10-19
CN102222692B CN102222692B (zh) 2013-06-12

Family

ID=44779197

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201010147601 Active CN102222692B (zh) 2010-04-14 2010-04-14 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US9018739B2 (zh)
CN (1) CN102222692B (zh)
WO (1) WO2011127634A1 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035712A (zh) * 2011-10-09 2013-04-10 中国科学院微电子研究所 半导体器件及其制造方法
CN103066122A (zh) * 2011-10-20 2013-04-24 中国科学院微电子研究所 Mosfet及其制造方法
CN103730369A (zh) * 2012-10-16 2014-04-16 中国科学院微电子研究所 半导体器件制造方法
CN103811348A (zh) * 2012-11-13 2014-05-21 中芯国际集成电路制造(上海)有限公司 Mos器件及其形成方法
CN104701167A (zh) * 2013-12-05 2015-06-10 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN105679674A (zh) * 2014-12-04 2016-06-15 格罗方德半导体公司 使用重叠掩膜减少栅极高度变化的方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543744B (zh) * 2010-12-29 2014-12-24 中芯国际集成电路制造(北京)有限公司 晶体管及其制作方法
US9721827B2 (en) * 2014-02-27 2017-08-01 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement with stress control and method of making
US9419139B2 (en) * 2014-12-04 2016-08-16 Globalfoundries Inc. Nitride layer protection between PFET source/drain regions and dummy gate during source/drain etch
US9379186B1 (en) * 2015-01-30 2016-06-28 Globalfoundries Inc. Fet structure for minimum size length/width devices for performance boost and mismatch reduction
US10141417B2 (en) 2015-10-20 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure, semiconductor device and the method of forming semiconductor device
US10714621B2 (en) * 2016-12-14 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming doped channel thereof
FR3090195B1 (fr) * 2018-12-18 2021-04-02 Commissariat Energie Atomique Procédé de fabrication d’un transistor à effet de champ a performances optimisées

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030162358A1 (en) * 2002-02-26 2003-08-28 International Business Machines Corporation Method of forming a fully-depleted soi (silicon-on-insulator) mosfet having a thinned channel region
CN1832142A (zh) * 2005-03-01 2006-09-13 国际商业机器公司 制作用于cmos器件的自对准双应力衬里的方法和结构
CN101097955A (zh) * 2006-06-29 2008-01-02 国际商业机器公司 半导体器件以及形成半导体器件的方法
US20090302412A1 (en) * 2008-06-04 2009-12-10 International Business Machines Corporation Carrier mobility enhanced channel devices and method of manufacture

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US6939751B2 (en) 2003-10-22 2005-09-06 International Business Machines Corporation Method and manufacture of thin silicon on insulator (SOI) with recessed channel
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US20060065937A1 (en) * 2004-09-30 2006-03-30 Thomas Hoffmann Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030162358A1 (en) * 2002-02-26 2003-08-28 International Business Machines Corporation Method of forming a fully-depleted soi (silicon-on-insulator) mosfet having a thinned channel region
CN1832142A (zh) * 2005-03-01 2006-09-13 国际商业机器公司 制作用于cmos器件的自对准双应力衬里的方法和结构
CN101097955A (zh) * 2006-06-29 2008-01-02 国际商业机器公司 半导体器件以及形成半导体器件的方法
US20090302412A1 (en) * 2008-06-04 2009-12-10 International Business Machines Corporation Carrier mobility enhanced channel devices and method of manufacture

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035712A (zh) * 2011-10-09 2013-04-10 中国科学院微电子研究所 半导体器件及其制造方法
CN103035712B (zh) * 2011-10-09 2015-10-14 中国科学院微电子研究所 半导体器件及其制造方法
CN103066122A (zh) * 2011-10-20 2013-04-24 中国科学院微电子研究所 Mosfet及其制造方法
CN103066122B (zh) * 2011-10-20 2016-01-20 中国科学院微电子研究所 Mosfet及其制造方法
CN103730369A (zh) * 2012-10-16 2014-04-16 中国科学院微电子研究所 半导体器件制造方法
WO2014059562A1 (zh) * 2012-10-16 2014-04-24 中国科学院微电子研究所 半导体器件制造方法
CN103811348A (zh) * 2012-11-13 2014-05-21 中芯国际集成电路制造(上海)有限公司 Mos器件及其形成方法
CN104701167A (zh) * 2013-12-05 2015-06-10 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN104701167B (zh) * 2013-12-05 2017-09-22 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN105679674A (zh) * 2014-12-04 2016-06-15 格罗方德半导体公司 使用重叠掩膜减少栅极高度变化的方法
CN105679674B (zh) * 2014-12-04 2017-09-05 格罗方德半导体公司 使用重叠掩膜减少栅极高度变化的方法

Also Published As

Publication number Publication date
US20110303951A1 (en) 2011-12-15
US9018739B2 (en) 2015-04-28
CN102222692B (zh) 2013-06-12
WO2011127634A1 (zh) 2011-10-20

Similar Documents

Publication Publication Date Title
CN102222692B (zh) 半导体器件及其制造方法
US11251086B2 (en) Semiconductor devices, FinFET devices, and manufacturing methods thereof
US11757002B2 (en) Reduced local threshold voltage variation MOSFET using multiple layers of epi for improved device operation
USRE45944E1 (en) Structure for a multiple-gate FET device and a method for its fabrication
CN102117750B (zh) Mosfet结构及其制作方法
KR20150043261A (ko) 수직 터널링 전계 효과 트랜지스터 셀 및 그 제조 방법
JP2012099517A (ja) 半導体装置及び半導体装置の製造方法
CN105470133B (zh) 半导体器件制造方法
US10438854B2 (en) Method for manufacturing CMOS structure
CN103579004A (zh) FinFET及其制造方法
US8426920B2 (en) MOSFET and method for manufacturing the same
US10096717B2 (en) MOSFET and method for manufacturing the same
CN103377946B (zh) 一种半导体结构及其制造方法
US20060199343A1 (en) Method of forming MOS transistor having fully silicided metal gate electrode
CN104008974A (zh) 半导体器件及其制造方法
US9543450B2 (en) Semiconductor devices and methods for manufacturing the same
CN112786451B (zh) 半导体结构及其形成方法
US9269709B2 (en) MOS transistor structure and method
US11869892B2 (en) Semiconductor device structure and methods of forming the same
CN112151607B (zh) 半导体结构及其形成方法
CN103367128A (zh) 超陡倒掺杂沟道的形成方法、半导体器件及其制造方法
US20240113198A1 (en) Method of modulating multi-gate device channels and structures thereof
CN111627819B (zh) 半导体结构及其形成方法
CN112151606B (zh) 半导体结构及其形成方法
CN111627854B (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant