WO2014059562A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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Publication number
WO2014059562A1
WO2014059562A1 PCT/CN2012/001535 CN2012001535W WO2014059562A1 WO 2014059562 A1 WO2014059562 A1 WO 2014059562A1 CN 2012001535 W CN2012001535 W CN 2012001535W WO 2014059562 A1 WO2014059562 A1 WO 2014059562A1
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Prior art keywords
dummy gate
gate
layer
forming
pattern
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PCT/CN2012/001535
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English (en)
French (fr)
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尹海洲
赵治国
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中国科学院微电子研究所
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Priority to US14/435,261 priority Critical patent/US20150235854A1/en
Publication of WO2014059562A1 publication Critical patent/WO2014059562A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a MOSFET capable of effectively improving a gate profile.
  • HK high-k material
  • EOT effective gate oxide thickness
  • MG metal gate
  • Forming a dummy gate stack depositing an interlayer dielectric layer (1LD), removing a dummy gate stack leaving a gate trench, and depositing a final gate structure of the HK/MG gate stack, relative to the front gate process, Finer control of gate size and avoiding high temperature effects (such as activating dopants in polysilicon, or reducing high-k material interface defects while migrating other impurities in the device, etc.), becoming the mainstream method for HK/MG structure fabrication .
  • RIE reactive ion etching
  • the control of the etching process is complicated, such as the selection of the etching end point, the adjustment of the etching rate, and the etching selectivity ratio. It is often difficult to obtain a completely vertical gate trench, and generally has a slanted sidewall which tends to cause a low filling rate, a void, and the like when a metal material is later deposited to fill the gate.
  • an object of the present invention is to overcome the above problems, and to improve the verticality of the cross-sectional shape of the gate while avoiding erosion of the bottom corner substrate and effectively improving the performance and reliability of the device.
  • the above object of the present invention is achieved by providing a semiconductor device manufacturing method comprising: forming a single crystal etch stop layer and a single crystal dummy gate layer on a substrate; wet etching the dummy gate layer to form a dummy gate a pattern; a gate spacer is formed around the dummy gate pattern; a wet etch removes the dummy gate pattern leaving a gate trench; and a gate stack is formed in the gate trench.
  • the etch stop layer and the dummy gate layer are formed by epitaxial growth.
  • the etch stop layer also applies stress to the substrate.
  • the dummy gate layer is a single crystal Si, which is wet etched by TMAH.
  • the sidewall of the dummy gate pattern is a (1 1 1 ) crystal plane.
  • the method further comprises: forming a lightly doped source/drain extension region in the substrate on both sides of the dummy gate pattern.
  • the wet etching of the dummy gate layer further includes: forming a heavily doped source and drain region in the substrate on both sides of the gate sidewall; forming an interlayer dielectric layer, covering Etching stop layer, gate spacer and dummy gate pattern; planarizing the interlayer dielectric layer until the dummy gate pattern is exposed.
  • the etch stop layer includes single crystal SiGe, Si:C, Si:H, SiGe:C, and combinations thereof.
  • the gate spacers include silicon nitride, silicon oxynitride, diamond-like amorphous carbon, and combinations thereof.
  • the epitaxial single crystal film is used as the dummy gate and the stop layer of the wet etched dummy gate can improve the verticality of the gate cross-sectional shape while avoiding the erosion of the bottom corner substrate. , effectively improve the performance and reliability of the device.
  • 1 to 7 are cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention
  • Figure 8 is a schematic flow chart of a method of fabricating a semiconductor device in accordance with the present invention. detailed description Features of the technical solution of the present invention and technical effects thereof will be described in detail below with reference to the accompanying drawings in conjunction with the exemplary embodiments. It should be noted that like reference numerals indicate similar structures, and the terms “first”, “second”, “upper”, “lower”, “thick”, “thin”, etc., used in the present application may be used. Modification of various device structures. These modifications are not intended to suggest a spatial, order, or hierarchical relationship to the structure of the device being modified unless specifically stated.
  • the substrate 1 is provided, for example, of a body Si, a body Ge, GaAs, SiGe, GeSn, InP, InSb, GaN or the like, and is preferably a body Si (e.g., a single crystal Si wafer).
  • the substrate 1 has a first crystal plane, for example, a (110) plane.
  • the etch stop layer 2 is epitaxially grown on the substrate 1 by PECVD, HDPCVD, MOCVD, MBE, ALD, etc., and the material thereof is preferably similar to the substrate 1 lattice constant (preferably having at least one of the same elements, for example, both Materials containing at least Si) but differing in chemical nature to avoid increasing defects while also increasing the etching selectivity, such as SiGe, Si:C, Si:H, SiGe:C, and the like, and combinations thereof.
  • the etch stop layer 2 is a single crystal material in order to reduce interface defects and improve device reliability.
  • etch stop layer 2 and the substrate 1 have different lattice constants, stress can be applied to the bottom, particularly the channel region, to increase carrier mobility, thereby further improving device performance.
  • LPCVD, PECVD, HDPCVD, ALD, MBE, thermal decomposition, etc. are epitaxially deposited on the etch stop layer 2 to form a dummy gate layer 3, such as single crystal silicon, polycrystalline silicon, amorphous silicon, amorphous germanium, SiGe, Si: C and combinations thereof, and preferably, the dummy gate layer 3 is made of the same material as the substrate 1 and different from the material of the etch stop layer 2, for example, all of single crystal silicon.
  • the dummy gate layer 3 is also a single crystal material.
  • the defects are smaller than those of the conventional CVD and PVD, and the side morphology of the pattern is more vertical in the later etching.
  • the crystal faces of the dummy gate layer 3 are the same as those of the substrate 1, and are all (110) faces.
  • the dummy gate layer is wet etched and stopped on the etch stop layer to form a dummy gate pattern.
  • a photoresist is spin-coated on the dummy gate layer 3 and exposed, developed to form a photoresist pattern (not shown), and then the dummy gate pattern 3 is formed by wet etching the dummy gate layer 3 using this as a mask.
  • TMAH tetradecyl ammonium hydroxide
  • a combination of strong acid + strong oxidant can be used for wet etching, such as sulphuric acid + hydrogen peroxide.
  • the dummy gate pattern 3P Since the TMAH corrosion rate is relatively low on the (111) plane, the final corrosion will form on the (111) plane when the pattern 3P is formed, that is, the dummy gate pattern 3P has the second and because of the partial crystal in the ⁇ 111 ⁇ crystal plane family.
  • the face is perpendicular to the (110) crystal plane (hereinafter referred to as (111) Surface), the formed gate pattern 3 ⁇ not only has a side that is completely vertical or almost completely perpendicular (for example, an angle between the side and the bottom surface is 90 ⁇ 0.5 degrees) (the crystal plane is (1 1 1 )), and the line is rough The degree is also low, and there is no problem of corner erosion at the bottom.
  • a hard mask layer (for example, a material such as SiN, not shown) may be formed on the dummy gate layer 3, the hard mask layer may be dry-etched to form a pattern, and then wet-etched. It is noted that, in order to utilize the stress of the etch stop layer, the mobility of the carriers is increased. In this embodiment, the etch stop layer is retained after the etch forming the dummy gate pattern 3P; In other embodiments, after the etch is formed into the dummy gate pattern 3P, the etch stop layer is continued to be removed until the substrate is exposed.
  • a hard mask layer for example, a material such as SiN, not shown
  • a gate spacer is formed on the side of the dummy gate pattern 3P.
  • Forming an insulating dielectric layer of silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC), and combinations thereof by conventional methods such as LPCVD, PECVD, HDPCVD, magnetron sputtering, etc., and photolithography/engraving The etch only leaves the gate spacer 4 on the side.
  • the gate spacer 4 has stress to further increase the carrier mobility in the channel region.
  • the source and drain regions 1 S/1D may be formed in the substrate 1 on both sides of the dummy gate pattern 3P in the process shown in FIGS. 2 to 3 .
  • the source/drain extension area has been widely known and will not be described here.
  • an interlayer dielectric layer 5 is formed on the device.
  • An interlayer dielectric layer (ILD) 5 of low-k material is formed by spin coating, spray coating, screen printing, CVD, etc., and the material thereof includes, but is not limited to, an organic low-k material (for example, an organic polymer containing an aryl group or a polycyclic ring).
  • Inorganic low-k materials eg, amorphous carbon-nitrogen thin films, polycrystalline boron-nitrogen thin films, fluorosilicate glass, BSG, PSG, BPSG
  • porous low-k materials eg, dialkyltrioxane (SSQ)-based porous low-k materials, Porous silica, porous SiOCH, C-doped silica, F-doped amorphous carbon, porous diamond, porous organic polymer.
  • silicon oxide is deposited by CVD to reduce cost.
  • the ILD 5 is planarized by CMP, etch back, etc. until the dummy gate pattern 3P is exposed.
  • the dummy gate pattern 3P is wet removed, leaving the gate trench 3D. Similar to the method shown in FIG. 2, the dummy gate pattern 3P of the Si material is removed by TMAH wet etching, and is automatically stopped on the etch stop layer 2 of the non-Si material. Since the TMAH etching rate is low on the (1 1 1 ) plane, and the side of the dummy gate pattern 3P is the (1 1 1 ) plane, the formed gate trench 3T is not only completely vertical or almost completely vertical (for example, the side The side with an angle of 90 ⁇ 0.5 degrees from the bottom surface.
  • the formed gate trench 3T not only has a completely vertical or almost completely vertical (for example, an angle between the side surface and the bottom surface) Angle is 90 ⁇ 0.5
  • the side of the degree, and the roughness of the line is also low, and there is no problem of corner erosion at the bottom.
  • the etch stop layer is left after etching the dummy gate pattern 3P; In other embodiments, after the dummy gate pattern 3P is etched, the etch stop layer is continued to be removed until the substrate is exposed to form the gate trench 3T.
  • a gate insulating layer 6, a work function adjusting layer 7, and a resistance adjusting layer 8 are formed in the gate trench 3A and on the ILD 5.
  • the gate insulating layer 6 is deposited by PECVD, HDPCVD, MOCVD, MBE, ALD, etc., and is made of silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof, wherein the high-k materials include, but are not limited to, nitrides. (e.g.
  • a work function adjusting layer 7 made of Al, TiAl, TiN, or TaN is formed on the gate insulating layer 6 in the gate trench by MOCVD, MBE, ALD, evaporation, sputtering, or the like.
  • a resistance adjusting layer 8 is formed on the work function adjusting layer 7 by MOCVD, MBE, ALD, evaporation, sputtering, or the like, and is made of Cu, ⁇ 1, Ti, Mo, Ta, W, and combinations thereof.
  • the gate insulating layer 6, the work function adjusting layer 7, and the resistance adjusting layer 8 are planarized until the ILD 5 is exposed to form the final gate stack structure 6/7/8. Thereafter, the source/drain contact holes and the fill metal can be further etched in the ILD 5 to form a contact to complete the wiring of the final device.
  • the epitaxial single crystal film is used as the dummy gate and the stop layer of the wet etched dummy gate can improve the verticality of the gate cross-sectional shape while avoiding the erosion of the bottom corner substrate. , effectively improve the performance and reliability of the device.

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Abstract

一种半导体器件制造方法，包括：在衬底（1）上形成单晶刻蚀停止层（2）和单晶假栅极层（3）；湿法腐蚀假栅极层（3），形成假栅极图形（3P）；在假栅极图形（3P）周围形成栅极侧墙（4）；湿法腐蚀去除假栅极图形（3P），留下栅极沟槽（3T）；在栅极沟槽（3T）中形成栅极堆叠。利用外延单晶薄膜作为假栅极以及湿法刻蚀假栅极的停止层，在提高栅极剖面形态的垂直度的同时，还能避免底部拐角衬底侵蚀，有效提高器件的性能和可靠性。

Description

半导体器件制造方法 优先权要求
本申请要求了 2012年 10月 16日提交的、申请号为 201210393669.2、 发明名称为 "半导器件制造方法" 的中国专利申请的优先权， 其全部内 容通过引用结合在本申请中。
技术领域
本发明涉及一种半导体器件制造方法， 更具体地， 涉及一种能有 效改进栅极剖面的 MOSFET制造方法。 背景技术
随着 MOSFET等半导体器件尺寸持续等比例缩减，传统的氧化硅栅 极绝缘层和掺杂多晶硅的栅极导电层构成的栅极堆叠结构已经无法适 用于小尺寸器件。 采用高 k材料 （HK ) 以降低有效栅氧厚度 （EOT ) 、 采用金属栅极（ MG )以有效调节栅极功函数， 这种 HK/MG结构成为目 前业界的主流设计。 相对于前栅工艺而言， 形成假栅极堆叠、 沉积层 间介质层 （ 1LD ) 、 去除假栅极堆叠留下栅极沟槽、 沉积最终 HK/MG 栅极堆叠的后栅工艺， 由于可以更精细控制栅极尺寸并且避免高温效 应 （例如在激活多晶硅中掺杂剂、 或者降低高 k材料界面缺陷而退火时 使得器件中其他杂质发生迁移等等） ， 成为 HK/MG结构制造的主流方 法。
然而， 采用例如反应离子刻蚀 （RIE ) 等干法刻蚀去除假栅极堆叠 时， 由于刻蚀工艺的控制较复杂， 例如刻蚀终点的选取、 刻蚀速率的 调整、 刻蚀选择比的选取等等， 往往难以获得完全垂直的栅极沟槽， 而通常具有倾斜的侧壁， 这种倾斜侧壁在稍后沉积金属材料填充栅极 时容易造成填充率低、出现孔隙等问题。而采用 TMAH湿法腐蚀多晶硅、 非晶硅材质的假栅极时， 虽然能形成较为垂直的侧壁， 但是容易在沟 槽底部以及拐角处存在一定量的过刻蚀也即拐角衬底侵蚀， 增大了沟 道区表面的缺陷， 改变了器件的性能。 发明内容
有鉴于此， 本发明的目的在于克服上述问题， 在提高栅极剖面形 态的垂直度的同时， 还能避免底部拐角衬底侵蚀， 有效提高器件的性 能和可靠性。
实现本发明的上述目的， 是通过提供一种半导体器件制造方法， 包括： 在衬底上形成单晶刻蚀停止层和单晶假栅极层； 湿法腐蚀假栅 极层， 形成假栅极图形； 在假栅极图形周围形成栅极侧墙； 湿法腐蚀 去除假栅极图形， 留下栅极沟槽； 在栅极沟槽中形成栅极堆叠。
其中， 采用外延生长形成刻蚀停止层和假栅极层。
其中， 刻蚀停止层还向衬底施加应力。
其中， 假栅极层为单晶 Si, 采用 TMAH湿法腐蚀。
其中， 假栅极图形的侧壁为 （ 1 1 1 ) 晶面。
其中， 形成假栅极图形之后， 形成栅极侧墙之前还包括： 在所述 假栅极图形两侧， 衬底之中形成轻掺杂的源漏扩展区。
其中， 形成栅极側墙之后， 湿法腐蚀假栅极层之前进一步包括： 在所述栅极侧墙两侧， 衬底之中形成重掺杂的源漏区； 形成层间介质 层， 覆盖刻蚀停止层、 栅极侧墙和假栅极图形； 平坦化层间介质层直 至暴露假栅极图形。
其中， 刻蚀停止层包括单晶 SiGe、 Si:C、 Si:H、 SiGe:C及其组合。 其中， 栅极侧墙包括氮化硅、 氮氧化硅、 类金刚石无定形碳及其 组合。
依照本发明的半导体器件制造方法， 利用外延单晶薄膜作为假栅 极以及湿法刻蚀假栅极的停止层， 在提高栅极剖面形态的垂直度的同 时， 还能避免底部拐角衬底侵蚀， 有效提高器件的性能和可靠性。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1至图 7为根据本发明的半导体器件制造方法各个步骤的剖视 图； 以及
图 8为根据本发明的半导体器件制造方法的示意流程图。 具体实施方式 以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结 构， 本申请中所用的术语 "第一" 、 "第二" 、 "上" 、 "下" 、 "厚" 、 "薄" 等等可用于修饰各种器件结构。 这些修饰除非特别说明并非暗 示所修饰器件结构的空间、 次序或层级关系。
参照图 1, 在衬底上形成刻蚀停止层以及假栅极层。 提供衬底 1, 其材质例如是体 Si、 体 Ge、 GaAs、 SiGe、 GeSn、 InP、 InSb、 GaN等等， 并且优选体 Si (例如单晶 Si晶片 ）。 衬底 1具有第一晶面， 例如为（ 110) 面。 随后通过 PECVD、 HDPCVD、 MOCVD、 MBE、 ALD等方法在衬 底 1上外延生长刻蚀停止层 2， 其材质优选为与衬底 1晶格常数相近（优 选具有至少一种相同的元素， 例如均至少包含 Si)、 但是化学性质有区 别的材料以避免增大缺陷同时还能提高刻蚀选择比，例如是 SiGe、 Si:C, Si:H、 SiGe:C等等及其组合。 优选地， 刻蚀停止层 2为单晶材料， 以便 于减小界面缺陷， 提高器件可靠性。 特别地， 由于刻蚀停止层 2与衬底 1晶格常数不同， 可以向^"底特别是沟道区施加应力以增大载流子迁移 率，从而进一步提高器件性能。随后，通过 LPCVD、 PECVD、 HDPCVD、 ALD、 MBE、 热分解等方法在刻蚀停止层 2上外延沉积形成假栅极层 3, 其材质例如是单晶硅、 多晶硅、 非晶硅、 非晶锗、 SiGe、 Si:C及其组合， 并且优选地， 假栅极层 3与衬底 1材质相同而与刻蚀停止层 2材质不同， 例如均为单晶硅。 优选地， 假栅极层 3也为单晶材料， 以便于减小界面 缺陷。 由于层 3、 2均为外延生长， 其缺陷较之普通 CVD、 PVD形成的 层更小， 在稍后的刻蚀中图形的侧面形态会更加垂直。 优选地， 假栅 极层 3的晶面与衬底 1相同， 均为 （ 110) 面。
参照图 2， 湿法刻蚀假栅极层， 停止在刻蚀停止层上， 形成假栅极 图形。 在假栅极层 3上旋涂光刻胶并曝光、 显影形成光刻胶图形 （未示 出） ， 随后以此为掩模采用湿法腐蚀假栅极层 3形成假栅极图形 3P。 对 于 Si材质的假栅极层 3而言， 采用四曱基氢氧化铵 （TMAH) 。 对于其 他材质的假栅极层 3， 可以采用强酸 +强氧化剂的组合来湿法腐蚀， 例 如石克酸 +双氧水。 由于在 （ 111 ) 面上 TMAH腐蚀速率较氐， 因此最终 腐蚀形成图形 3P时会停止在 （ 111 ) 面上， 也即假栅极图形 3P具有第二 并且因为 {111}晶面族中部分晶面与 （ 110)晶面垂直（以下称作（ 111 ) 面） ， 形成的栅极图形 3Ρ不仅具有完全垂直或者几乎完全垂直 （例如 侧面与底面之间的夹角角度为 90 ± 0.5度） 的侧面 （晶面为 （ 1 1 1 ) ) , 而且线条粗糙度也较低、 底部不会出现拐角侵蚀的问题。 此外， 也可 以在假栅极层 3上形成硬掩模层 （例如 SiN等材质， 未示出） ， 干法刻 蚀硬掩模层形成图形， 然后湿法腐蚀。 值得注意的是， 为利用刻蚀停 止层的应力作用， 提高载流子的迁移率， 在本实施例中， 刻蚀形成假 栅极图形 3P之后保留了除刻蚀停止层； 在本发明的其他实施例中， 刻 蚀形成假栅极图形 3P之后， 继续去除刻蚀停止层直至暴露衬底。
参照图 3， 在假栅极图形 3P侧面形成栅极侧墙。 采用传统的方法， 例如 LPCVD、 PECVD、 HDPCVD、 磁控溅射等方法形成氮化硅、 氮氧 化硅、 类金刚石无定形碳 （ DLC ) 及其组合等材质的绝缘介质层， 并 且光刻 /刻蚀而仅在侧面留下栅极侧墙 4。 优选地， 栅极侧墙 4具有应力， 以进一步提高沟道区载流子迁移率。 值得注意的是， 实际上可以在图 2〜图 3所示的过程中在假栅极图形 3P的两侧衬底 1中形成源漏区 1 S/1D (包括重掺杂区以及轻掺杂的源漏扩展区） ， 其方法已广为公知， 在 此不再赘述。
参照图 4 , 在器件上形成层间介质层 5。 通过旋涂、 喷涂、 丝网印 刷、 CVD等方法形成低 k材料的层间介质层 （ILD ) 5， 其材质包括但是 不限于有机低 k材料 （例如含芳基或者多元环的有机聚合物） 、 无机低 k材料（例如无定形碳氮薄膜、 多晶硼氮薄膜、 氟硅玻璃、 BSG、 PSG、 BPSG ) 、 多孔低 k材料 （例如二硅三氧烷 （ SSQ ) 基多孔低 k材料、 多 孔二氧化硅、 多孔 SiOCH、 掺 C二氧化硅、 掺 F多孔无定形碳、 多孔金 刚石、 多孔有机聚合物） 。 优选地， 采用 CVD沉积氧化硅以降低成本。 优选地， 采用 CMP、 回刻等方法平坦化 ILD 5直至暴露假栅极图形 3P。
参照图 5， 湿法去除假栅极图形 3P， 留下栅极沟槽 3丁。 与图 2所示 方法类似， 采用 TMAH湿法腐蚀去除 Si材质的假栅极图形 3P， 并自动停 止在非 Si材质的刻蚀停止层 2上。 由于在（ 1 1 1 )面上 TMAH腐蚀速率较 低， 并且假栅极图形 3P的侧面为 （ 1 1 1 ) 面， 因此形成的栅极沟槽 3T不 仅具有完全垂直或者几乎完全垂直 （例如侧面与底面之间的夹角角度 为 90 ± 0.5度） 的侧面。 由于 TMAH基本不与不同于 Si材料的刻蚀停止 层 2反应， 并且因为外延层缺陷密度低， 形成的栅极沟槽 3T不仅具有完 全垂直或者几乎完全垂直 （例如侧面与底面之间的夹角角度为 90 ± 0.5 度） 的侧面， 而且线条粗糙度也较低、 底部不会出现拐角侵蚀的问题。 与前面所述原因类似， 为利用刻蚀停止层的应力作用， 提高载流子的 迁移率， 在本实施例中， 刻蚀假栅极图形 3P之后保留了刻蚀停止层； 在本发明的其他实施例中， 刻蚀假栅极图形 3P之后， 继续去除刻蚀停 止层直至暴露衬底， 以形成栅极沟槽 3T。
参照图 6， 在栅极沟槽 3Τ中以及 ILD 5上形成栅极绝缘层 6、 功函数 调节层 7、 以及电阻调节层 8。 采用 PECVD、 HDPCVD、 MOCVD、 MBE、 ALD等方式沉积栅极绝缘层 6， 其材质为氧化硅、 氮化硅、 氮氧化硅、 高 k材料及其组合， 其中高 k材料包括但不限于氮化物（例如 SiN、 A1N、 TiN ) 、 金属氧化物 （主要为副族和镧系金属元素氧化物， 例如 A1203、 Ta205、 Ti02、 ZnO、 Zr02、 ΗίΌ2、 Ce02、 Y203、 La203 ) 、 钙钛矿相 氧化物（例如 PbZrxTi1 -x03 ( PZT )、 BaxSrl-xTi03 ( BST ) )。通过 MOCVD、 MBE、 ALD、 蒸发、 溅射等方法， 在栅极沟槽中栅极绝缘层 6上形成 Al、 TiAl、 TiN、 TaN材质的功函数调节层 7。 通过 MOCVD、 MBE、 ALD、 蒸发、 溅射等方法， 在功函数调节层 7上形成电阻调节层 8 , 其材质为 Cu、 Λ1、 Ti、 Mo、 Ta、 W及其组合。
参照图 7， 平坦化栅极绝缘层 6、 功函数调节层 7、 以及电阻调节层 8 , 直至暴露 ILD 5， 构成最终的栅极堆叠结构 6/7/8。 此后， 可以进一 步在 ILD 5中刻蚀形成源漏接触孔、 填充金属形成接触， 完成最终器件 的布线。
依照本发明的半导体器件制造方法， 利用外延单晶薄膜作为假栅 极以及湿法刻蚀假栅极的停止层， 在提高柵极剖面形态的垂直度的同 时， 还能避免底部拐角衬底侵蚀， 有效提高器件的性能和可靠性。
尽管已参照一个或多个示例性实施例说明本发明 , 本领域 4支术人 员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合 适的改变和等价方式。 此外， 由所公开的教导可做出许多可能适于特 定情形或材料的修改而不脱离本发明范围。 因此， 本发明的目的不在 于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实 施例。

Claims

权 利 要 求
1 . 一种半导体器件制造方法， 包括：
在衬底上形成单晶刻蚀停止层和单晶假栅极层；
湿法腐蚀假栅极层， 形成假栅极图形；
在假栅极图形周围形成栅极侧墙；
湿法腐蚀去除假栅极图形， 留下栅极沟槽；
在栅极沟槽中形成栅极堆叠。
2. 如权利要求 1的方法， 其中， 采用外延生长形成刻蚀停止层和 假栅极层。
3. 如权利要求 1的方法， 其中， 刻蚀停止层还向衬底施加应力。
4. 如权利要求 1的方法， 其中， 假栅极层为单晶 Si, 采用 TMAH湿 法腐蚀。
5. 如权利要求 1的方法， 其中， 假栅极图形的侧壁为 （ 1 1 1 )晶面。
6. 如权利要求 1的方法， 其中， 形成假栅极图形之后， 形成栅极 侧墙之前还包括： 在所述假栅极图形两侧， 衬底之中形成轻掺杂的源 漏扩展区。
7. 如权利要求 1的方法， 其中， 形成栅极侧墙之后， 湿法腐蚀假 栅极层之前进一步包括：
在所述栅极侧墙两侧， 衬底之中形成重掺杂的源漏区；
形成层间介质层， 覆盖刻蚀停止层、 栅极侧墙和假栅极图形； 平坦化层间介质层直至暴露假栅极图形。
8. 如权利要求 1的方法， 其中， 刻蚀停止层包括单晶的 SiGe、 Si:C、 Si:H、 SiGe:C及其组合。
9. 如权利要求 1的方法， 其中， 栅极侧墙包括氮化硅、 氮氧化硅、 类金刚石无定形碳及其组合。
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