TWI641148B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI641148B
TWI641148B TW105139536A TW105139536A TWI641148B TW I641148 B TWI641148 B TW I641148B TW 105139536 A TW105139536 A TW 105139536A TW 105139536 A TW105139536 A TW 105139536A TW I641148 B TWI641148 B TW I641148B
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curvature
radius
groove
semiconductor
epitaxial
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TW201724523A (zh
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程潼文
陳志山
林木滄
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台灣積體電路製造股份有限公司
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Abstract

一種半導體元件包含半導體基材、複數半導體鰭片、閘極堆疊與磊晶結構。半導體鰭片係位於半導體基材上。半導體鰭片分別包含凹陷於其中。閘極堆疊係位於半導體鰭片之部分上，且此部分係鄰近凹陷。磊晶結構係橫跨半導體鰭片之凹陷。磊晶結構包含複數轉角與至少一凹槽，凹槽係位於於轉角之間，且凹槽具有一曲率半徑，此曲率半徑係大於轉角之至少一者的曲率半徑。

Description

半導體元件及其製造方法
本揭露之部分實施方式係關於一種半導體元件及其製造方法。
近年來，隨著電晶體之效能改善與電晶體之尺寸縮小的高速競爭下，由基材所形成之通道與位於鰭片中的源極/汲極區域之電晶體已蓬勃發展。此非平面元件係多閘極鰭式場效電晶體(Fin Field-Effect Transistor；FinFET)。多閘極鰭式場效電晶體具有跨過鰭片狀之矽主體之閘極電極以形成通道區域。磊晶源極/汲極區域係鄰近通道區域以在通道區域中增加載流子遷移率。
依據本揭露之部分實施方式，一種半導體元件包含半導體基材、複數半導體鰭片、閘極堆疊與磊晶結構。半導體鰭片係位於半導體基材上。半導體鰭片分別包含凹陷於其中。閘極堆疊係位於半導體鰭片之部分上，且此部分係鄰近凹陷。磊晶結構係橫跨半導體鰭片之凹陷。磊晶結構包含複數轉 角與至少一凹槽，凹槽係位於於轉角之間，且凹槽具有一曲率半徑，此曲率半徑係大於轉角之至少一者的曲率半徑。
依據本揭露之部分實施方式，一種半導體元件包含半導體基材、複數半導體鰭片、閘極堆疊及磊晶結構。半導體鰭片係位於半導體基材上。半導體鰭片分別包含複數凹陷於其中。閘極堆疊係位於半導體鰭片之部分上，且半導體鰭片之此部分係鄰近凹陷。磊晶結構係橫跨半導體鰭片之凹陷。磊晶結構包含至少一凹槽於其中。磊晶結構之凹槽具有一曲率半徑，此曲率半徑係大於約0.5奈米。
依據本揭露之部分實施方式，一種形成半導體元件之方法包含以下步驟。形成複數半導體鰭片於半導體基材上。移除半導體鰭片之部分以形成複數凹陷。形成一閘極堆疊於半導體鰭片之其他部分上，且半導體鰭片之其他部分係鄰近凹陷。形成複數磊晶結構於凹陷中，至少直到磊晶結構合併，且在合併之磊晶結構中形成一凹槽為止。調整凹槽之形狀，使得形狀調整後之凹槽具有一曲率半徑，且此曲率半徑係大於形狀調整前之凹槽之曲率半徑。
100‧‧‧基材
110‧‧‧半導體鰭片
112‧‧‧凹陷
114‧‧‧嵌入部分
116‧‧‧突出部分
120‧‧‧隔離結構
130‧‧‧虛設閘極材料層
140‧‧‧遮罩層
150‧‧‧虛設閘極堆疊
160‧‧‧間隔物
170‧‧‧形狀尚未調整之磊晶結構
172‧‧‧磊晶層
174‧‧‧覆蓋層
175‧‧‧磊晶結構
176‧‧‧覆蓋層
180‧‧‧合併磊晶結構
185‧‧‧合併磊晶結構
186‧‧‧凹槽
187‧‧‧凹面
188‧‧‧頂轉角
200‧‧‧層間介電層
210‧‧‧凹陷
220‧‧‧閘極介電層
230‧‧‧閘極電極層
240‧‧‧閘極堆疊
250‧‧‧源極/汲極接觸
252‧‧‧下表面
閱讀以下詳細敘述並搭配對應之圖式，可了解本揭露之多個樣態。需留意的是，圖式中的多個特徵並未依照該業界領域之標準作法繪製實際比例。事實上，所述之特徵的尺寸可任意的增加或減少以利於討論的清晰性。
第1圖至第13圖為依據本揭露之部分實施方式於不同步驟 形成半導體元件的剖面示意圖。
以下將以圖式及詳細說明清楚說明本揭露之精神，任何所屬技術領域中具有通常知識者在瞭解本揭露之實施方式後，當可由本揭露所教示之技術，加以改變及修飾，其並不脫離本揭露之精神與範圍。舉例而言，敘述「第一特徵形成於第二特徵上方或上」，於實施方式中將包含第一特徵及第二特徵具有直接接觸；且也將包含第一特徵和第二特徵為非直接接觸，具有額外的特徵形成於第一特徵和第二特徵之間。此外，本揭露在多個範例中將重複使用元件標號以及/或文字。重複的目的在於簡化與釐清，而其本身並不會決定多個實施方式以及/或所討論的配置之間的關係。
此外，方位相對詞彙，如「在...之下」、「下面」、「下」、「上方」或「上」或類似詞彙，在本文中為用來便於描述繪示於圖式中的一個元件或特徵至另外的元件或特徵之關係。方位相對詞彙除了用來描述裝置在圖式中的方位外，其包含裝置於使用或操作下之不同的方位。當裝置被另外設置(旋轉90度或者其他面向的方位)，本文所用的方位相對詞彙同樣可相應地進行解釋。
第1圖至第13圖為依據本揭露之部分實施方式於不同步驟形成半導體元件的剖面示意圖。參照第1圖。半導體鰭片110係形成於基材100上。在部分實施方式中，基材100包含塊體矽基材。在部分實施方式中，基材100可為結晶矽。在 其他實施方式中，基材100可包含其他半導體元素，例如：鍺，或包含半導體化合物，例如：碳化矽、砷化鎵、砷化銦、或磷化銦。在其他實施方式中，基材100包含絕緣層覆矽(SOI)基材。絕緣層覆矽基材係可藉由使用氧佈植分離、晶圓接合、及/或其他適當方法形成。
半導體鰭片110可從基材100延伸。半導體鰭片110係可藉由使用適當製程，例如：光微影及蝕刻所形成。在部分實施方式中，半導體鰭片110係藉由使用乾式蝕刻或電漿製程以從基材100蝕刻。隨後，隔離結構120係被形成以填充在半導體鰭片110之間之溝槽的下部，而作為淺溝槽隔離(shallow trench isolation；STI)。換句話說，半導體鰭片110係被隔離結構120所圍繞。隔離結構120可包含任何適當介電材料，例如：氧化矽。形成隔離結構120之方法包含在基材100上沉積介電材料以覆蓋半導體鰭片110，視情況執行平坦化製程以移除在半導體鰭片110間之溝槽外的過量介電材料。隨後，在餘留介電材料上執行蝕刻製程直至暴露半導體鰭片110之上部。
參照第2圖。虛設閘極材料層130係形成於半導體鰭片110上。虛設閘極材料層130可包含多晶矽。虛設閘極材料層130係可藉由沉積製程，例如：化學氣相沉積(Chemical Vapor Deposition；CVD)製程所形成。遮罩層140係藉由沉積製程，例如：化學氣相沉積製程，形成於虛設閘極材料層130上。在部分實施方式中，遮罩層140可包含硬遮罩，例如：氮化矽(SiN)、氧化矽或及其組合。在部分實施方式中，遮罩層 140可係多層結構。舉例來說，遮罩層140可包含在虛設閘極材料層130上形成之氮化矽層與在氮化矽層上形成之氧化矽層。
參照第3圖。遮罩層140與虛設閘極材料層130係被圖案化以形成跨過部分半導體鰭片110之虛設閘極堆疊150。除虛設閘極堆疊150之外的半導體鰭片110之其他部分係被暴露。圖案化步驟包含執行光微影與蝕刻製程。
參照第4圖。一對間隔物160係形成於虛設閘極堆疊150之相對側壁上。在部分實施方式中，間隔物160可包含氧化矽、氮化矽、氮氧化矽、或其他適當材料。間隔物160可包含單層或多層結構。間隔物160之形成方法包含在基材100上形成介電層，且隨後執行蝕刻製程以移除部分介電層。在部分實施方式中，間隔物160可用以偏移隨後形成之摻雜區域，例如：源極/汲極區域。間隔物160可進一步用於設計或修正源極/汲極區域之輪廓。
參照第5圖。由虛設閘極堆疊150及間隔物160所暴露之部分半導體鰭片110係分別被部分地移除(或部分挖凹)以形成凹陷112。在此移除步驟之後，至少一餘留半導體鰭片110具有嵌入部分114及突出部分116。嵌入部分114係嵌入隔離結構120中，且嵌入部分114係至少部分被凹陷112暴露。突出部分116係從嵌入部分114突出並鄰近凹陷112。虛設閘極堆疊150與間隔物160係覆蓋於突出部分116上，且分別由間隔物160暴露突出部分116之相對側壁。可使用虛設閘極堆疊150及間隔物160作為硬遮罩，並藉由反應性離子蝕刻(Reactive Ion Etching；RIE)，或任何其他適當移除製程執行此移除。在部分實施方式中，可在壓力約1毫托至1000毫托之間，功率約50瓦至1000瓦之間，偏壓約20伏至500伏之間，溫度約40℃至60℃之間，使用溴化氫及/或氯氣作為蝕刻氣體，以執行此蝕刻製程。此外，在此實施方式中，可調整用於蝕刻製程之偏壓以允許良好控制蝕刻方向，從而得到半導體鰭片110之嵌入部分114之預定輪廓。
參照第6圖。形狀尚未調整(unshaped)之磊晶結構170係分別形成於凹陷112中且在半導體鰭片110之嵌入部分114上。在此磊晶製程期間，形狀尚未調整之磊晶結構170之磊晶生長係縱向與橫向延伸，使得形狀尚未調整之磊晶結構170合併在一起(或實體連接)以形成形狀尚未調整之合併磊晶結構180，且形狀尚未調整之合併磊晶結構180係橫跨半導體鰭片110之凹陷112。形狀尚未調整之磊晶結構170係藉由使用一或多磊晶製程形成，從而在半導體鰭片110之嵌入部分114中形成呈結晶狀態之矽特徵、矽鍺特徵、其他適當特徵或其組合。舉例來說，至少一形狀尚未調整之磊晶結構170具有磊晶層172及覆蓋層174。覆蓋層174覆蓋磊晶層172。在部分實施方式中，磊晶層172包含矽鍺，且覆蓋層174包含矽。磊晶層172係可藉由磊晶生長形成於嵌入部分114上。覆蓋層174亦可藉由磊晶生長形成於磊晶層172上。在部分實施方式中，覆蓋層174包含實質上純矽。此覆蓋層174可增加形狀尚未調整之磊晶結構170之導電性。形狀尚未調整之磊晶結構170之覆蓋層174係被合併。
在部分實施方式中，形狀尚未調整之磊晶結構170的晶格常數係與半導體鰭片110之晶格常數不同，因此在由虛設閘極堆疊150覆蓋之半導體鰭片110之突出部分中的通道可被磊晶結構170施加應力或應變以提升半導體元件之載子遷移率且增強元件效能。舉例來說，半導體鰭片110包含矽，且磊晶結構170之磊晶層172包含矽鍺。磊晶製程之一些實施例包含化學氣相沉積技術(例如：氣相磊晶(Vapor-Phase Epitaxy；VPE)及/或超高真空化學氣相沉積(Ultra-High Vacuum CVD；UHV-CVD))、分子束磊晶、及/或其他適當製程。磊晶製程可使用氣態及/或液態先驅物，以與半導體鰭片110之嵌入部分114之成分互相反應。在部分實施方式中，當形狀尚未調整之磊晶結構170包含矽鍺時，例如：具有矽鍺之磊晶層172，形狀尚未調整之磊晶結構170之磊晶生長的先驅物可分別包含含矽之氣體及含鍺之氣體，例如：矽甲烷(SiH4)與鍺烷(GeH4)，並調整含矽氣體與含鍺氣體之分壓以改變鍺原子百分比與矽原子百分比。在磊晶生長期間，可控制含鍺之先驅物的流率以調整形狀尚未調整之磊晶結構170的大小。在部分實施方式中，可控制含鍺氣體之流率以增加形狀尚未調整之磊晶結構170的大小，且此含鍺氣體之流率控制可增加在隨後製程中所形成的源極/汲極接觸的面積。
在部分實施方式中，形狀尚未調整之磊晶結構170可為原位摻雜。舉例來說，摻雜種類包含p型摻雜，例如：硼或氟化硼(BF2)、及/或其他適當摻雜。若形狀尚未調整之磊晶結構170不為原位摻雜，則可執行第二佈植製程(亦即，接 合佈植製程)以摻雜形狀尚未調整之磊晶結構170。可執行一或多退火製程以活化形狀尚未調整之磊晶結構170。退火製程包含快速熱退火(Rapid Thermal Annealing；RTA)及/或雷射退火製程。
參照第7圖與第8圖，其中第8圖係沿第7圖之線8-8的剖面圖。形狀調整製程係被執行以將第6圖之形狀尚未調整之合併磊晶結構180調整形狀為形狀調整後之合併磊晶結構185。舉例來說，第6圖之合併磊晶結構180可被蝕刻以形成具有實質上光滑轉角的合併磊晶結構185。由於合併磊晶結構185係藉由形狀調整製程調整形狀，因此合併磊晶結構185包含實質上圓形之至少一彎曲凹槽186。在隨後製程中，此實質上圓形之凹槽186可增加源極/汲極接觸所形成之面積。換句話說，於第6圖之形狀尚未調整之磊晶結構170係被調整形狀為第7圖之形狀調整後之磊晶結構175，且於第6圖之形狀尚未調整之磊晶結構170之間之凹槽186係被調整形狀為第7圖之介於磊晶結構175之間之凹槽186，使得在第7圖之形狀調整後之磊晶結構175之間的凹槽186的曲率半徑，大於第6圖之形狀尚未調整之磊晶結構170之間的凹槽的曲率半徑。換個方式說，第6圖中之形狀尚未調整之磊晶結構170係被調整形狀以形成第7圖中之形狀調整後之磊晶結構175，這些磊晶結構175共同形成凹面187，且凹面187定義實質上圓形凹槽186於其上。換句話說，凹面187係實質上圓形以作為實質上圓形凹槽186之下表面。在隨後製程中，此凹面187之實質上圓形剖面可增加源極/汲極接觸所形成之面積。在部分實施方式中，凹面187 (或實質上圓形凹槽186)之曲率半徑係大於約0.5奈米，其源極/汲極接觸所形成之面積可被增加。在部分實施方式中，至少一形狀調整後之磊晶結構175之高度範圍係從約40奈米至約60奈米。在部分實施方式中，至少一形狀調整後之磊晶結構175之寬度範圍係從約30奈米至約50奈米。
在部分實施方式中，如在第8圖所示，形狀調整後之合併磊晶結構185具有頂轉角188。形狀調整後之合併磊晶結構185之頂轉角188係分別覆蓋於形成形狀調整後之磊晶結構175之半導體鰭片110。換句話說，多個頂轉角188在基材100之表面102上之投影分別與多個半導體鰭片110重疊。實質上圓形凹槽186係位於此些頂轉角188之間，且凹面187亦係位於此些頂轉角188之間。在部分實施方式中，形狀調整製程係將頂轉角188調整形狀為實質上圓形轉角。在部分實施方式中，藉由形狀調整製程，至少一實質上圓形頂轉角188之曲率半徑係小於實質上圓形凹槽186的曲率半徑。換句話說，實質上圓形凹槽186之曲率半徑係大於實質上圓形頂轉角188之曲率半徑，使得源極/汲極接觸所形成之面積可被增加。舉例來說，實質上圓形凹槽186之曲率半徑係大於約0.5奈米，且實質上圓形頂轉角188之曲率半徑範圍係從約1奈米至約10奈米、或小於約0.5奈米。
實質上圓形頂轉角188係相對於實質上圓形凹槽186凸起。換句話說，實質上圓形凹槽186係相對於實質上圓形頂轉角188凹進並位於多個實質上圓形頂轉角188之間。換句話說，實質上圓形頂轉角188係鄰近凹面187之兩相對側， 且凹面187具有與實質上圓形頂轉角188相比更接近基材100之底部。換句話說，從凹面187之底部至基材100之表面102的距離比從實質上圓形頂轉角188至基材100之表面102的距離短。在此配置中，實質上圓形頂轉角188與實質上圓形凹槽186可共同形成實質上波紋狀表面，且實質上波紋狀表面之凹進區域具有大於實質上波紋狀表面之凸起區域的曲率半徑，這可增加源極/汲極接觸所形成之面積。
在部分實施方式中，在形狀調整製程之後，覆蓋層174之至少一部分係被移除。位於磊晶層172之間的覆蓋層174之合併部分係被保留以作為合併覆蓋層176。實質上圓形凹槽186係形成於合併覆蓋層176之外表面上。換句話說，合併之覆蓋層176係被成形以在其上形成凹面187。在部分實施方式中，覆蓋層174係被調整形狀，且磊晶層172係不被調整形狀。在部分實施方式中，覆蓋層174與磊晶層172皆係被調整形狀。在部分實施方式中，在形狀調整製程之後，磊晶層172之一部分係被暴露，且磊晶層172之暴露表面係鄰近定義實質上圓形凹槽186之凹面187。
在部分實施方式中，實質上圓形頂轉角188係形成於磊晶層172上。換句話說，磊晶層172具有藉由形狀調整製程形狀調整後之實質上圓形頂轉角188。在部分實施方式中，實質上圓形凹槽186之底部與實質上圓形頂轉角188之頂部係由不同材料所形成。舉例來說，實質上圓形凹槽186之底部包含矽，且實質上圓形頂轉角188之頂部包含矽鍺。在部分 實施方式中，選擇性磊晶製程係執行於合併磊晶結構185以在合併之磊晶結構185上形成另一矽頂蓋，從而改善導電性。
在部分實施方式中，形狀調整製程包含等向性蝕刻製程。換句話說，等向性蝕刻製程係執行於第6圖之形狀尚未調整之合併磊晶結構180以形成第7圖中形狀調整後之合併磊晶結構185。等向性蝕刻係一種不包含優先方向之蝕刻。在部分實施方式中，等向性蝕刻可為鍺選擇性蝕刻製程、矽選擇性蝕刻製程、或其組合。舉例來說，用於等向性蝕刻製程之蝕刻劑可包含氫氟酸(HF)、氫氯酸(HCl)、氫溴酸(HBr)、過氧化氫(H2O2)、其他適當蝕刻劑、或及其組合。矽選擇性蝕刻製程係指對矽具有選擇性的蝕刻製程。換句話說，在單一蝕刻製程中，含矽結構之蝕刻量係大於另一結構之蝕刻量。相似地，鍺選擇性蝕刻製程係指對鍺具有選擇性之蝕刻製程。換句話說，在單一蝕刻製程中，含鍺結構之蝕刻量係大於另一結構之蝕刻量。
在部分實施方式中，如第8圖所示，基材100具有表面102，且半導體鰭片110係位於基材100之表面102上(或從表面102突出)。實質上圓形凹槽186在基材100之表面102上的投影至少係位於相鄰半導體鰭片110之間。因此，源極/汲極接觸所形成之面積可被增加。
在部分實施方式中，如第8圖所示，部分隔離結構120係位於合併磊晶結構185下方。換句話說，合併磊晶結構185在基材100之表面102上之投影與隔離結構120在基材100之表面102上之投影係重疊。隔離結構120具有鄰近合併磊 晶結構185之頂面122。換句話說，頂面122係遠離基材100。藉由形狀調整製程，隔離結構120之頂面122係至少部分被挖凹。換句話說，隔離結構120之頂面122可為凹面，且藉由至少此形狀調整製程以形成此凹面輪廓。舉例來說，頂部凹面122可為彎曲或實質上圓形。
參照第9圖。層間介電(Interlayer Dielectric；ILD)層200係形成於基材100上以覆蓋虛設閘極堆疊150、磊晶結構185及半導體鰭片110。層間介電層200可包含氧化矽、氮化矽、氮氧化矽、碳化矽、低介電常數介電材料、或及其組合。藉由沉積製程，例如：化學氣相沉積製程形成層間介電層200。然後，部分層間介電層200係被移除以暴露虛設閘極堆疊150之頂面。移除步驟可包含執行化學機械研磨(Chemical-Mechanical Polishing；CMP)製程。
參照第10圖。間隔物160間之虛設閘極堆疊150係藉由使用適當製程，例如：光微影及蝕刻而移除以形成凹陷210。凹陷210之形成係藉由反應性離子蝕刻或藉由任何其他適當移除製程所形成。凹陷210之形成可包含選擇性蝕刻製程，其係選擇性蝕刻虛設閘極堆疊150，並相對地不蝕刻或少量蝕刻下方的半導體鰭片110之突出部分。在凹陷210形成期間，可藉由遮罩，例如：光阻遮罩或硬遮罩，保護間隔物160及層間介電層200。在凹陷210形成之後，可藉由灰化、剝離、或其他適當技術移除遮罩。
參照第11圖及第12圖，其中第12圖係沿第11圖中之線12的剖面圖。閘極介電層220係形成於凹陷210中，且位 於凹陷210中之半導體鰭片110之突出部分上。閘極電極層230係形成於凹陷210中且在閘極介電層220上。閘極介電層220與閘極電極層230在間隔物160之間形成閘極堆疊240。舉例而言，可防止電子空乏的閘極介電層220材料可包含：高介電係數之介電材料，例如：金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽酸鹽、金屬氮氧化物、金屬鋁酸鹽、矽酸鋯、鋁酸鋯、或其組合。在部分實施方式中，閘極介電層220可包含氧化鉿(HfO2)、氧化矽鉿(HfSiO)、氮氧化矽鉿(HfSiON)、氧化鉭鉿(HfTaO)、氧化鈦鉿(HfTiO)、氧化鋯鉿(HfZrO)、氧化鑭(LaO)、氧化鋯(ZrO)、氧化鈦(TiO)、氧化鉭(Ta2O5)、氧化釔(Y2O3)、氧化鈦鍶(SrTiO3、STO)、氧化鈦鋇(BaTiO3、BTO)、氧化鋯鋇(BaZrO)、氧化鑭鉿(BaZrO)、氧化矽鑭(LaSiO)、氧化矽鋁(AlSiO)、氧化鋁(Al2O3)、氮化矽(Si3N4)、氮氧化物(SiON)、或其組合。閘極介電層220可具有多層結構，例如：一層氧化矽(例如：界面層)及另一層高介電係數材料。閘極介電層220係可藉由使用化學氣相沉積、物理氣相沉積、原子層沉積、熱氧化、臭氧氧化、其他適當製程、或其組合所形成。
在部分實施方式中，閘極電極層230包含半導體材料例如：多晶矽、非晶矽、或諸如此類的材料。閘極電極層230係被摻雜沉積或未摻雜沉積。舉例而言，在部分實施方式中，閘極電極層230包含藉由低壓化學氣相沉積沉積之未經摻雜之多晶矽。於實際應用中，多晶矽可摻雜，例如：磷離子(或其他P型摻雜劑)以形成P型金氧半元件；或者摻雜硼(或其 他N-型摻雜劑)以形成N型金氧半元件。舉例而言，藉由加熱爐沉積原位摻雜多晶矽，多晶矽亦可被沉積。或者，閘極電極層230可包含多晶矽金屬合金或包含金屬例如：鎢(W)、鎳(Ni)、鋁(Al)、鉭(Ta)、鈦(Ti)、或其組合的金屬閘極。
參照第13圖。源極/汲極接觸250係形成於層間介電層200中，且係接觸磊晶結構185之實質上圓形凹面187。換句話說，源極/汲極接觸250係形成於實質上圓形凹槽186上。在部分實施方式中，由於源極/汲極接觸250係形成於實質上圓形凹面187上，源極/汲極接觸250可包含具有實質上圓形下表面252，且實質上圓形下表面252係對應實質上圓形凹面187的輪廓。換句話說，實質上圓形下表面252係接觸實質上圓形凹面187，且實質上圓形下表面252具有與凹槽186之曲率半徑實質上相同之曲率半徑。在部分實施方式中，實質上圓形下表面252之曲率半徑係大於約0.5奈米。在部分實施方式中，實質上圓形下表面252之曲率半徑係大於實質上圓形頂轉角188之曲率半徑。源極/汲極接觸250之形成可包含形成接觸孔，接觸孔係藉由蝕刻製程以穿過層間介電層200且向下蝕刻至合併磊晶結構185之實質上圓形凹面187，接著，藉由沉積製程，例如：化學氣相沉積製程，將金屬或其他適當導電材料沉積於接觸孔中，以形成源極/汲極接觸250。
在部分實施方式中，橫跨半導體鰭片之凹陷之磊晶結構具有凹槽。此凹槽係被調整形狀以具有一曲率半徑，此曲率半徑係大於磊晶結構之轉角之曲率半徑。因此，源極/汲極接觸可被形成於較大面積上，並可藉此降低接觸電阻。
上述已概述數個實施方式的特徵，因此熟習此技藝者可更了解本揭露之態樣。熟悉此技藝者應了解到，其可輕易地利用本揭露做為基礎，來設計或潤飾其他製程與結構，以實現與在此所介紹之實施方式相同之目的及/或達到相同的優點。熟悉此技藝者也應了解到，這類均等架構並未脫離本揭露之精神和範圍，且熟悉此技藝者可在不脫離本揭露之精神和範圍下，進行各種之更動、取代與潤飾。

Claims (10)

  1. 一種半導體元件，包含一半導體基材；複數半導體鰭片，於該半導體基材上，該些半導體鰭片分別包含複數凹陷於其中；至少一閘極堆疊，於該些半導體鰭片之部分上，且該些半導體鰭片之該些部分係鄰近該些凹陷；以及至少一磊晶結構，橫跨該些半導體鰭片之該些凹陷，其中該磊晶結構包含複數轉角與至少一凹槽，該凹槽係位於該些轉角之間，且該凹槽具有一曲率半徑，該凹槽之該曲率半徑係大於該些轉角之至少一者的曲率半徑。
  2. 如申請專利範圍第1項所述之半導體元件，其中該磊晶結構更包含分複數個磊晶層，該些磊晶層係分別位於該些半導體鰭片上，且至少一帽層(cap layer)係位於該些磊晶層之間，其中該凹槽係至少位於該帽層上。
  3. 如申請專利範圍第1項所述之半導體元件，更包含：至少一接觸，於該凹槽上；其中該接觸具有一下表面，該下表面接觸該磊晶結構，該接觸之該下表面具有一曲率半徑，該曲率半徑係大於該些轉角之至少一者之曲率半徑；或其中該接觸具有一下表面，該下表面接觸該磊晶結構，該接觸之該下表面具有一曲率半徑，該曲率半徑係大於約0.5奈米。
  4. 如申請專利範圍第1項所述之半導體元件，其中該凹槽之該曲率半徑係大於約0.5奈米；或其中該些轉角之至少一者之該曲率半徑係小於約0.5奈米。
  5. 一種半導體元件，包含：一半導體基材；複數半導體鰭片，於該半導體基材上，該些半導體鰭片分別包含複數凹陷於其中；至少一閘極堆疊，於該些半導體鰭片之部分上，且該半導體鰭片之該些部分係鄰近該些凹陷；至少一磊晶結構，橫跨該些半導體鰭片之該些凹陷，其中該磊晶結構包含至少一凹槽及至少一轉角於其中，該轉角係鄰近於該凹槽，且該磊晶結構之該凹槽具有一曲率半徑，該曲率半徑係大於約0.5奈米；以及至少一接觸，具有一下表面，該下表面接觸該磊晶結構，其中該接觸之該下表面具有一曲率半徑，該下表面之該曲率半徑係大於該轉角之一曲率半徑。
  6. 如申請專利範圍第5項所述之半導體元件，其中該凹槽具有一底部，該底部較該轉角接近該基板；該下表面之該曲率半徑係與該凹槽之該曲率半徑係實質上相等的；或該下表面之該曲率半徑係大於約0.5奈米。
  7. 如申請專利範圍第5項所述之半導體元件，其中該凹槽具有一底部，該底部較該轉角接近該基板；該轉角之該曲率半徑係小於該凹槽之該曲率半徑；或該凹槽具有一底部，該底部較該轉角接近該基板，該凹槽之該底部與該轉角之材料係不同的。
  8. 一種用於形成半導體元件的方法，包含：形成複數半導體鰭片於一半導體基材上；移除該些半導體鰭片之部分以形成複數凹陷；形成一閘極堆疊於該些半導體鰭片之其他部分上，且該些半導體鰭片之該些其他部分係鄰近該些凹陷；形成複數磊晶結構於該些凹陷中，至少直到該些磊晶結構合併且在該些合併之磊晶結構中形成一凹槽為止；以及調整該凹槽之形狀，使得該些合併之磊晶結構中之該形狀調整後之凹槽具有一曲率半徑，且該曲率半徑係大於形狀調整前之該凹槽之曲率半徑。
  9. 如申請專利範圍第8項所述之用於形成半導體元件的方法，其中該調整該凹槽之形狀包含執行一等向性蝕刻製程於該些合併之磊晶結構；其中用於該調整該凹槽之形狀之一蝕刻劑包含過氧化氫(H2O2)；或其中執行該調整該凹槽之形狀，至少直到該凹槽之該曲率半徑係大於約0.5奈米。
  10. 如申請專利範圍第8項所述之用於形成半導體元件的方法，其中該形成該些合併之磊晶結構包含：分別形成複數磊晶層於該些凹陷中；以及分別形成複數覆蓋物於該些磊晶層上，至少直至該些覆蓋物被合併，其中該調整該凹槽之形狀包含移除該些覆蓋物之至少一部分。
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US20200075590A1 (en) 2020-03-05
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US11594534B2 (en) 2023-02-28
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US10636788B2 (en) 2020-04-28
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