WO2013166631A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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Publication number
WO2013166631A1
WO2013166631A1 PCT/CN2012/000912 CN2012000912W WO2013166631A1 WO 2013166631 A1 WO2013166631 A1 WO 2013166631A1 CN 2012000912 W CN2012000912 W CN 2012000912W WO 2013166631 A1 WO2013166631 A1 WO 2013166631A1
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dummy gate
stack structure
gate
source
layer
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PCT/CN2012/000912
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English (en)
French (fr)
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尹海洲
张珂珂
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中国科学院微电子研究所
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Priority to US14/399,260 priority Critical patent/US9530861B2/en
Publication of WO2013166631A1 publication Critical patent/WO2013166631A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device applied to a back gate process. Background technique
  • high-k/metal gate stack structures are commonly used to replace traditional SiO2/polysilicon gate structures.
  • the gate-first process is to fabricate a high-k/metal gate stack structure and then source-drain implant.
  • the gate-gate process first performs source-drain implantation and then forms a high-k/metal gate stack structure.
  • the back gate process does not need to withstand the high temperatures of source-drain annealing and is now gaining industry acceptance.
  • a dummy gate of a silicon-based material such as polysilicon, microcrystalline silicon, or amorphous silicon is usually formed on the substrate, and after etching to form a dummy gate stacked structure, the dummy gate stacked structure is The mask performs source-drain doping implantation, and after depositing the interlayer dielectric layer, the dummy gate stack structure is etched away to leave the gate trenches, and the high-k material and the metal gate material are again deposited in the gate trenches.
  • the dummy gate is the same as the substrate, and is made of a silicon-based material, it is inevitable that the substrate is over-etched during the etching of the dummy gate, resulting in an increase in surface defect density of the substrate channel region, affecting device electrical power. Performance, reliability.
  • a pad oxide layer silicon oxide, high-k material, etc., typically only about 3 nm thick
  • an etch stop layer usually a refractory metal nitride such as TiN, TaN, etc.
  • the pad oxide region and/or the etch stop layer are used to protect the substrate channel region.
  • the pad oxide layer and/or the etch barrier layer are ultra-thin and difficult to be uniformly formed, and it is still possible to cause partial substrate over-etching during etching to form the gate trench.
  • the process of forming such an ultra-thin pad oxide layer and/or etch barrier layer is complicated, expensive, and difficult In order to be suitable for large-scale device manufacturing, it is difficult to effectively improve efficiency and reduce costs. In summary, it is difficult in the prior art to protect the substrate in the gate-last process from being over-etched efficiently and at low cost. Summary of the invention
  • the present invention provides a method of fabricating a semiconductor device, comprising the steps of: forming a dummy gate stack structure on a substrate, wherein the dummy gate stack structure comprises a carbon-based material; and a substrate on both sides of the dummy gate stack structure Forming a source/drain region; etching removes the dummy gate stack structure until the substrate is exposed, leaving a gate trench; forming a gate stack structure in the gate trench.
  • the dummy gate stack structure comprises a dummy gate layer and a dummy gate cap layer, and the dummy gate layer comprises a carbon-based material.
  • the carbon-based material includes an amorphous carbon film and a hydrogenated amorphous carbon film.
  • the method further includes the steps of: depositing an interlayer dielectric layer, planarizing the interlayer dielectric layer until the dummy gate cap layer is exposed, and further planarizing the dummy gate cap Layer until the dummy gate layer is exposed.
  • the step of forming the source and drain regions further includes: forming a first gate spacer on the substrate on both sides of the dummy gate stack structure; performing the first source/drain ion implantation by using the first gate spacer as a mask, Forming a lightly doped source-drain extension region in a substrate on both sides of the dummy gate stack structure; forming a second gate spacer on the first gate sidewall; using the second gate spacer as a mask, performing The second source and drain ions are implanted to form a heavily doped source and drain region.
  • the method further comprises the steps of: forming a metal silicide on the source and drain regions.
  • the dummy gate stack structure is removed by oxygen plasma etching.
  • the oxygen plasma is etched to remove the dummy gate stack structure
  • the HF-based etching solution is used to remove the residual oxide film.
  • the step of forming a gate stack structure further includes: depositing a gate insulating layer in the gate trench; depositing a work function adjusting metal layer on the gate insulating layer; depositing a resistance adjusting metal layer on the work function adjusting metal layer.
  • the method further includes the steps of: forming an interlayer dielectric layer, contacting the etch stop layer; etching the interlayer dielectric layer, and contacting the etch stop layer to form a source drain a contact hole; a source/drain contact plug is formed in the source/drain contact hole; and a lead connected to the source/drain contact plug is formed.
  • a carbon-based material is used in place of the dummy gate of the silicon-based material, and in the gate-gate process, the dummy gate is removed without adding a pad oxide layer and/or an etch barrier layer, thereby ensuring In addition to device reliability, the process is simplified and the cost is reduced.
  • 1 to 14 are schematic cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention
  • Figure 15 is a flow chart showing a method of fabricating a semiconductor device in accordance with the present invention. detailed description
  • 1 to 14 are schematic cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention.
  • a dummy gate stacked structure 2 is formed on the substrate 1.
  • a substrate 1 is provided, such as a silicon-based material, including bulk silicon (Si), silicon-on-insulator (SOI), SiGe, SiC, strained silicon, silicon nanotubes, and the like.
  • bulk silicon or SOI is selected as the substrate 1 for compatibility with a CMOS process.
  • the dummy gate layer 2A and the dummy gate cap layer 2B are sequentially deposited on the substrate 1 by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, MBE, sputtering, or the like.
  • the dummy gate layer 2A is made of a carbon-based material, and the carbon-based material mainly includes an amorphous carbon film (aC) and a hydrogenated amorphous carbon film (aC:H).
  • Amorphous carbon and hydrogenated amorphous carbon films are mainly obtained by methods such as cathode ray deposition, radio frequency sputtering, ion beam deposition, MV PECVD, RFPECVD, HDPCVD, and the like.
  • the subsequent etching for example, dry etching of oxygen plasma
  • the dummy gate layer 2A of the carbon-based material is reacted and removed by etching, and the substrate 1 of the silicon-based material is substantially unreacted or etched.
  • Pseudo gate cover Layer 2B is a material having a higher hardness for protecting and controlling the shape of the dummy gate layer 2A, such as silicon nitride, silicon oxynitride, DLC, etc., but if subsequent lithography/etching control is precise, The dummy gate cap layer 2B may also be omitted, and thus the dummy gate stack structure 2 may substantially include only the dummy gate layer 2A. As shown in FIG. 2, the lithography/etching dummy gate layer 2A and the dummy gate cap layer 2B form a dummy gate stack structure 2.
  • source-drain doping is performed using the dummy gate stacked structure 2 as a mask, and source and drain regions 4 are formed in the substrate 1 on both sides of the dummy gate stacked structure 2.
  • a first dummy gate spacer 3A is formed on the substrate 1 on both sides of the dummy gate stack structure 2, and the material thereof is, for example, silicon dioxide, silicon nitride, silicon oxynitride.
  • DLC due to the higher intrinsic stress of DLC, can additionally increase the carrier mobility in the channel region, increase the device driving capability
  • the dummy gate stack structure 2 and the first dummy gate spacer 3A are used as a mask
  • a first source-drain ion implantation is performed to form a lightly doped source-drain extension region 4A and a hazy doped region (not shown) in the substrate 1 on both sides of the first dummy gate spacer 3A.
  • the type, amount, and energy of the doping ions depend on the type of MOSFET and the junction depth, and will not be described here.
  • the first dummy gate spacer 3A may be omitted in practice, that is, the source-drain extension region 4A is formed by directly implanting the dummy gate stack structure 2 as a mask. As shown in FIG. 4, after deposition and etching, a second dummy gate spacer 3B is formed on the dummy gate stack structure 2 or the first dummy gate spacer 3A, and the material thereof is, for example, silicon dioxide or silicon nitride.
  • the second type of doping ions is the same as the first time, and the dose and energy are larger to form a heavily doped region.
  • a metal silicide 5 is conventionally formed on the source/drain regions 4 by sputtering, MOCVD or the like.
  • a metal layer (not shown) is deposited over the entire device, having a thickness of, for example, 1 to 10 nm, and then annealed at, for example, 450 to 55 (TC, such that the metal layer reacts with Si in the source and drain regions 4 to form a metal silicide 5 for The source-drain resistance of the device is lowered.
  • the metal silicide 5 such as NiSi, NiPtSi, NiCoSi, NiPtCoSi, or the like has a thickness of, for example, 1 to 30 nm.
  • an interlayer dielectric layer (ILD) 6 is deposited on the entire device by a conventional method such as LPCVD, PECVD, HDPCVD, spin coating or the like.
  • the ILD6 material is, for example, silicon oxide or a low-k material, and the low-k material includes, but is not limited to, an organic low-k material (for example, an organic polymer containing an aryl group or a polycyclic ring), an inorganic low-k material (for example, an amorphous carbon-nitrogen film, polycrystalline).
  • porous low-k material for example, disilane trioxane (SSQ)-based porous low-k material, porous silica, porous SiOCH, C-doped silica, F-doped Porous amorphous carbon, porous diamond, porous organic polymer.
  • SSQ disilane trioxane
  • the ILD 6 and the dummy gate cap layer 2B are planarized until the dummy gate layer 2A is exposed.
  • the first CMP is performed to planarize the ILD6 of the low-k material until the dummy gate cap layer 2B of the nitride material is exposed.
  • the CMP slurry, the polishing pad, and the termination conditions are replaced, and the second CMP is performed to planarize the dummy gate cap layer 2B until the dummy gate layer 2A of the carbon-based material is exposed.
  • the dummy gate layer 2A is etched away to form a gate trench 2C.
  • the dummy gate layer 2A of the carbon-based material is removed by dry etching, such as oxygen plasma etching, until the substrate 1 is exposed.
  • the dummy gate layer 2A is the above carbon-based material
  • the amorphous carbon reacts with oxygen to form a carbon dioxide gas
  • the hydrogenated amorphous carbon reacts with oxygen to form carbon dioxide and water vapor, thereby etching and removing
  • the substrate 1 of the silicon-based material is initially reacted to form a silicon oxide to cover the surface of the substrate to block further reactive etching, so that it can be said that the substrate 1 does not substantially participate in the reaction or is substantially not etched.
  • the substrate 1 is substantially not etched, and an oxide film (not shown, having a thickness of, for example, only 1 to 3 nm) can be formed to protect the substrate. 1 . Therefore, in the technical solution of the present invention, it is not necessary to intentionally deposit a pad oxide layer and/or an etch barrier layer before depositing the dummy gate layer 2A, which ensures the reliability of the device and simplifies the process and reduces the cost.
  • the native oxide film in the dry etching process is removed by wet etching using an HF-based etching solution, such as a diluted HF (DHF), sustained-release etching solution. (BOE, a mixed solution of HF and NH 4 F).
  • DHF diluted HF
  • BOE sustained-release etching solution.
  • a gate insulating layer 7A forming a high-k material is deposited in the gate trench 2C.
  • High-k materials include, but are not limited to, nitrides (eg, SiN, A1N, TiN), metal oxides (mainly subgroups and lanthanide metal element oxides such as A1 2 0 3 , Ta 2 0 5 , Ti0 2 , ZnO, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3 , La 2 0 3 ), perovskite phase oxide (for example, PbZrxTi xO; (PZT), Ba x Sr, -x Ti0 3 (BST )).
  • the gate insulating layer 7A may be distributed on the bottom surface of the gate trench 2C as shown in FIG. 11. The thickness of the gate insulating layer 7A is, for example, only about 1 nm.
  • a work function adjusting metal layer 7B is deposited on the gate insulating layer 7A and the ILD 6 in the gate trench 2C.
  • the material of the layer 7B is, for example, TiN or TaN.
  • a resistance adjusting metal layer 7C is deposited on the work function adjusting metal layer 7B.
  • the material of the layer 7C is, for example, Ti, Ta, W, Al, Cu, Mo, or the like.
  • Layers 7A, 7B and 7C together form the final gate stack structure 7 of the MOSFET.
  • the planarization layer 7C is planarized until the ILD6 is exposed, and a contact etch stop layer (CESL) 8 and a second ILD 9 of a SiN material are deposited on the entire device, and the second ILD9, CESL8, and ILD6 are etched to form source/drain contact holes.
  • a contact etch stop layer (CESL) 8 and a second ILD 9 of a SiN material are deposited on the entire device, and the second ILD9, CESL8, and ILD6 are etched to form source/drain contact holes.
  • CSL contact etch stop layer
  • a carbon-based material is used in place of the dummy gate of the silicon-based material, and in the gate-gate process, the dummy gate is removed without adding a pad oxide layer and/or an etch barrier layer, thereby ensuring In addition to device reliability, the process is simplified and the cost is reduced.

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Abstract

一种半导体器件的制造方法，包括步骤：在衬底上形成伪栅极堆叠结构，其中伪栅极堆叠结构包含碳基材料；在伪栅极堆叠结构两侧的衬底中形成源漏区；刻蚀去除伪栅极堆叠结构，直至暴露衬底，留下栅极沟槽；在栅极沟槽中形成栅极堆叠结构。根据该半导体器件制造方法，采用碳基材料替代了硅基材料的伪栅极，在后栅工艺中刻蚀去除伪栅极时无需添加垫氧化层和/或刻蚀阻挡层，在确保器件可靠性之外还简化了工艺，降低了成本。

Description

半导体器件制造方法 优先权要求
本申请要求了 2012年 5月 8日提交的、 申请号为 201210140207.X、 发明名称为 "半导体器件制造方法" 的中国专利申请的优先权， 其全 部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件制造方法， 特别是涉及一种应用于后 栅工艺的半导体器件制造方法。 背景技术
IC 集成度不断增大需要器件尺寸持续按比例缩小， 为解决 MOS 器件不断按比例缩小带来的一系列问题， 一般采用高 K/金属栅堆叠结 构来代替传统的 Si02/多晶硅栅结构。 目前， 制造高 K/金属栅结构半导 体器件主要分为先栅工艺和后栅工艺。 先栅工艺是先制造高 K/金属栅 栈结构再进行源漏注入， 后栅工艺是先进行源漏注入， 再形成高 K/金 属栅栈结构。 后栅工艺不需要经受源漏退火的高温， 目前逐渐获得业 界的认可。
在这种后栅工艺中， 通常是在衬底上形成多晶硅、 微晶硅、 非晶 硅等硅基材质的伪栅极， 刻蚀形成伪栅极堆叠结构之后， 以伪栅极堆 叠结构为掩膜进行源漏掺杂注入， 随后沉积层间介质层之后， 刻蚀去 除伪栅极堆叠结构以留下栅极沟槽， 在栅极沟槽中再次沉积高 k 材料 以及金属栅极材料。 由于上述伪栅极与衬底相同， 均采用硅基材料制 成， 在刻蚀伪栅极过程中难免也会过刻蚀衬底， 造成衬底沟道区表面 缺陷密度增大， 影响器件电学性能、 可靠性。 为此， 必须在衬底上形 成垫氧化层 （氧化硅、 高 k材料等， 厚度通常仅 3nm左右） 和 /或刻蚀 阻挡层（通常为 TiN、 TaN等难熔金属氮化物， 厚度例如仅 lnm左右）， 利用垫氧化层和 /或刻蚀阻挡层来保护衬底沟道区。
然而， 上述垫氧化层和 /或刻蚀阻挡层厚度超薄， 难以均勾形成， 在刻蚀形成栅极沟槽的过程中仍然有可能造成局部衬底过刻蚀。 此外， 形成这种超薄的垫氧化层和 /或刻蚀阻挡层的工艺复杂、 材料昂贵， 难 以适用于大规模器件制造， 难以有效提高效率、 降低成本。 综上所述， 现有技术中难以高效、 低成本地保护后栅工艺中衬底 不被过刻蚀。 发明内容
由上所述， 本发明的目的在于提供一种能高效、 低成本地保护后 栅工艺中衬底不被过刻蚀的半导体器件制造方法。
为此， 本发明提供了一种半导体器件制造方法， 包括步骤： 在衬 底上形成伪栅极堆叠结构， 其中伪栅极堆叠结构包含碳基材料； 在伪 栅极堆叠结构两侧的衬底中形成源漏区； 刻蚀去除伪栅极堆叠结构， 直至暴露衬底， 留下栅极沟槽； 在栅极沟槽中形成栅极堆叠结构。
其中， 伪栅极堆叠结构包括伪栅极层和伪栅极盖层， 伪栅极层包 括碳基材料。
其中， 碳基材料包括非晶碳薄膜、 氢化非晶碳薄膜。
其中， 在形成源漏区之后、 刻蚀去除伪栅极堆叠结构之前， 进一 步包括步骤： 沉积层间介质层， 平坦化层间介质层直至暴露伪栅极盖 层， 进一步平坦化伪栅极盖层直至暴露伪栅极层。
其中， 形成源漏区的步骤进一步包括： 在伪栅极堆叠结构两侧的 衬底上形成第一栅极侧墙； 以第一栅极侧墙为掩膜， 执行第一源漏离 子注入， 在伪栅极堆叠结构两侧的衬底中形成轻掺杂的源漏延伸区； 在第一栅极侧墙上形成第二栅极侧墙； 以第二栅极侧墙为掩膜， 执行 第二源漏离子注入， 形成重掺杂源漏区。
其中， 在形成源漏区之后、 刻蚀去除伪栅极堆叠结构之前， 进一 步包括步骤： 在源漏区上形成金属硅化物。
其中， 采用氧等离子体刻蚀去除伪栅极堆叠结构。 其中， 氧等离 子体刻蚀去除伪栅极堆叠结构之后， 还采用 HF基刻蚀液湿法处理去除 残余的氧化膜。
其中， 形成栅极堆叠结构的步骤进一步包括： 在栅极沟槽中沉积 栅极绝缘层； 在栅极绝缘层上沉积功函数调节金属层； 在功函数调节 金属层上沉积电阻调节金属层。
其中， 形成栅极堆叠结构之后， 进一步包括步骤： 形成层间介质 层、 接触刻蚀停止层； 刻蚀层间介质层、 接触刻蚀停止层形成源漏接 触孔； 在源漏接触孔中填充形成源漏接触塞； 形成与源漏接触塞连接 的引线。
依照本发明的半导体器件制造方法， 采用碳基材料替代了硅基材 料的伪栅极， 在后栅工艺中刻蚀去除伪栅极时无需添加垫氧化层和 /或 刻蚀阻挡层， 在确保器件可靠性之外还简化了工艺、 降低了成本。
附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1至图 14为依照本发明的半导体器件制造方法的各个步骤的剖 面示意图； 以及
图 15为依照本发明的半导体器件制造方法的流程图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果， 公开了可有效简化伪栅极去除的半导体器件制 造方法。 需要指出的是， 类似的附图标记表示类似的结构， 本申请中 所用的术语 "第一" 、 "第二" 、 "上" 、 "下" 等等可用于修饰各 种器件结构或制造工序。 这些修饰除非特别说明并非暗示所修饰器件 结构或制造工序的空间、 次序或层级关系。
图 1至图 14为依照本发明的半导体器件制造方法的各个步骤的剖 面示意图。
参照图 15以及图 1、 图 2 , 在衬底 1上形成伪栅极堆叠结构 2。 提供 衬底 1 , 例如为硅基材料， 包括体硅（ Si )、 绝缘体上硅（ SOI )、 SiGe、 SiC、 应变硅、 硅纳米管等等。 优选地， 选用体硅或 SOI作为衬底 1 , 以 便与 CMOS工艺兼容。 如图 1所示， 在衬底 1上采用 LPCVD、 PECVD、 HDPCVD, ALD、 MBE、 溅射等常规方法依次沉积伪栅极层 2A、 伪栅 极盖层 2B。 伪栅极层 2A材质为碳基材料， 碳基材料主要包括非晶碳薄 膜（a-C ) 以及氢化非晶碳薄膜（a-C:H )。 非晶碳及氢化非晶碳薄膜主 要由阴极射线沉积、 射频溅射、 离子束沉积、 MV PECVD、 RFPECVD、 HDPCVD等方法获得。 在后续的刻蚀 （例如氧等离子体的干法刻蚀） 中， 碳基材质的伪栅极层 2A会反应而刻蚀去除， 而硅基材质的衬底 1 基本不反应也不被刻蚀， 因此这两种不同材质的结构能自动提供良好 的刻蚀选择性， 无需再额外添加垫氧化物和 /或刻蚀阻挡层。 伪栅极盖 层 2B为硬度较高的材料， 用于保护、 控制伪栅极层 2A的形状， 其材质 例如为氮化硅、 氮氧化硅、 DLC等等， 但是如果后续光刻 /刻蚀控制精 准的话， 伪栅极盖层 2B也可以省略， 因此伪栅极堆叠结构 2实质上可以 仅包括伪栅极层 2A。 如图 2所示， 光刻 /刻蚀伪栅极层 2A和伪栅极盖层 2B, 形成了伪栅极堆叠结构 2。
参照图 15以及图 3、 图 4, 以伪栅极堆叠结构 2为掩膜， 执行源漏掺 杂离子注入， 在伪栅极堆叠结构 2两侧的衬底 1中形成源漏区 4。 如图 3 所示， 先沉积后刻蚀， 在伪栅极堆叠结构 2两侧衬底 1上形成第一伪栅 极侧墙 3A, 其材质例如为二氧化硅、 氮化硅、 氮氧化硅、 DLC (由于 DLC具有较高本征应力， 可以额外提高沟道区载流子迁移率， 增大器 件驱动能力）等等；以伪栅极堆叠结构 2以及第一伪栅极侧墙 3A为掩膜， 执行第一次源漏离子注入，在第一伪栅极侧墙 3 A两侧衬底 1中形成轻掺 杂的源漏延伸区 4A以及暈状掺杂区 （未示出） 。 掺杂离子的种类、 剂 量、 能量依照 MOSFET类型以及结深而定， 在此不再赘述。 值得注意的 是， 实际上也可以省略第一伪栅极侧墙 3A, 也即直接以伪栅极堆叠结 构 2为掩膜注入形成源漏延伸区 4A。 如图 4所示， 先沉积后刻蚀， 在伪 栅极堆叠结构 2或第一伪栅极侧墙 3A上形成第二伪栅极侧墙 3B，其材质 例如为二氧化硅、 氮化硅、 氮氧化硅、 DLC等等； 以第二伪栅极侧墙 3B为掩膜， 执行第二次源漏离子注入， 在第二伪栅极侧墙 3B两側的衬 底 1中形成重掺杂的源漏区 4B。 第二次掺杂离子的种类与第一次相同， 剂量、 能量更大从而形成重掺杂区。
优选地， 参照图 15以及图 5 , 在源漏区 4上采用溅射、 MOCVD等常 规形成金属硅化物 5。 在整个器件上沉积金属层 （未示出） ， 厚度例如 l ~ 10nm , 随后在例如 450 ~ 55(TC下退火， 使得金属层与源漏区 4中的 Si反应形成金属硅化物 5 , 用于降低器件的源漏电阻。金属硅化物 5例如 NiSi、 NiPtSi、 NiCoSi、 NiPtCoSi等等, 其厚度例如 l ~ 30nm。
参照图 15 以及图 6 , 在整个器件上采用 LPCVD、 PECVD、 HDPCVD, 旋涂等常规方法沉积层间介质层（ILD ) 6。 ILD6材质例如 为氧化硅或低 k材料， 低 k材料包括但不限于有机低 k材料 （例如含 芳基或者多元环的有机聚合物） 、 无机低 k 材料 （例如无定形碳氮薄 膜、多晶硼氮薄膜、氟硅玻璃）、多孔低 k材料（例如二硅三氧烷（SSQ ) 基多孔低 k材料、 多孔二氧化硅、 多孔 SiOCH、 掺 C二氧化硅、 掺 F 多孔无定形碳、 多孔金刚石、 多孔有机聚合物） 。
参照图 15以及图 7、 图 8, 平坦化 ILD6以及伪栅极盖层 2B, 直 至暴露伪栅极层 2A。 如图 7 所示， 执行第一 CMP, 平坦化处理低 k 材料的 ILD6,直至暴露氮化物材质的伪栅极盖层 2B。随后如图 8所示， 更换 CMP研磨液、 研磨垫以及终止条件， 执行第二 CMP, 平坦化处 理伪栅极盖层 2B, 直至暴露碳基材料的伪栅极层 2A。
参照图 15 以及图 9、 图 10， 刻蚀去除伪栅极层 2A, 形成栅极沟 槽 2C。 如图 9所示， 采用干法刻蚀， 例如氧等离子体刻蚀， 去除碳基 材料的伪栅极层 2A, 直至暴露衬底 1。 由于伪栅极层 2A 为上述碳基 材料， 在氧等离子体刻蚀过程中， 非晶碳会与氧反应形成二氧化碳气 体， 氢化非晶碳会与氧气反应形成二氧化碳和水蒸气， 从而刻蚀去除， 而硅基材质的衬底 1 初步反应形成氧化硅之后就覆盖在衬底 〗 表面从 而阻挡了进一步反应刻蚀， 因此可以说衬底 1 基本不参与反应或者基 本不被刻蚀。 总之， 在刻蚀去除伪栅极层 2A的过程中， 衬底 1基本未 被刻蚀， 并且可以原发的形成氧化物薄膜（未示出， 厚度例如仅为 1 ~ 3nm )从而保护衬底 1 , 因此在本发明的技术方案中无需在沉积伪栅极 层 2A 之前特意沉积形成垫氧化层和 /或刻蚀阻挡层， 确保了器件可靠 性之外还简化了工艺、 降低了成本。 随后， 优选地， 如图 10所示， 采 用 HF基刻蚀液湿法去除上述干法刻蚀过程中原生的氧化物薄膜， HF 基刻蚀液例如稀释 HF ( DHF )、 緩释刻蚀液 （BOE, HF与 NH4F的混 合溶液）。
之后， 参照图 15以及图 1 1至图 14, 与现有的后栅工艺相同或相 似， 完成后续的 MOSFET结构制造。
参照图 1 1，在栅极沟槽 2C中沉积形成高 k材料的栅极绝缘层 7A。 高 k材料包括但不限于氮化物 （例如 SiN、 A1N、 TiN ) 、 金属氧化物 (主要为副族和镧系金属元素氧化物， 例如 A1203、 Ta205、 Ti02、 ZnO、 Zr02、 Hf02、 Ce02、 Y203、 La203 )、钙钛矿相氧化物（例如 PbZrxTi xO; ( PZT ) 、 BaxSr,-xTi03 ( BST ) ) 。 其中， 栅极绝缘层 7A可以如图 1 1 所示分布在栅极沟槽 2C的底面，栅极绝缘层 7A的厚度例如仅为 lnm左 右。
参照图 12 , 在栅极沟槽 2C中的栅极绝缘层 7A以及 ILD6上沉积功函 数调节金属层 7B。 层 7B的材质例如为 TiN、 TaN。 参照图 13， 在功函数调节金属层 7B上沉积电阻调节金属层 7C。 层 7C的材质例如为 Ti、 Ta、 W、 Al、 Cu、 Mo等等。 层 7A、 7B以及 7C共 同构成 MOSFET的最终栅极堆叠结构 7。
参照图 14， 平坦化层 7C直至暴露 ILD6, 在整个器件上沉积例如 SiN 材质的接触刻蚀停止层（ CESL )8以及第二 ILD9,刻蚀第二 ILD9、 CESL8 以及 ILD6形成源漏接触孔， 在源漏接触孔中填充金属和 /或金属氮化物 形成源漏接触塞 10, 沉积第三 ILD1 1并刻蚀形成引线孔， 在引线孔中填 充金属形成引线 12， 构成器件的字线或位线， 完成最终的器件结构。
依照本发明的半导体器件制造方法， 采用碳基材料替代了硅基材 料的伪栅极， 在后栅工艺中刻蚀去除伪栅极时无需添加垫氧化层和 /或 刻蚀阻挡层， 在确保器件可靠性之外还简化了工艺、 降低了成本。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和 等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的 器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种半导体器件制造方法， 包括步骤：
在村底上形成伪栅极堆叠结构， 其中伪栅极堆叠结构包含碳基材 料；
在伪栅极堆叠结构两側的村底中形成源漏区；
刻蚀去除伪栅极堆叠结构， 直至暴露衬底， 留下栅极沟槽； 在栅极沟槽中形成栅极堆叠结构。
2. 如权利要求 1的半导体器件制造方法， 其中， 伪栅极堆叠结构包 括伪栅极层和伪栅极盖层， 伪栅极层包括碳基材料。
3. 如权利要求 2的半导体器件制造方法， 其中， 碳基材料包括非晶 碳薄膜、 氢化非晶碳薄膜。
4. 如权利要求 2的半导体器件制造方法，其中，在形成源漏区之后、 刻蚀去除伪栅极堆叠结构之前， 进一步包括步骤： 沉积层间介质层， 平坦化层间介质层直至暴露伪栅极盖层， 进一步平坦化伪栅极盖层直 至暴露伪栅极层。
5. 如权利要求 1的半导体器件制造方法， 其中， 形成源漏区的步骤 进一步包括：
在伪栅极堆叠结构两侧的村底上形成第一栅极侧墙；
以第一栅极侧墙为掩膜， 执行第一源漏离子注入， 在伪栅极堆叠 结构两侧的衬底中形成轻掺杂的源漏延伸区；
在第一栅极侧墙上形成第二栅极侧墙；
以第二栅极侧墙为掩膜， 执行第二源漏离子注入， 形成重掺杂源 漏区。
6. 如权利要求 1的半导体器件制造方法，其中，在形成源漏区之后、 刻蚀去除伪栅极堆叠结构之前， 进一步包括步骤： 在源漏区上形成金 属硅化物。
7. 如权利要求 1的半导体器件制造方法， 其中， 采用氧等离子体刻 蚀去除伪栅极堆叠结构。
8. 如权利要求 7的半导体器件制造方法， 其中， 氧等离子体刻蚀去 除伪栅极堆叠结构之后， 还采用 HF基刻蚀液湿法处理去除残余的氧化 膜。
9. 如权利要求 1的半导体器件制造方法， 其中， 形成栅极堆叠结构 的步骤进一步包括： 在栅极沟槽中沉积栅极绝缘层； 在栅极绝缘层上 沉积功函数调节金属层； 在功函数调节金属层上沉积电阻调节金属层。
10. 如权利要求 1的半导体器件制造方法， 其中， 形成栅极堆叠结 构之后， 进一步包括步骤： 形成层间介质层、 接触刻蚀停止层； 刻蚀 层间介质层、 接触刻蚀停止层形成源漏接触孔； 在源漏接触孔中填充 形成源漏接触塞； 形成与源漏接触塞连接的引线。
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