CN103730369B - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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CN103730369B
CN103730369B CN201210393669.2A CN201210393669A CN103730369B CN 103730369 B CN103730369 B CN 103730369B CN 201210393669 A CN201210393669 A CN 201210393669A CN 103730369 B CN103730369 B CN 103730369B
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尹海洲
赵治国
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种半导体器件制造方法，包括：在衬底上形成刻蚀停止层和假栅极层；湿法腐蚀假栅极层，形成假栅极图形；在假栅极图形周围形成栅极侧墙；湿法腐蚀去除假栅极图形，留下栅极沟槽；在栅极沟槽中形成栅极堆叠。依照本发明的半导体器件制造方法，利用外延单晶薄膜作为假栅极以及湿法刻蚀假栅极的停止层，在提高栅极剖面形态的垂直度的同时，还能避免底部拐角衬底侵蚀，有效提高器件的性能和可靠性。

Description

半导体器件制造方法
技术领域
本发明涉及一种半导体器件制造方法，更具体地，涉及一种能有效改进栅极剖面的MOSFET制造方法。
背景技术
随着MOSFET等半导体器件尺寸持续等比例缩减，传统的氧化硅栅极绝缘层和掺杂多晶硅的栅极导电层构成的栅极堆叠结构已经无法适用于小尺寸器件。采用高k材料(HK)以降低有效栅氧厚度(EOT)、采用金属栅极(MG)以有效调节栅极功函数，这种HK/MG结构成为目前业界的主流设计。相对于前栅工艺而言，形成假栅极堆叠、沉积层间介质层(ILD)、去除假栅极堆叠留下栅极沟槽、沉积最终HK/MG栅极堆叠的后栅工艺，由于可以更精细控制栅极尺寸并且避免高温效应(例如在激活多晶硅中掺杂剂、或者降低高k材料界面缺陷而退火时使得器件中其他杂质发生迁移等等)，成为HK/MG结构制造的主流方法。
然而，采用例如反应离子刻蚀(RIE)等干法刻蚀去除假栅极堆叠时，由于刻蚀工艺的控制较复杂，例如刻蚀终点的选取、刻蚀速率的调整、刻蚀选择比的选取等等，往往难以获得完全垂直的栅极沟槽，而通常具有倾斜的侧壁，这种倾斜侧壁在稍后沉积金属材料填充栅极时容易造成填充率低、出现孔隙等问题。而采用TMAH湿法腐蚀多晶硅、非晶硅材质的假栅极时，虽然能形成较为垂直的侧壁，但是容易在沟槽底部以及拐角处存在一定量的过刻蚀也即拐角衬底侵蚀，增大了沟道区表面的缺陷，改变了器件的性能。
发明内容
有鉴于此，本发明的目的在于克服上述问题，在提高栅极剖面形态的垂直度的同时，还能避免底部拐角衬底侵蚀，有效提高器件的性能和可靠性。
实现本发明的上述目的，是通过提供一种半导体器件制造方法，包括：在衬底上形成单晶刻蚀停止层和单晶假栅极层；湿法腐蚀假栅极层，形成假栅极图形；在假栅极图形周围形成栅极侧墙；湿法腐蚀去除假栅极图形，留下栅极沟槽；在栅极沟槽中形成栅极堆叠。
其中，采用外延生长形成刻蚀停止层和假栅极层。
其中，刻蚀停止层还向衬底施加应力。
其中，假栅极层为单晶Si，采用TMAH湿法腐蚀。
其中，假栅极图形的侧壁为(111)晶面。
其中，形成假栅极图形之后，形成栅极侧墙之前还包括：在所述假栅极图形两侧，衬底之中形成轻掺杂的源漏扩展区。
其中，形成栅极侧墙之后，湿法腐蚀假栅极层之前进一步包括：在所述栅极侧墙两侧，衬底之中形成重掺杂的源漏区；形成层间介质层，覆盖刻蚀停止层、栅极侧墙和假栅极图形；平坦化层间介质层直至暴露假栅极图形。
其中，刻蚀停止层包括单晶SiGe、Si:C、Si:H、SiGe:C及其组合。
其中，栅极侧墙包括氮化硅、氮氧化硅、类金刚石无定形碳及其组合。
依照本发明的半导体器件制造方法，利用外延单晶薄膜作为假栅极以及湿法刻蚀假栅极的停止层，在提高栅极剖面形态的垂直度的同时，还能避免底部拐角衬底侵蚀，有效提高器件的性能和可靠性。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1至图7为根据本发明的半导体器件制造方法各个步骤的剖视图；以及
图8为根据本发明的半导体器件制造方法的示意流程图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”、“厚”、“薄”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
参照图1，在衬底上形成刻蚀停止层以及假栅极层。提供衬底1，其材质例如是体Si、体Ge、GaAs、SiGe、GeSn、InP、InSb、GaN等等，并且优选体Si(例如单晶Si晶片)。衬底1具有第一晶面，例如为(110)面。随后通过PECVD、HDPCVD、MOCVD、MBE、ALD等方法在衬底1上外延生长刻蚀停止层2，其材质优选为与衬底1晶格常数相近(优选具有至少一种相同的元素，例如均至少包含Si)、但是化学性质有区别的材料以避免增大缺陷同时还能提高刻蚀选择比，例如是SiGe、Si:C、Si:H、SiGe:C等等及其组合。优选地，刻蚀停止层2为单晶材料，以便于减小界面缺陷，提高器件可靠性。特别地，由于刻蚀停止层2与衬底1晶格常数不同，可以向衬底特别是沟道区施加应力以增大载流子迁移率，从而进一步提高器件性能。随后，通过LPCVD、PECVD、HDPCVD、ALD、MBE、热分解等方法在刻蚀停止层2上外延沉积形成假栅极层3，其材质例如是单晶硅、多晶硅、非晶硅、非晶锗、SiGe、Si:C及其组合，并且优选地，假栅极层3与衬底1材质相同而与刻蚀停止层2材质不同，例如均为单晶硅。优选地，假栅极层3也为单晶材料，以便于减小界面缺陷。由于层3、2均为外延生长，其缺陷较之普通CVD、PVD形成的层更小，在稍后的刻蚀中图形的侧面形态会更加垂直。优选地，假栅极层3的晶面与衬底1相同，均为(110)面。
参照图2，湿法刻蚀假栅极层，停止在刻蚀停止层上，形成假栅极图形。在假栅极层3上旋涂光刻胶并曝光、显影形成光刻胶图形(未示出)，随后以此为掩模采用湿法腐蚀假栅极层3形成假栅极图形3P。对于Si材质的假栅极层3而言，采用四甲基氢氧化铵(TMAH)。对于其他材质的假栅极层3，可以采用强酸+强氧化剂的组合来湿法腐蚀，例如硫酸+双氧水。由于在(111)面上TMAH腐蚀速率较低，因此最终腐蚀形成图形3P时会停止在(111)面上，也即假栅极图形3P具有第二晶面。同时，由于TMAH基本不与不同于Si材料的刻蚀停止层2反应，并且因为{111}晶面族中部分晶面与(110)晶面垂直(以下称作(111)面)，形成的栅极图形3P不仅具有完全垂直或者几乎完全垂直(例如侧面与底面之间的夹角角度为90±0.5度)的侧面(晶面为(111))，而且线条粗糙度也较低、底部不会出现拐角侵蚀的问题。此外，也可以在假栅极层3上形成硬掩模层(例如SiN等材质，未示出)，干法刻蚀硬掩模层形成图形，然后湿法腐蚀。值得注意的是，为利用刻蚀停止层的应力作用，提高载流子的迁移率，在本实施例中，刻蚀形成假栅极图形3P之后保留了除刻蚀停止层；在本发明的其他实施例中，刻蚀形成假栅极图形3P之后，继续去除刻蚀停止层直至暴露衬底。
参照图3，在假栅极图形3P侧面形成栅极侧墙。采用传统的方法，例如LPCVD、PECVD、HDPCVD、磁控溅射等方法形成氮化硅、氮氧化硅、类金刚石无定形碳(DLC)及其组合等材质的绝缘介质层，并且光刻/刻蚀而仅在侧面留下栅极侧墙4。优选地，栅极侧墙4具有应力，以进一步提高沟道区载流子迁移率。值得注意的是，实际上可以在图2～图3所示的过程中在假栅极图形3P的两侧衬底1中形成源漏区1S/1D(包括重掺杂区以及轻掺杂的源漏扩展区)，其方法已广为公知，在此不再赘述。
参照图4，在器件上形成层间介质层5。通过旋涂、喷涂、丝网印刷、CVD等方法形成低k材料的层间介质层(ILD)5，其材质包括但是不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、BSG、PSG、BPSG)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)。优选地，采用CVD沉积氧化硅以降低成本。优选地，采用CMP、回刻等方法平坦化ILD 5直至暴露假栅极图形3P。
参照图5，湿法去除假栅极图形3P，留下栅极沟槽3T。与图2所示方法类似，采用TMAH湿法腐蚀去除Si材质的假栅极图形3P，并自动停止在非Si材质的刻蚀停止层2上。由于在(111)面上TMAH腐蚀速率较低，并且假栅极图形3P的侧面为(111)面，因此形成的栅极沟槽3T不仅具有完全垂直或者几乎完全垂直(例如侧面与底面之间的夹角角度为90±0.5度)的侧面。由于TMAH基本不与不同于Si材料的刻蚀停止层2反应，并且因为外延层缺陷密度低，形成的栅极沟槽3T不仅具有完全垂直或者几乎完全垂直(例如侧面与底面之间的夹角角度为90±0.5度)的侧面，而且线条粗糙度也较低、底部不会出现拐角侵蚀的问题。与前面所述原因类似，为利用刻蚀停止层的应力作用，提高载流子的迁移率，在本实施例中，刻蚀假栅极图形3P之后保留了刻蚀停止层；在本发明的其他实施例中，刻蚀假栅极图形3P之后，继续去除刻蚀停止层直至暴露衬底，以形成栅极沟槽3T。
参照图6，在栅极沟槽3T中以及ILD 5上形成栅极绝缘层6、功函数调节层7、以及电阻调节层8。采用PECVD、HDPCVD、MOCVD、MBE、ALD等方式沉积栅极绝缘层6，其材质为氧化硅、氮化硅、氮氧化硅、高k材料及其组合，其中高k材料包括但不限于氮化物(例如SiN、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y203、La203)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))。通过MOCVD、MBE、ALD、蒸发、溅射等方法，在栅极沟槽中栅极绝缘层6上形成Al、TiAl、TiN、TaN材质的功函数调节层7。通过MOCVD、MBE、ALD、蒸发、溅射等方法，在功函数调节层7上形成电阻调节层8，其材质为Cu、Al、Ti、Mo、Ta、W及其组合。
参照图7，平坦化栅极绝缘层6、功函数调节层7、以及电阻调节层8，直至暴露ILD5，构成最终的栅极堆叠结构6/7/8。此后，可以进一步在ILD 5中刻蚀形成源漏接触孔、填充金属形成接触，完成最终器件的布线。
依照本发明的半导体器件制造方法，利用外延单晶薄膜作为假栅极以及湿法刻蚀假栅极的停止层，在提高栅极剖面形态的垂直度的同时，还能避免底部拐角衬底侵蚀，有效提高器件的性能和可靠性。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (9)

1.一种半导体器件制造方法，包括：
在衬底上形成单晶刻蚀停止层和单晶假栅极层；
湿法腐蚀单晶假栅极层，停止在单晶刻蚀停止层上，形成假栅极图形；
在假栅极图形周围形成栅极侧墙；
湿法腐蚀去除假栅极图形，留下栅极沟槽；
在栅极沟槽中形成栅极堆叠。
2.如权利要求1的方法，其中，采用外延生长形成刻蚀停止层和假栅极层。
3.如权利要求1的方法，其中，刻蚀停止层还向衬底施加应力。
4.如权利要求1的方法，其中，假栅极层为单晶Si，采用TMAH湿法腐蚀。
5.如权利要求1的方法，其中，假栅极图形的侧壁为(111)晶面。
6.如权利要求1的方法，其中，形成假栅极图形之后，形成栅极侧墙之前还包括：在所述假栅极图形两侧，衬底之中形成轻掺杂的源漏扩展区。
7.如权利要求1的方法，其中，形成栅极侧墙之后，湿法腐蚀去除假栅极层之前进一步包括：
在所述栅极侧墙两侧，衬底之中形成重掺杂的源漏区；
形成层间介质层，覆盖刻蚀停止层、栅极侧墙和假栅极图形；
平坦化层间介质层直至暴露假栅极图形。
8.如权利要求1的方法，其中，刻蚀停止层包括单晶的SiGe、Si:C、Si:H、SiGe:C或组合。
9.如权利要求1的方法，其中，栅极侧墙包括氮化硅、氮氧化硅、类金刚石无定形碳或组合。
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