CN103531455B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103531455B
CN103531455B CN201210229543.1A CN201210229543A CN103531455B CN 103531455 B CN103531455 B CN 103531455B CN 201210229543 A CN201210229543 A CN 201210229543A CN 103531455 B CN103531455 B CN 103531455B
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CN103531455A (zh
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尹海洲
朱慧珑
张珂珂
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种半导体器件制造方法，包括：在衬底上形成T型伪栅极结构；去除T型伪栅极结构，留下T型栅极沟槽；在T型栅极沟槽中填充金属层，形成T型金属栅极结构。依照本发明的半导体器件制造方法，通过形成T型伪栅极以及T型栅极沟槽，避免了后续金属栅极填充工艺中的悬挂现象以及孔洞形成，提高了器件性能。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法，特别是涉及一种避免在金属栅极中形成孔洞的半导体器件制造方法以及使用该方法制造的半导体器件。
背景技术
随着MOSFET特征尺寸持续等比例缩减，对栅极绝缘隔离效果以及栅极对沟道区控制能力的要求越来越高，传统的氧化硅栅绝缘层在厚度逐渐变薄的情况下已经难以继续提供足够的绝缘隔离，而多晶硅栅极也难以精确控制功函数以调节器件阈值电压。高k材料作为栅极绝缘层、并且金属材料填充作为栅极导电层的高k-金属栅结构已经成为目前MOSFET的主流。由于高k材料特性易在高温或者离子轰击条件下变化，先沉积栅极堆叠结构而后离子注入并激活退火形成源漏区的前栅工艺发展受到限制。先沉积伪栅极堆叠、注入形成源漏区，再刻蚀去除伪栅极形成栅极沟槽、在栅极沟槽中沉积栅极堆叠，这种后栅工艺逐渐占据主导地位。
然而，随着尺寸进一步缩减，小尺寸的器件使得栅极沟槽的深宽比越来越大，后栅工艺中填充栅极沟槽成为制约工艺发展的一个重要瓶颈。正如US2012/012948A1中所公开的，由于栅极沟槽宽度相对于其深度而言过窄，在沉积功函数调节层/金属阻挡层时，该第一层金属材料会在栅极沟槽的上边沿形成“悬挂”，也即在上边沿处第一金属层会形成朝向栅极沟槽中心、超越了栅极侧墙的局部突起。在后续沉积金属填充层时，第二层金属材料会由于该局部突起而在顶部过早闭合、结束沉积填充，相应地在中部和底部形成了未完全填充而引发的孔洞。这些孔洞使得整个金属栅的电阻率不必要地增大，降低了器件的性能。
发明内容
由上所述，本发明的目的在于提供一种能够避免在金属栅极中形成孔洞的半导体器件制造方法以及使用该方法制造的半导体器件。
为此，本发明提供了一种半导体器件制造方法，包括：在衬底上形成T型伪栅极结构；去除T型伪栅极结构，留下T型栅极沟槽；在T型栅极沟槽中填充金属层，形成T型金属栅极结构。
其中，形成T型伪栅极结构的步骤进一步包括：在衬底上形成栅极绝缘层与伪栅极层构成的伪栅极堆叠结构；在伪栅极堆叠结构两侧形成栅极侧墙，栅极侧墙的高度小于伪栅极堆叠结构的高度，从而暴露出伪栅极堆叠结构顶部；在暴露出的伪栅极堆叠结构顶部上以及侧面形成伪栅极外延层，伪栅极外延层与伪栅极层共同构成T型伪栅极结构。
其中，形成伪栅极外延层的同时，在栅极侧墙两侧形成源漏外延层。
其中，形成源漏外延层的同时或者之后，对源漏外延层掺杂形成源漏重掺杂区。
其中，形成栅极侧墙的步骤进一步包括：在衬底以及伪栅极层上形成侧墙材料层；过刻蚀侧墙材料层，使得形成的栅极侧墙的高度小于伪栅极堆叠结构的高度。
其中，在形成伪栅极堆叠结构之后、形成栅极侧墙之前，在伪栅极堆叠结构两侧衬底中形成源漏扩展区和/或晕状源漏区。
其中，形成T型伪栅极结构之后、去除T型伪栅极结构之前，在衬底上形成层间介质层并且平坦化层间介质层直至暴露T型伪栅极结构。
其中，金属层包括功函数调节层与金属栅填充层。
其中，功函数调节层包括TiN、TaN及其组合，金属栅填充层包括Ti、Ta、W、Al、Cu、Mo及其组合。
其中，栅极绝缘层包括高k材料。
其中，伪栅极层包括多晶硅、非晶硅、微晶硅、非晶碳、氢化非晶碳及其组合。
其中，栅极侧墙包括氮化硅、氮氧化硅、DLC及其组合。
其中，T型伪栅极结构的顶部与底部的宽度差不大于栅极侧墙的宽度。
本发明还提供了一种半导体器件，包括衬底、衬底上的高k材料的栅极绝缘层、栅极绝缘层上的T型金属栅极结构、以及T型金属栅极结构两侧的源漏区。
依照本发明的半导体器件制造方法，通过形成T型伪栅极以及T型栅极沟槽，避免了后续金属栅极填充工艺中的悬挂现象以及孔洞形成，提高了器件性能。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1至图9为依照本发明的半导体器件制造方法的各个步骤的剖面示意图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了能够避免在金属栅极中形成孔洞的半导体器件制造方法以及使用该方法制造的半导体器件。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
图1至图9为依照本发明的半导体器件制造方法的各个步骤的剖面示意图。
参照图1，在衬底1上形成伪栅极堆叠结构2，在伪栅极堆叠结构2以及衬底1上形成侧墙材料层3。提供衬底1，例如为硅基材料，包括体硅(Si)、绝缘体上硅(SOI)、SiGe、SiC、应变硅、硅纳米管等等。此外，衬底1也可以是其他半导体材料，例如Ge、GeOl、SiGe、III-V族化合物、II-VI族化合物。优选地，选用体硅或SOI作为衬底1，以便与CMOS工艺兼容。优选地，形成由衬底1对应的氧化材料(例如氧化硅等绝缘材料)构成的隔离区1A，例如在衬底1中通过刻蚀后再沉积填充的工艺形成浅沟槽隔离(STI)1A，STI1A包围并限定出了器件的有源区。如图1所示，在衬底1上(有源区中)采用LPCVD、HDPCVD、ALD、MBE、阴极射线沉积、射频溅射、离子束沉积、MVPECVD、RFPECVD等常规方法依次沉积栅极绝缘层2A、伪栅极层2B，并随后刻蚀形成伪栅极堆叠。栅极绝缘层2A可以是常规的氧化硅，也即作为垫氧化层，在后栅工艺中用于保护衬底沟道区不被过刻蚀，去除伪栅极2B以及栅极绝缘层2A形成栅极沟槽之后再重新填充高k材料形成最终的栅极绝缘层。栅极绝缘层2A也可以是高k材料，形成之后不再去除，而是直接保留作为最终的栅极绝缘层2A。高k材料包括但不限于氮化物(例如SiN、AIN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))。伪栅极层2B为硅基材料或者碳基材料，包括多晶硅、非晶硅、微晶硅、非晶碳、氢化非晶碳及其组合。优选地，伪栅极层2B采用与衬底1同源的材料，也即同为Si基材料，只是晶体形态不同。栅极绝缘层2A与伪栅极层2B的宽度、厚度依照器件性能需要而选定。以伪栅极堆叠2A/2B为掩模，在伪栅极堆叠结构两侧的衬底有源区中进行第一次源漏离子注入，形成轻掺杂的源漏延伸区(LDD)1B和/或晕状(halo)源漏掺杂区1C。掺杂离子的种类、剂量、能量依照MOSFET类型以及结深而定，在此不再赘述。采用LPCVD、HDPCVD、ALD、MBE、阴极射线沉积、射频溅射、离子束沉积、MVPECVD、RFPECVD等常规沉积方法，在整个器件上——也即伪栅极堆叠结构2以及两侧衬底1上形成侧墙材料层3，其材质例如为氮化硅、氮氧化硅、类金刚石无定形碳(DLC)及其组合，提供栅极侧壁绝缘隔离之外还可以优选地施加应力以提高沟道区载流子迁移率。此时，如图1所示，侧墙材料层3覆盖了STI1A、源漏扩展区1B、伪栅极层2B。
如图2所示，刻蚀侧墙材料层3，形成栅极侧墙3A，其中栅极侧墙3A的高度小于伪栅极堆叠结构2的高度。采用等离子体刻蚀、反应离子刻蚀(RIE)等各向异性干法刻蚀工艺和/或各向同性的湿法刻蚀工艺相结合刻蚀侧墙材料层3，并且优选地执行过刻蚀(例如5％～10％)，使得刻蚀得到的栅极侧墙3A的高度小于伪栅极堆叠结构2的高度，也即栅极侧墙3A的顶部低于伪栅极层2B的顶部，从而使得伪栅极层2B顶部的一部分区域(顶部以及侧面)暴露出来，以用于稍后的外延。如图2所示，伪栅极层2B暴露的区域的高度可以是伪栅极层2B高度的1/3以下，优选地为1/4～1/6，以便良好控制外延区域的形状，进一步控制稍后T型伪栅极、T型栅极沟槽的形状。
如图3所示，形成T型伪栅极结构。例如，选择性外延生长，在伪栅极层2B顶部以及源漏扩展区1B顶部分别形成伪栅极外延层2C和源漏外延层1D。对于伪栅极层2B与衬底1(源漏扩展区1B)均为Si基材料的情形，同时在两者顶部选择性外延生长硅材料的伪栅极外延层2C和源漏外延层1D，其中伪栅极外延层2C与伪栅极层2B一同构成T型伪栅极结构以用于避免悬挂现象和孔洞形成，而源漏外延层1D在源漏扩展区1B上构成源漏提升区1D以用于降低源漏接触电阻。当伪栅极层2B与衬底1材质不同时，例如伪栅极层2B为碳基材料而衬底1为硅基材料，可分两次选择性外延生长出材料不同的伪栅极外延层2C和源漏外延层1D，例如伪栅极外延层2C与伪栅极层2B均为非晶碳、氢化非晶碳，源漏外延层1D与衬底1(源漏扩展区1B)均为硅基材料(多晶硅、非晶硅)、锗基材料(多晶锗、非晶锗)或者相同的化合物材料。优选地，为提高源漏区域掺杂浓度降低源漏区域接触电阻，可以在外延生长的同时对于源漏外延层1D施行原位掺杂而获得掺杂浓度更高的源漏重掺杂区1D，或者也可以形成之后执行额外的离子注入工艺来掺杂使得源漏外延区(以及其下方的部分衬底)构成源漏重掺杂区(未示出)。
如图4所示，在整个器件结构上沉积形成层间介质层4。例如通过LPCVD、PECVD、旋涂、喷涂、丝网印刷等方式，形成低k材料的层间介质层(ILD)4，低k材料包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、BSG、PSG、BPSG)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)。优选地，ILD4为氧化硅或者氮氧化硅。
如图5所示，可以采用过刻蚀或者CM P工艺，平坦化ILD4，直至暴露伪栅极层2B。此时，如图5所示，位于伪栅极层2B顶部以上部分的伪栅极外延层2C被去除，而仅留下伪栅极层2B侧面的部分伪栅极外延层2C’，2C’与2B一同构成T型伪栅极结构。T型伪栅极结构顶部与底部之间的宽度差与栅极侧墙3A与伪栅极堆叠结构2的高度差过小时难以抑制悬挂现象，而当该宽度差过大时(例如超过栅极侧墙3A本身宽度)则容易使得最终栅极与源漏区在顶视图中重叠部分过大造成寄生电容增大而降低器件性能。此外，当伪栅极外延层2C’底部与伪栅极层2B底部之间的高度差过大时栅极侧墙3A通常会被腐蚀的过于严重，失去其遮蔽阻挡的作用。因此，优选地，该高度差和/或宽度差不大于栅极侧墙3A的宽度。具体地，前述的高度差和/或宽度差是栅极侧墙3A宽度的0.5～1.0倍。
如图6所示，刻蚀去除T型伪栅极结构2B/2C’，留下T型栅极沟槽2D。可采用湿法或干法可刻蚀去除T型伪栅极结构，只是不同的材料采用不同的溶液或气体。例如，同样是干法刻蚀，对于均是硅基材质的伪栅极外延层2C’与伪栅极层2B构成的T型伪栅极结构，可采用卤素基气体进行刻蚀；对于材质为碳基材料的T型伪栅极结构可采用氧等离子体刻蚀，去除伪栅极而留下栅极沟槽2D。特别地，当栅极绝缘层2A是用作垫氧化层的氧化硅时，可以一并去除栅极绝缘层2A直至暴露衬底1(沟道区)并随后沉积高k材料；而当栅极绝缘层2A本身就是高k材料时，则刻蚀栅极沟槽时停止在栅极绝缘层2A的顶表面上。
如图7所示，在整个器件上形成第一金属层5。例如通过溅射、MOCVD、ALD等方式，在ILD4上以及T型栅极沟槽2D中沉积形成第一金属层5A，用作功函数调节层或者金属阻挡层。第一金属层5A的材质例如是TiN、TaN及其组合，其厚度依照功函数调节需要而选定。值得注意的是，由于T型栅极沟槽的特殊形态，使得沉积第一金属层5A时不会发生悬挂现象。
如图8所示，在第一金属层5A上沉积第二金属层7B。例如通过溅射、MOCVD、ALD等方式，在第一金属层5A上(包括继续填充在栅极沟槽中)形成第二金属层5B以用作金属栅填充层，其材质例如为Ti、Ta、W、Al、Cu、Mo等等及其组合。由于图7所示的第一金属层5A沉积时没有发生悬挂现象，因此第二金属层5B得以顺利完全填充了栅极沟槽的剩余部分，没有在栅极中留下任何孔洞，因此确保了栅极电阻不会增大，最终提高了器件性能。如图8所示，第一金属层5A、第二金属层5B共同构成了与T型栅极沟槽共型的T型金属栅极结构。
最后，如图9所示，完成后续工艺。在整个器件上沉积例如SiN、SiON材质的接触刻蚀停止层(CESL)6，沉积第二ILD7，刻蚀第二ILD7、CESL6以及ILD4形成源漏接触孔，在源漏接触孔中暴露的源漏外延层1D上/中形成金属化层8(例如NiSi、PtSi、CoSi等金属硅化物)以降低源漏接触电阻，填充金属和/或金属氮化物形成源漏接触塞9，沉积第三ILD10并刻蚀形成引线孔，在引线孔中填充金属形成引线11，构成器件的字线或位线，完成最终的器件结构。如图9所示，最终的MOSFET器件结构至少包括衬底1、衬底1上的栅极绝缘层2A、T型金属栅极结构5A/5B、T型金属栅极结构两侧的源漏区(源漏扩展区1B、晕状源漏区1C、源漏外延层1D)、源漏区上的金属化层8。MOSFET其余各个部件结构以及相应的材料在上述方法描述中已经详细列出，在此不再赘述。
依照本发明的半导体器件制造方法，通过形成T型伪栅极以及T型栅极沟槽，避免了后续金属栅极填充工艺中的悬挂现象以及孔洞形成，提高了器件性能。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (12)

1.一种半导体器件制造方法，包括：
在衬底上形成栅极绝缘层与伪栅极层构成的伪栅极堆叠结构；
在伪栅极堆叠结构两侧形成栅极侧墙，栅极侧墙的高度小于伪栅极堆叠结构的高度，从而暴露出伪栅极堆叠结构顶部；
在暴露出的伪栅极堆叠结构顶部上以及侧面形成伪栅极外延层，伪栅极外延层与伪栅极层共同构成T型伪栅极结构；
去除T型伪栅极结构，留下T型栅极沟槽；
在T型栅极沟槽中填充金属层，形成T型金属栅极结构。
2.如权利要求1的方法，其中，形成伪栅极外延层的同时，在栅极侧墙两侧形成源漏外延层。
3.如权利要求2的方法，其中，形成源漏外延层的同时或者之后，对源漏外延层掺杂形成源漏重掺杂区。
4.如权利要求1的方法，其中，形成栅极侧墙的步骤进一步包括：在衬底以及伪栅极层上形成侧墙材料层；过刻蚀侧墙材料层，使得形成的栅极侧墙的高度小于伪栅极堆叠结构的高度。
5.如权利要求1的方法，其中，在形成伪栅极堆叠结构之后、形成栅极侧墙之前，在伪栅极堆叠结构两侧衬底中形成源漏扩展区和/或晕状源漏区。
6.如权利要求1的方法，其中，形成T型伪栅极结构之后、去除T型伪栅极结构之前，在衬底上形成层间介质层并且平坦化层间介质层直至暴露T型伪栅极结构。
7.如权利要求1的方法，其中，金属层包括功函数调节层与金属栅填充层。
8.如权利要求7的方法，其中，功函数调节层包括TiN、TaN及其组合，金属栅填充层包括Ti、Ta、W、Al、Cu、Mo及其组合。
9.如权利要求1的方法，其中，栅极绝缘层包括高k材料。
10.如权利要求1的方法，其中，伪栅极层包括多晶硅、非晶硅、微晶硅、非晶碳、氢化非晶碳及其组合。
11.如权利要求1的方法，其中，栅极侧墙包括氮化硅、氮氧化硅、DLC及其组合。
12.如权利要求1的方法，其中，T型伪栅极结构的顶部与底部的宽度差不大于栅极侧墙的宽度。
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CN102437041A (zh) * 2011-11-29 2012-05-02 上海华力微电子有限公司 一种形成高阶电常数k和t型金属栅极的形成方法
CN102427033A (zh) * 2011-12-02 2012-04-25 上海华力微电子有限公司 一种形成高阶电常数k和t型金属栅极的形成方法

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