CN105489652B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN105489652B
CN105489652B CN201410484648.0A CN201410484648A CN105489652B CN 105489652 B CN105489652 B CN 105489652B CN 201410484648 A CN201410484648 A CN 201410484648A CN 105489652 B CN105489652 B CN 105489652B
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grid
layer
polycrystalline
source
fin
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CN105489652A (zh
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殷华湘
张永奎
赵治国
陆智勇
朱慧珑
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Ruili Flat Core Microelectronics Guangzhou Co Ltd
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Institute of Microelectronics of CAS
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Abstract

一种半导体器件，包括：多个鳍片结构，在衬底上沿第一方向延伸；栅极堆叠结构，在衬底上沿第二方向延伸，跨越多个鳍片结构，其中栅极堆叠结构包括栅极导电层和栅极绝缘层，栅极导电层由掺杂的多晶半导体构成；沟道区，多个鳍片结构中位于栅极堆叠结构下方；源漏区，在多个鳍片结构上、位于栅极堆叠结构沿第一方向两侧。依照本发明的半导体器件及其制造方法，在后栅工艺中对多晶半导体栅极掺杂后与两侧源漏区同步执行退火以驱动掺杂剂均匀分布，能有效提高对于掺杂多晶半导体栅极调节阈值电压的精度，以低成本抑制短沟道效应。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法，特别是涉及一种掺杂多晶硅后栅工艺的FinFET及其制造方法。
背景技术
在当前的亚20nm技术中，三维多栅器件(FinFET或Tri--gate)是主要的器件结构，这种结构增强了栅极控制能力、抑制了漏电与短沟道效应。
例如，双栅SOI结构的MOSFET与传统的单栅体Si或者SOI MOSFET相比，能够抑制短沟道效应(SCE)以及漏致感应势垒降低(DIBL)效应，具有更低的结电容，能够实现沟道轻掺杂，可以通过设置金属栅极的功函数来调节阈值电压，能够得到约2倍的驱动电流，降低了对于有效栅氧厚度(EOT)的要求。而三栅器件与双栅器件相比，栅极包围了沟道区顶面以及两个侧面，栅极控制能力更强。进一步地，全环绕纳米线多栅器件更具有优势。
通常，一种FinFET结构以及制造方法包括：在体Si或者SOI衬底中刻蚀形成多个平行的沿第一方向延伸的鳍片和沟槽；在沟槽中填充绝缘材料，回刻以露出部分鳍片，形成浅沟槽隔离(STI)；在鳍片顶部以及侧壁沉积通常为氧化硅的较薄(例如仅1～5nm)假栅极绝缘层，在假栅极绝缘层上沉积通常为多晶硅、非晶硅的假栅极层以及氮化硅的假栅极盖层；刻蚀假栅极层和假栅极绝缘层，形成沿第二方向延伸的假栅极堆叠，其中第二方向优选地垂直于第一方向；以假栅极堆叠为掩模，对鳍片进行倾斜的浅掺杂注入形成轻掺杂漏结构(LDD)特别是源漏延伸(SDE)结构以抑制漏致感应势垒降低效应；在假栅极堆叠的沿第一方向的两侧沉积并刻蚀形成栅极侧墙；在栅极侧墙两侧外延生长晶格常数相近材料形成高应力的源漏区(由于栅极侧墙、假栅极堆叠顶部等为绝缘介电质材质，无法在其上外延生长半导体材料)，优选采用SiGe、SiC等高于Si应力的材料以提高载流子迁移率；优选地，在源漏区上形成接触刻蚀停止层(CESL)；在晶片上沉积层间介质层(ILD)；刻蚀去除假栅极堆叠，在ILD中留下栅极沟槽；在栅极沟槽中沉积高k材料(HK)的栅极绝缘层以及金属/金属合金/金属氮化物(MG)的栅极导电层，并优选包括氮化物材质的栅极盖层以保护金属栅极。进一步地，利用掩模刻蚀ILD形成源漏接触孔，暴露源漏区；可选地，为了降低源漏接触电阻，在源漏接触孔中形成金属硅化物。填充金属/金属氮化物形成接触塞，通常优选填充率较高的金属W、Ti。由于CESL、栅极侧墙的存在，填充的金属W、Ti会自动对准源漏区，最终形成接触塞。
然而，上述金属栅极和高k材料构成的栅极堆叠结构，虽然能够有效提高栅极控制能力，例如有效抑制短沟道效应并且精确调节阈值电压，但是随着FinFET器件特征尺寸(沟道区长度，通常稍大于或者等于金属栅极堆叠沿第一方向的长度/宽度)持续缩减至例如10nm乃至8nm以下，如何有效提高金属材料填充后栅工艺形成的栅极沟槽成为难题，工艺复杂性使得制造成本高居难下。而另一方面，传统的应用于平面大尺寸MOSFET的多晶硅栅极结构难以应用于后栅工艺的FinFET，因为对于短沟道、短栅长器件而言难以精确控制窄栅极内部的掺杂剂分布均匀，如此形成的多晶硅栅极面临短沟道效应控制困难、阈值电压调节难以精确等等技术挑战。
发明内容
由上所述，本发明的目的在于克服上述技术困难，提出一种新的FinFET结构及其制造方法，能有效提高对于掺杂多晶半导体栅极调节阈值电压的精度，以低成本抑制短沟道效应。
为此，本发明提供了一种半导体器件，包括：多个鳍片结构，在衬底上沿第一方向延伸；栅极堆叠结构，在衬底上沿第二方向延伸，跨越多个鳍片结构，其中栅极堆叠结构包括栅极导电层和栅极绝缘层，栅极导电层由掺杂的多晶半导体构成；沟道区，多个鳍片结构中位于栅极堆叠结构下方；源漏区，在多个鳍片结构上、位于栅极堆叠结构沿第一方向两侧。
其中，多晶半导体选自多晶Si、多晶SiGe、多晶Si:C、多晶Si:H、多晶Ge、多晶SiGeC、多晶GeSn、多晶SiSn、多晶InP、多晶GaN、多晶InSb、多晶碳化半导体的任意一种或其组合。
其中，源漏区包括在多个鳍片结构中的源漏延伸区、以及在源漏延伸区上方的抬升源漏区。
其中，多个鳍片结构中部和/或底部具有穿通阻挡层。
其中，对于pFinFET器件而言，多晶半导体中的杂质为p型杂质，选自B、In、Ga、Al、Mg、Sn的任一种及其组合；对于nFinFET器件而言，多晶半导体中的杂质为n型杂质，选自P、As、Te、Se、Sb、S的任一种及其组合。
本发明还提供了一种半导体器件制造方法，包括：在衬底上形成沿第一方向延伸的多个鳍片；在鳍片上形成沿第二方向延伸的假栅极堆叠结构；在假栅极堆叠结构沿第一方向两侧的鳍片中和/或上形成掺杂的源漏区，假栅极堆叠结构下方的、源漏区之间的鳍片部分构成沟道区；在衬底上形成层间介质层，选择性刻蚀去除假栅极堆叠结构，在层间介质层中留下栅极沟槽；在栅极沟槽中以及层间介质层顶面上依次沉积栅极绝缘层以及多晶半导体层；对多晶半导体层掺杂，以掺杂的多晶半导体层作为栅极导电层；执行激活退火，同时激活了源漏区以及栅极导电层中的掺杂剂，促使掺杂剂在栅极导电层中均匀分布。
其中，形成栅极堆叠结构之前进一步包括，执行离子注入，在鳍片中部和/或底部形成穿通阻挡层。
其中，多晶半导体选自多晶Si、多晶SiGe、多晶Si:C、多晶Si:H、多晶Ge、多晶SiGeC、多晶GeSn、多晶SiSn、多晶InP、多晶GaN、多晶InSb、多晶碳化半导体的任意一种或其组合。
其中，形成源漏区的步骤具体包括：在假栅极堆叠结构两侧形成第一栅极侧墙；以第一栅极侧墙为掩模对鳍片执行轻掺杂离子注入，形成源漏延伸区；在第一栅极侧墙两侧的源漏延伸区上外延生长抬升源漏区；在第一栅极侧墙两侧形成第二栅极侧墙；以第二栅极侧墙为掩模对抬升源漏区执行重掺杂离子注入。
其中，轻掺杂离子注入为倾斜离子注入，调整倾斜角以控制源漏延伸区的结深。
其中，激活退火之后，平坦化栅极导电层和栅极绝缘层，直至暴露层间介质层。
其中，对于pFinFET器件而言，多晶半导体中的杂质为p型杂质，选自B、In、Ga、Al、Mg、Sn的任一种及其组合；对于nFinFET器件而言，多晶半导体中的杂质为n型杂质，选自P、As、Te、Se、Sb、S的任一种及其组合。
依照本发明的半导体器件及其制造方法，在后栅工艺中对多晶半导体栅极掺杂后与两侧源漏区同步执行退火以驱动掺杂剂均匀分布，能有效提高对于掺杂多晶半导体栅极调节阈值电压的精度，以低成本抑制短沟道效应。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1至图13为依照本发明的FinFET制造方法各步骤的示意图；以及
图14为依照本发明的FinFET器件结构透视图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了有效提高多晶半导体栅极阈值电压控制精度的三维多栅FinFET及其制造方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
值得注意的是，以下各个附图中上部部分为器件沿图14中第一方向(鳍片延伸方向，源漏延伸方向，也即Y--Y’轴线)的剖视图，中间部分为器件沿第二方向(栅极堆叠延伸方向，垂直于第一方向，也即X--X’轴线)的栅极堆叠中线的剖视图，下部部分为器件沿平行于第二方向且位于栅极堆叠之外(第一方向上具有一定距离)位置处(也即X1--X1’轴线)获得的剖视图。
如图1所示，在衬底1上形成沿第一方向延伸的多个鳍片结构1F以及鳍片结构之间的沟槽1G，其中第一方向为未来器件沟道区延伸方向(图14中的Y--Y’轴线)。提供衬底1，衬底1依照器件用途需要而合理选择，可包括单晶体硅(Si)、单晶体锗(Ge)、应变硅(StrainedSi)、锗硅(SiGe)，或是化合物半导体材料，例如氮化镓(GaN)、砷化镓(GaAs)、磷化铟(InP)、锑化铟(InSb)，以及碳基半导体例如石墨烯、SiC、碳纳管等等。出于与CMOS工艺兼容的考虑，衬底1优选地为体Si。任选的，在衬底1上形成硬掩模层2，例如通过LPCVD、PECVD、溅射等工艺形成的氮化硅、氮氧化硅层2。在硬掩模层2上涂覆光刻胶并曝光显影形成光刻胶图形(未示出)，以光刻胶图形为掩模，刻蚀硬掩模层2形成硬掩模图形，并且进一步以硬掩模图形2为掩模刻蚀衬底1，在衬底1中形成多个沿第一方向平行分布的沟槽1G以及沟槽1G之间剩余的衬底1材料所构成的鳍片1F。刻蚀优选各向异性的刻蚀，例如等离子体干法刻蚀、反应离子刻蚀(RIE)或者四甲基氢氧化铵(TMAH)湿法腐蚀，使得沟槽1G的深宽比优选地大于5:1。鳍片1F沿第二方向的宽度例如仅为5～50nm并优选10～20nm。
如图2所示，在鳍片结构1F和衬底1上形成隔离介质层3。例如，在鳍片1F之间的沟槽1G中通过PECVD、HDPCVD、RTO(快速热氧化)、旋涂、FlowCVD等工艺沉积填充材质例如为氧化硅、氮氧化硅、氢氧化硅、有机物等的绝缘隔离介质层3。如图2所示，由于鳍片结构1F的存在，沉积的层3在鳍片结构1F顶部具有凸起。优选地，采用CMP、回刻(etch--back)等平坦化工艺处理层3，直至暴露硬掩模层2。
如图3所示，在鳍片1F中和/或底部形成穿通阻挡层(PTSL)4。在图2所示结构平坦化露出硬掩模层2之后，执行离子注入，可以包括N、C、F、P、Cl、As、B、In、Sb、Ga、Si、Ge等及其组合。随后执行退火，例如在500～1200摄氏度下热处理1ms～10min，使得注入的元素与鳍片1F反应，形成高掺杂的(掺杂上述材料的Si)或者绝缘材料的(例如掺杂有上述元素的氧化硅)的穿通阻挡层4。在本发明一个实施例中，控制注入能量和剂量，仅在鳍片1F中形成了沟道穿通阻挡层4A，如图3所示，以抑制沟道区通过STI侧面的泄漏。然而，在本发明另一优选实施例中，控制注入能量和剂量，使得穿通阻挡层4还分布在鳍片1F底部与衬底1界面处作为STI穿通阻挡层4B，以有效隔绝鳍片1F中沟道区、源漏区与相邻鳍片有源区之间的泄漏电流。层4B材质可以与层4A材质相同，也可以包含上述元素中的不同组分(但至少包含氧)。层4B可以与层4A同时一次性注入形成(不同元素注入深度不同)，也可以先后两次不同深度、剂量的注入，例如可以先深距离注入形成层4B，后浅距离注入形成层4A，反之亦然。此外，除了上述高掺杂的穿通阻挡层之外，也可以注入大量的氧(O)以形成氧化硅基的绝缘层以作为穿通阻挡层(该氧化硅层内也可以进一步掺杂上述杂质)。值得注意的是，沟道穿通阻挡层4A距离鳍片1F顶部(或底部)的高度可以任意设定，在本发明一个实施例中优选为鳍片1F自身高度的1/3～1/2。STI穿通阻挡层4B和沟道穿通阻挡层4A厚度例如是5～30nm。层4A的宽度(沿第一和/或第二方向)依照整个器件有源区宽度而设定，层4A的宽度则与鳍片1F相同，也即层4B的宽度明显大于层4A的宽度。
如图4所示，选择性刻蚀隔离层3，再次形成沟槽1G，暴露出鳍片1F一部分。可以采用光刻胶图形或者其他硬掩模图形，选择各向异性的刻蚀方法，例如等离子体干法刻蚀、RIE，刻蚀隔离层3，使得剩余的隔离层3构成了浅沟槽隔离(STI)3。优选地，沟槽1G的深度，也即STI 3顶部距离鳍片1F顶部的距离，大于等于沟道穿通阻挡层4A顶部距离鳍片1F顶部的距离，以便完全抑制沟道区之间的穿通。随后，湿法腐蚀去除了硬掩模2。
如图5所示，在整个晶片上、也即在鳍片1F、STI 3上形成假绝缘层5A、以及假栅极层5B。例如通过PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等常规工艺，在整个器件结构上形成假绝缘层5A以及假栅极层5B。假绝缘层5A的材质可以是氧化物、氮化物、氮氧化物。假栅极层5B的材质包括多晶硅、SiGe、非晶硅、非晶碳等。随后例如在整个器件上涂覆光刻胶(未示出)，利用含有沿第二方向(优选垂至于鳍片1F延伸的第一方向)分布线条的掩模或者刻线板对光刻胶曝光、显影而形成多个沿第二方向延伸分布的光刻胶图形，随后以光刻胶图形为掩模依次刻蚀假栅极层5B、假绝缘层5A，直至暴露鳍片结构1F顶部以及STI 3的顶部。刻蚀工艺优选各向异性的刻蚀工艺，例如等离子干法刻蚀、RIE等，刻蚀气体可以为针对硅基材质(如多晶硅、氧化硅、氮化硅等)的碳氟基刻蚀气体，也可以为针对非硅基材质(例如多晶SiGe、多晶Ge、其他高k材料)的卤素刻蚀气体(例如Cl2、Br2、HBr、HCl等)，形成沿第二方向延伸的线条，并且如图5下部所示重新露出了鳍片1F之间的沟槽1G。
如图6所示，在假栅极堆叠5沿第一方向的两侧形成第一栅极侧墙6A。在整个器件上通过LPCVD、PECVD、HDPCVD、UHVCVD、MOCVD、MBE、ALD、蒸发、(磁控)溅射等工艺形成绝缘材料层6，其材质例如氮化硅、氮氧化硅、氧化硅、含碳氧化硅、非晶碳、类金刚石无定形碳(DLC)等及其组合。在本发明一个实施例中，优选氮化硅。随后，采用各向异性刻蚀工艺，刻蚀绝缘材料层6，仅在假栅极堆叠结构5沿第一方向的两侧留下第一栅极侧墙6A。值得注意的是，虽然图6所示第一栅极侧墙6A为三角形，但是在本发明另一优选实施例中，侧墙6A优选具有L型，也即具有水平的第一部分以及垂直的第二部分，以便与栅极堆叠5保持良好的共形，从而利于减薄栅极侧墙6A的厚度，以进一步缩减器件尺寸、提高器件均匀度。在本发明一个优选实施例中，层6A的厚度例如仅1～5nm、优选2～4nm、并最佳为3nm。
如图7所示，以第一栅极侧墙6A为掩模，对包含器件的晶片执行轻掺杂离子注入，在假栅极堆叠5和栅极侧墙6A沿第一方向的两侧鳍片1F中形成了轻掺杂源漏(LDD)或者源漏延伸区(SDE)结构1LS/1LD，两者之间的鳍片1F构成了沟道区1C。其中，垂直倾角β(注入方向与垂直方向所夹的锐角角度)可以例如0～45±0..5度)。可以通过以垂直方向为轴线，180度旋转晶片衬底1或者旋转离子注入腔室中喷嘴而实现在栅极堆叠结构5沿第一方向两侧形成对称的LDD/SDE结构。此外，依照本发明的优选实施例，可以调整垂直倾角β以调整LDD/SDE结构的纵向(沿垂直方向)结深，从而控制源漏区与鳍片1F之间底部界面特性。
如图8所示，在栅极侧墙6A沿第一方向两侧的LDD源漏区1LS/1LD上外延生长抬升源漏区1HS和1HD。例如通过PECVD、MOCVD、MBE、ALD、热分解、蒸发、溅射等工艺，在栅极堆叠结构5/栅极侧墙6A沿第一方向的两侧上方外延生长抬升漏区1HD和提升源区1HS。其中，抬升源漏区1HS/1HD材质优选与衬底1、鳍片1F不同，例如具有更高应力的SiGe、Si:C、Si:H、SiSn、GeSn、SiGe:C等及其组合。如图8下部所示，由于外延生长在各个晶面生长速度不一致，最后外延形成的抬升源漏区往往具有菱形、钻石形等剖面。优选地，形成抬升源漏区之后，进一步在第一栅极侧墙6A上采用类似工艺和材质形成第二栅极侧墙6B，并且利用第二栅极侧墙6B为掩膜，通过离子注入对抬升源漏区掺杂以降低源漏区接触电阻。值得注意的是，抬升源漏区掺杂之后，并不立即执行激活退火工艺，而是等待后续对多晶半导体栅极掺杂完成后同步执行掺杂剂激活以节省工艺，并且同时驱动注入离子在多晶半导体栅极中的均匀分布。
如图9所示，在整个器件上形成接触刻蚀停止层(CESL)7A以及层间介质层(ILD)7B。优选地，先在器件上通过PECVD、HDPCVD、溅射等工艺形成氮化硅的接触刻蚀停止层7A(可以省略)。随后，通过旋涂、喷涂、丝网印刷、CVD、PVD等工艺形成氧化硅、低k材料的ILD7B，其中低k材料包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、BSG、PSG、BPSG)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)。
如图10所示，选择性刻蚀去除假栅极堆叠结构5A/5B，直至露出鳍片1F中的沟道区1C，在ILD 7B中留下了栅极开口7C。可以针对假栅极堆叠的材料选择合适的各向异性刻蚀工艺，例如TMAH湿法工艺针对性去除多晶硅、非晶硅，或者氧等离子干法刻蚀去除非晶碳，碳氟基刻蚀气体的等离子干法刻蚀去除假栅极绝缘层等等。
如图11所示，在整个器件结构之上沉积高K材质的栅极绝缘层8A、以及多晶半导体材质的栅极导电层8B，完全填充了栅极开口7C，并且覆盖了ILD 7B的顶表面。沉积工艺例如PECVD、HDPCVD、MOCVD、MBE、ALD等台阶覆盖率高的沉积工艺。栅极绝缘层8A的高k材质包括但不限于包括选自HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOx的铪基材料(其中，各材料依照多元金属组分配比以及化学价不同，氧原子含量x可合理调整，例如可为1～6且不限于整数)，或是包括选自ZrO2、La2O3、LaAlO3、TiO2、Y2O3的稀土基高K介质材料，或是包括Al2O3，以其上述材料的复合层。多晶半导体层8B的材质包括多晶Si、多晶SiGe、多晶Si:C、多晶Si:H、多晶Ge、多晶SiGeC、多晶GeSn、多晶SiSn、多晶InP、多晶GaN、多晶InSb、多晶碳化半导体等。可以选择工艺参数，例如提高沉积温度(例如850～1300摄氏度)使得一次形成上述材料的多晶半导体层；也可以先在较低温度下(例如600～800摄氏度)下先形成上述材料的非晶、微晶半导体层，然后采用激光退火、RTA退火等修复工艺使得半导体层中的晶粒重新组合形成多晶半导体层。值得注意的是，如图11下部所示，至少多晶半导体层8B覆盖了ILD 7B的顶部，如此增大了多晶半导体的总体积，便于在后续掺杂、退火时利用较大的扩散空间来消除局部(例如小尺寸栅极区域)掺杂方向和/或浓度的不均匀性。
如图12所示，对多晶半导体层8B进行掺杂，形成掺杂多晶半导体层8B’。在本发明一个优选实施例中，可以采用离子注入，依据不同的器件类型对多晶半导体栅极掺入不同的掺杂剂以调节所需的阈值电压，例如对于pFinFET器件而言，多晶半导体中的杂质为p型杂质，选自B、In、Ga、Al、Mg、Sn的任一种及其组合；对于nFinFET器件而言，多晶半导体中的杂质为n型杂质，选自P、As、Te、Se、Sb、S的任一种及其组合。。随后，优选地对整个器件执行退火(例如退火温度600～800摄氏度，退火时间1s～3min)，激活杂质并且促使其在整个多晶半导体层8B中均匀分布，而形成了掺杂多晶半导体层8B’以用作栅极导电层。此时，抬升源漏区1HS/1HD中的掺杂剂也一并受到高温退火的驱动而重新分布，获得了所需的结深以及浓度分布。与此同时，该退火还进一步减缓了LDD/SDE的轻掺杂注入以及抬升源漏区的重掺杂注入对于鳍片结构顶部的损伤以及减少外延层中的缺陷，有利于以精简的工艺提高器件的可靠性。值得注意的是，在此过程中，相对于传统工艺中先形成栅极线条然后再掺杂、退火的工艺，本发明的器件及其制造方法利用大面积注入然后激活退火，避免了因为离子注入方向的不均匀分布或者等离子点火喷射系统的偶然波动给小尺寸栅极线条带来的掺杂浓度局部巨大跃变，也通过大面积、长距离的扩散提高了掺杂层8B’内掺杂剂分布的均匀性，有助于精确控制器件的阈值电压，在晶片的不同区域内均可以获得稳定、均一化的电学特性。
最后，如图13所示，采用CMP或者回刻蚀(etch--back)等平坦化工艺处理层8B、层8A直至暴露ILD 7B。之后可以采用常规工艺完成器件互连。例如，依次刻蚀ILD 7B、接触刻蚀停止层7A，直至暴露源漏区1HS/1HD，形成接触孔。刻蚀方法优选各向异性的干法刻蚀，例如等离子干法刻蚀或者RIE。优选地，在接触孔暴露的源漏区上形成金属硅化物(未示出)以降低接触电阻。例如，在接触孔中蒸发、溅射、MOCVD、MBE、ALD形成金属层(未示出)，其材质例如Ni、Pt、Co、Ti、W等金属以及金属合金。在250～1000摄氏度下退火1ms～10min，使得金属或金属合金与源漏区中所含的Si元素反应形成金属硅化物，以降低接触电阻。随后在接触孔中填充接触金属层，例如通过MOCVD、MBE、ALD、蒸发、溅射等工艺，形成了接触金属层，其材料优选延展性较好、填充率较高并且相对低成本的材料，例如包括W、Ti、Pt、Ta、Mo、Cu、Al、Ag、Au等金属、这些金属的合金、以及这些金属的相应氮化物。随后，采用CMP、回刻等工艺平坦化接触金属层，直至暴露CESL层7A。
最后形成的器件结构如图13所示，包括：多个鳍片结构1F，在衬底1上沿第一方向延伸分布，多个鳍片结构1F之间存在多个浅沟槽隔离(STI)3；栅极堆叠结构包括栅极导电层8B’以及栅极绝缘层8A，跨越每个鳍片结构，沿第二方向延伸分布，栅极堆叠结构8下方的鳍片结构构成沟道区1C；源漏区，形成在栅极堆叠沿第一方向两侧的鳍片结构之上；其中，栅极导电层8B’由掺杂多晶半导体构成。其他的器件结构和材料、参数等已经参照附图1至附图13描述在制造过程中，在此不再赘述。
依照本发明的半导体器件及其制造方法，在后栅工艺中对多晶半导体栅极掺杂后与两侧源漏区同步执行退火以驱动掺杂剂均匀分布，能有效提高对于掺杂多晶半导体栅极调节阈值电压的精度，以低成本抑制短沟道效应。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (7)

1.一种半导体器件制造方法，包括：
在衬底上形成沿第一方向延伸的多个鳍片；
在鳍片上形成沿第二方向延伸的假栅极堆叠结构；
在假栅极堆叠结构沿第一方向两侧的鳍片中和/或上形成掺杂的源漏区，假栅极堆叠结构下方的、源漏区之间的鳍片部分构成沟道区；
在衬底上形成层间介质层，选择性刻蚀去除假栅极堆叠结构，在层间介质层中留下栅极沟槽；
在栅极沟槽中以及层间介质层顶面上依次沉积栅极绝缘层以及多晶半导体层；
对多晶半导体层掺杂，以掺杂的多晶半导体层作为栅极导电层；
执行激活退火，同时激活了源漏区以及栅极导电层中的掺杂剂，促使掺杂剂在栅极导电层中均匀分布。
2.如权利要求1的半导体器件制造方法，其中，形成栅极堆叠结构之前进一步包括，执行离子注入，在鳍片中部和/或底部形成穿通阻挡层。
3.如权利要求1的半导体器件制造方法，其中，多晶半导体选自多晶Si、多晶SiGe、多晶Si:C、多晶Si:H、多晶Ge、多晶SiGeC、多晶GeSn、多晶SiSn、多晶InP、多晶GaN、多晶InSb、多晶碳化半导体的任意一种或其组合。
4.如权利要求1的半导体器件制造方法，其中，形成源漏区的步骤具体包括：在假栅极堆叠结构两侧形成第一栅极侧墙；以第一栅极侧墙为掩模对鳍片执行轻掺杂离子注入，形成源漏延伸区；在第一栅极侧墙两侧的源漏延伸区上外延生长抬升源漏区；在第一栅极侧墙两侧形成第二栅极侧墙；以第二栅极侧墙为掩模对抬升源漏区执行重掺杂离子注入。
5.如权利要求4的半导体器件制造方法，其中，轻掺杂离子注入为倾斜离子注入，调整倾斜角以控制源漏延伸区的结深。
6.如权利要求1的半导体器件制造方法，其中，激活退火之后，平坦化栅极导电层和栅极绝缘层，直至暴露层间介质层。
7.如权利要求1的半导体器件制造方法，其中，对于pFinFET器件而言，多晶半导体中的杂质为p型杂质，选自B、In、Ga、Al、Mg、Sn的任一种及其组合；对于nFinFET器件而言，多晶半导体中的杂质为n型杂质，选自P、As、Te、Se、Sb、S的任一种及其组合。
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