CN111863963A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN111863963A
CN111863963A CN201910336097.6A CN201910336097A CN111863963A CN 111863963 A CN111863963 A CN 111863963A CN 201910336097 A CN201910336097 A CN 201910336097A CN 111863963 A CN111863963 A CN 111863963A
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side wall
forming
semiconductor device
substrate
interlayer dielectric
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910336097.6A priority Critical patent/CN111863963A/zh
Priority to US16/857,447 priority patent/US11569131B2/en
Publication of CN111863963A publication Critical patent/CN111863963A/zh
Priority to US18/085,210 priority patent/US20230118901A1/en
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Abstract

本发明提供一种半导体器件及其形成方法，包括步骤：提供衬底，所述衬底上形成有若干分隔排列的鳍部；在所述衬底上形成伪栅结构，且所述伪栅结构横跨所述鳍部；在所述伪栅结构的侧壁上形成第一侧墙；在所述衬底上形成上形成层间介电层，且所述层间介电层的顶部低于所述第一侧墙的顶部；在所述层间介电层上、所述第一侧墙的侧壁上形成第二侧墙；本发明由于所述第二侧墙的存在，增大了后续形成的金属栅极结构到导电插塞之间的距离，从而能够减少金属栅极结构之间的寄生电容，使得形成的半导体器件的交流特性增强，半导体器件的使用性能的稳定性得到提高。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高的元件密度，以及更高的集成度的方向发展。器件作为最基本的半导体器件，目前正被广泛应用，传统的平面器件对沟道电流的控制能力变弱，产生短沟道效应而导致漏电流，最终影响半导体器件的电学性能。
为了克服器件的短沟道效应，抑制漏电流，现有技术提出了鳍式场效应晶体管(Fin FET)，鳍式场效应晶体管是一种常见的多栅器件，鳍式场效应晶体管的结构包括：位于半导体衬底表面的鳍部和隔离结构，所述隔离结构覆盖部分所述鳍部的侧壁，位于衬底上且横跨的栅极结构；位于所述栅极结构两侧的鳍部内的源区和漏区。
然而，随着半导体器件的尺寸缩小，器件密度的提高，所形成的鳍式场效应晶体管的性能不稳定。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，使得形成的半导体器件的性能稳定。
为解决上述问题，本发明提供半导体器件的形成方法，包括步骤：提供衬底，所述衬底上形成有若干分隔排列的鳍部；在所述衬底上形成伪栅结构，且所述伪栅结构横跨所述鳍部；在所述伪栅结构的侧壁上形成第一侧墙；在所述衬底上、所述第一侧墙的侧壁上形成层间介电层，且所述层间介电层的顶部低于所述第一侧墙的顶部；在所述层间介电层上、所述第一侧墙的侧壁上形成第二侧墙。
可选的，所述第一侧墙为单层结构或者叠层结构。
可选的，所述第一侧墙的材料包括氧化硅、氮化硅、碳化硅、碳氧化硅、碳化硅中的一种或者多种组合。
可选的，所述第一侧墙的厚度在3～8纳米之间。
可选的，所述第二侧墙为单层结构或者叠层结构。
可选的，所述第二侧墙的材料包括氮化硅、氧化硅、碳氧化硅、氮氧化硅中一种或者多种组合。
可选的，所述第二侧墙的厚度在2～6纳米之间。
可选的，所述层间介电层的材料包括氧化硅、碳化硅、氮氧化硅、氮化硅一种或者多种组合。
可选的，形成所述层间介电层的工艺为化学气相沉积法或者原子层沉积法。
利用上述方法形成的一种半导体器件，包括：衬底；若干鳍部，位于所述衬底上；伪栅结构，位于所述衬底上，且横跨所述鳍部；第一侧墙，位于所述伪栅结构的侧壁上；层间介电层，位于所述衬底上以及所述第一侧墙的侧壁上，且顶部低于所述第一侧墙的顶部；第二侧墙，位于所述层间介电层上以及所述第一侧墙的侧壁上。
与现有技术相比，本发明的技术方案具有以下优点：
在所述伪栅结构的侧壁上形成所述第一侧墙之后，在所述衬底上形成上形成层间介电层，且所述层间介电层的顶部低于所述第一侧墙的顶部；在所述层间介电层上、所述第一侧墙的侧壁上形成第二侧墙；后续将所述伪栅结构替换成金属栅结构以及形成导电插塞时，由于所述第二侧墙的存在，增大了后续形成的金属栅极结构到导电插塞之间的距离，从而能够减少金属栅极结构之间的寄生电容，使得形成的半导体器件的交流特性增强，便于提高半导体器件的使用性能的稳定性。
附图说明
图1至图5是一种半导体器件形成过程的结构示意图；
图6至图12是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
目前形成的半导体器件中，金属栅极之间的寄生电容较大，由于寄生电容产生的干扰作用大，导致半导体器件的交流特性差，影响半导体器件使用性能的稳定性。具体形成过程参考图1至图5。
图1至图5是一种半导体器件形成过程的结构示意图。
参考图1，提供衬底1。
参考图2，在所述衬底1上形成若干鳍部2。
参考图3至图4，在所述衬底1上形成伪栅结构3，且所述伪栅结构横跨所述鳍部2。
图4是图3在剖线A-A的剖面图。
参考图5，在所述伪栅结构3两侧的所述鳍部2内形成源漏区4。
发明人发现，在后续去除所述伪栅结构3形成金属栅极结构，在所述源漏区4处形成导电插塞时，金属栅极结构与导电插塞之间的距离太小，金属栅极结构之间的寄生电容太大，在半导体器件使用时寄生电容产生的干扰作用越大，从而使得半导体器件的交流特性变差，影响半导体器件使用性能的稳定性。
发明人研究发现，在伪栅结构的侧壁上形成第一侧墙之后，在衬底上形成上形成层间介电层，使得层间介电层的顶部低于第一侧墙的顶部；在层间介电层上、所述第一侧墙的侧壁上形成第二侧墙，由于第二侧墙的存在，在后续去除伪栅结构形成金属栅极结构以及形成导电插塞时，增加了金属栅极结构到导电插塞之间的距离，从而使得金属栅极结构之间的寄生电容得到减小，这样在半导体器件使用过程中，寄生电容对其产生的干扰作用也就越小，半导体器件使用性能也就越好，稳定性也越好。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细地说明。
图6至图12是本发明一实施例中半导体器件形成过程的结构示意图。
首先参考图6，提供衬底100，所述衬底100上形成有若干分隔排列的鳍部200。
本实施例中，所述衬底100的材料为单晶硅；其他实施例中，所述衬底100可以是单晶硅，多晶硅或非晶硅；所述衬底100也可以是硅、锗、锗化硅、砷化镓等半导体材料。
形成所述鳍部200的方法包括：在所述衬底100上形成鳍部材料；图形化所述鳍部材料以形成鳍部200。
所述鳍部200的材料为单晶硅；其他实施例中，所述鳍部200的材料还可为硅锗(SiGe)或者砷化镓等半导体材料。
本实施例中，没有在所述衬底100上形成隔离结构；其他实施例中，在形成所述伪栅结构300，还可在所述衬底100上形成隔离结构，隔离结构覆盖所述鳍部200的部分侧壁。
参考图7至图8，在所述衬底100上形成伪栅结构300，且所述伪栅结构300横跨所述鳍部200。
图8是图7沿着剖线A-A的剖视图。
本实施例中，在所述伪栅结构300的顶部没有形成栅极掩膜层；其他实施例中，还可在所述伪栅结构300的顶部形成栅极掩膜层，起到保护所述伪栅结构300的作用。
本实施例中，采用传统的工艺形成所述伪栅结构300。
本实施例中，所述伪栅结构300的材料为多晶硅。
参考图9，在所述伪栅结构300的侧壁上形成第一侧墙301。
本实施例中，所述第一侧墙301的单层结构；其他实施例中，所述第一侧墙301的还可为叠层结构。
本实施例中，所述第一侧墙301的材料为氮化硅；其他实施例中，所述第一侧墙301的材料还可为氧化硅、碳化硅、碳氧化硅、碳化硅中的一种或者多种组合。
所述第一侧墙301用于定义后续形成的源漏掺杂层的位置，且所述第一侧墙301用作保护所述伪栅结构300的侧壁，避免后续去除所述伪栅结构300形成金属栅极结构时，出现金属栅极结构的形貌缺陷，影响半导体结构的电学性能。
本实施例中，采用原子层沉积的方法形成第一侧墙301的第一侧墙材料，工艺参数包括：采用的气体包括DCS气体掺杂SiH2Cl2或者氨气(NH3)，所述气体的流量为1500～4000sccm；温度为200～600℃。
本实施例中，刻蚀所述第一侧墙材料形成所述第一侧墙301，直至暴露出所述衬底100以及所述伪栅结构300的顶部，刻蚀的工艺为选用四氟化碳(CF4)、CH3F气体和氧气(O2)作为刻蚀气氛；所述四氟化碳(CF4)气体的气体流量范围是5～100sccm、所述CH3F气体的气体流量范围是8～250sccm；所述氧气(O2)的气体流量范围是10～400sccm；采用的源射频功率RF的范围是50～300W；电压范围是30～100V；刻蚀处理时间为4～～50s；刻蚀压强为10～2000毫托。
本实施例中，所述第一侧墙301的厚度在3～8纳米之间。
本实施例中，当所述第一侧墙301的厚度小于3纳米时，由于所述第一侧墙301的厚度太薄，后续工艺过程中不能起到保护所述伪栅结构300的侧壁形貌的作用，同时由于所述第一侧墙301的厚度太薄，定义后续形成的源漏掺杂层的位置离金属栅极结构的位置太近，影响形成的半导体器件的电学性能；当所述第一侧墙301的厚度大于8纳米时，此时所述第一侧墙301的厚度太厚，一方面造成形成所述第一侧墙301材料的浪费；另外一方面，由于所述第一侧墙301的厚度太厚，定义后续形成的源漏掺杂层的位置离金属栅极结构的位置太大，不利于形成集成度高的半导体器件。
参考图10，在所述衬底100上、所述第一侧墙301的侧壁上形成层间介电层400，且所述层间介电层400的顶部低于所述第一侧墙301的顶部。
本实施例中，所述层间介电层400的材料碳化硅；其他实施例中，所述层间介电层400的材料还可为氧化硅、氮氧化硅、氮化硅的一种或者多种组合。
本实施例中，形成所述层间介电层400工艺为化学气相沉积工艺；所述层间介电层400的工艺参数包括采用的气体包括氧气、氨气(NH3)、和N(SiH3)3气体，氧气的流量为20sccm～10000sccm，氨气(NH3)气体的流量为20sccm～10000sccm，N(SiH3)3气体的流量为20sccm～10000sccm，腔室压强为0.01～10托，温度为30℃～90℃。
其他实施例中，还可以采用原子层沉积法或者等离子体增强化学气相沉积法等方法形成所述层间介电层400。
本实施例中，形成所述层间介电层400后，通过化学机械研磨的方式使使得所述层间介电层400的顶部与所述第一侧墙301的顶部齐平；其他实施例中，还可采用机械研磨工艺使得所述层间介电层400的顶部与所述第一侧墙301的顶部齐平。
本实施例中，采用化学机械研磨的方式的原因在于化学机械研磨方法综合了化学研磨和机械研磨的优势，可以保证获得表面平整度高的所述层间介电层400，有助于形成质量好的半导体器件。
本实施例中，采用干法刻蚀所述层间介电层400，直至所述层间介电层400的顶部低于所述第一侧墙301的顶部；刻蚀所述层间介电层400的工艺参数包括，选用氦气(He)、氨气(NH3)以及NF3气体作为刻蚀气氛，其中所述氦气(He)的气体流量范围是600sccm～2000sccm，所述氨气(NH3)的气体流量为200sccm～5000sccm，所述NF3气体流量为20sccm～2000sccm，刻蚀压强为2～100毫托，刻蚀处理时间为20～1000s。
参考图11，在所述层间介电层400上、所述第一侧墙301的侧壁上形成第二侧墙302。
本实施例中，所述第二侧墙302为单层结构；其他实施例中，所述第二侧墙302还可为叠层结构。
本实施例中，所述第二侧墙302的材料为氮化硅；其他实施例中，所述第二侧墙302的材料还可为氧化硅、碳氧化硅、氮氧化硅中的一种或者多种组合。
本实施例中，所述第二侧墙302的厚度在2～6纳米之间。
本实施例中，当所述第二侧墙302的厚度小于2纳米时，在后续形成金属栅极结构和导电插塞时，由于形成的所述第二侧墙302的厚度太薄，金属栅极结构与导电插塞的距离太小，金属栅极结构之间的寄生电容没有得到很好减少，寄生电容产生的干扰作用没有得到缓解，不能够提高半导体器件使用性能的稳定；当所述第二侧墙302的厚度大于6纳米的时候，由于形成的所述第二侧墙302的厚度太厚，一方面导致形成的所述第二侧墙302的材料浪费；另外一方面，由于形成的所述第二侧墙302的厚度太厚，不利于形成集成度较高的半导体器件；同时也会影响到形成的半导体器件的电学性能。
参考图12，在所述伪栅结构300两侧的所述鳍部200内形成源漏区500。
本实施例中，在后续去除所述伪栅结构300形成金属栅极结构以及在所述源漏区500形成导电插塞时，由于所述第二侧墙302的存在，增加了形成的金属栅极结构到形成的导电插塞之间的距离，使得金属栅极结构之间的寄生电容减少，因此由于寄生电容的存在而产生的干扰作用就减少，半导体器件的交流特性增强，半导体器件的使用性能的稳定性得到提高。
利用上述方法形成的一种半导体器件，包括：衬底100；若干鳍部200，位于所述衬底100上；伪栅结构300，位于所述衬底100上，且横跨所述鳍部200；第一侧墙301，位于所述衬底100上以及所述伪栅结构300的侧壁上；层间介电层400，位于所述衬底100上、所述第一侧墙301的侧壁上，且顶部低于所述第一侧墙301的顶部；第二侧墙302，位于所述层间介电层400上以及所述第一侧墙301的侧壁上。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (10)

1.一种半导体器件的形成方法，其特征在于，包括：
提供衬底，所述衬底上形成有若干分隔排列的鳍部；
在所述衬底上形成伪栅结构，且所述伪栅结构横跨所述鳍部；
在所述伪栅结构的侧壁上形成第一侧墙；
在所述衬底上、所述第一侧墙的侧壁上形成层间介电层，且所述层间介电层的顶部低于所述第一侧墙的顶部；
在所述层间介电层上、所述第一侧墙的侧壁上形成第二侧墙。
2.如权利要求1所述半导体器件的形成方法，其特征在于，所述第一侧墙为单层结构或者叠层结构。
3.如权利要求2所述半导体器件的形成方法，其特征在于，所述第一侧墙的材料包括氧化硅、氮化硅、碳化硅、碳氧化硅、碳化硅中的一种或者多种组合。
4.如权利要求1所述半导体器件的形成方法，其特征在于，所述第一侧墙的厚度在3～8纳米之间。
5.如权利要求1所述半导体器件的形成方法，其特征在于，所述第二侧墙为单层结构或者叠层结构。
6.如权利要求5所述半导体器件的形成方法，其特征在于，所述第二侧墙的材料包括氮化硅、氧化硅、碳氧化硅、氮氧化硅中的一种或者多种组合。
7.如权利要求1所述半导体器件的形成方法，其特征在于，所述第二侧墙的厚度在2～6纳米之间。
8.如权利要求1所述半导体器件的形成方法，其特征在于，所述层间介电层的材料包括氧化硅、碳化硅、氮氧化硅、氮化硅中一种或者多种组合。
9.如权利要求1所述半导体器件的形成方法，其特征在于，形成所述层间介电层的工艺为化学气相沉积法或者原子层沉积法。
10.一种采用权利要求1至9任一项方法所形成的半导体器件，其特征在于，包括：
衬底；
若干鳍部，位于所述衬底上；
伪栅结构，位于所述衬底上，且横跨所述鳍部；
第一侧墙，位于所述伪栅结构的侧壁上；
层间介电层，位于所述衬底上以及所述第一侧墙的侧壁上，且顶部低于所述第一侧墙的顶部；
第二侧墙，位于所述层间介电层上以及所述第一侧墙的侧壁上。
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