WO2014005361A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014005361A1
WO2014005361A1 PCT/CN2012/078839 CN2012078839W WO2014005361A1 WO 2014005361 A1 WO2014005361 A1 WO 2014005361A1 CN 2012078839 W CN2012078839 W CN 2012078839W WO 2014005361 A1 WO2014005361 A1 WO 2014005361A1
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gate
dummy gate
layer
type
source
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PCT/CN2012/078839
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English (en)
French (fr)
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尹海洲
朱慧珑
张珂珂
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中国科学院微电子研究所
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Priority to US14/412,173 priority Critical patent/US9576802B2/en
Publication of WO2014005361A1 publication Critical patent/WO2014005361A1/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and, in particular, to a method of fabricating a semiconductor device that avoids the formation of holes in a metal gate and a semiconductor device fabricated using the method. Background technique
  • the gate isolation isolation effect and the gate-to-channel region control capability are becoming higher and higher, and the conventional silicon oxide gate insulating layer is gradually thinner. It has been difficult to continue to provide sufficient isolation of the insulation, and it is difficult for the polysilicon gate to precisely control the work function to adjust the device threshold voltage.
  • the high-k material acts as a gate insulating layer, and the metal material fills the high-k-metal gate structure as a gate conductive layer, which has become the mainstream of the current MOSFET.
  • the development of the front gate process in which the gate stack structure is first deposited and then ion implanted and activated to form source and drain regions is limited.
  • the dummy gate stack is deposited first, the source and drain regions are implanted, the dummy gate is etched to form the gate trench, and the gate stack is deposited in the gate trench. This gate-gate process gradually assumes the dominant position.
  • the second layer of metal material Upon subsequent deposition of the metal fill layer, the second layer of metal material will prematurely close at the top due to the local protrusions, ending the deposition fill, and correspondingly forming voids in the middle and bottom that are not completely filled. These holes unnecessarily increase the resistivity of the entire metal gate, degrading the performance of the device. Summary of the invention
  • the present invention provides a method of fabricating a semiconductor device, comprising: forming a T-type dummy gate structure on a substrate; removing a T-type dummy gate structure, leaving a T-type gate trench; The gate trench is filled with a metal layer to form a ⁇ -type metal gate structure.
  • the step of forming a T-type dummy gate structure further comprises: forming a dummy gate stack structure composed of a gate insulating layer and a dummy gate layer on the substrate; forming a gate on both sides of the dummy gate stacked structure The height of the sidewall spacer is smaller than the height of the dummy gate stack structure, thereby exposing the top of the dummy gate stack structure; forming a dummy gate epitaxial layer on the top and sides of the exposed dummy gate stack structure, the dummy gate The epitaxial layer and the dummy gate layer together form a T-type dummy gate structure.
  • a dummy drain epitaxial layer is formed on both sides of the gate spacer while forming a dummy gate epitaxial layer.
  • the source-drain epitaxial layer is doped to form a source Leak heavily doped regions.
  • step of forming the gate spacer further comprises: forming a sidewall material layer on the substrate and the dummy gate layer; over etching the sidewall material layer, so that the height of the formed gate sidewall is less than pseudo The height of the gate stack structure.
  • the metal layer includes a work function adjusting layer and a metal gate filling layer.
  • the work function adjusting layer comprises TiN, TaN and a combination thereof
  • the metal gate filling layer comprises Ti, Ta, W, Al, Cu, Mo and a combination thereof.
  • the gate insulating layer comprises a high-k material.
  • the dummy gate layer comprises polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, hydrogenated amorphous carbon, and combinations thereof.
  • the gate spacer comprises silicon nitride, silicon oxynitride, DLC, and combinations thereof.
  • the difference in width between the top and the bottom of the T-type dummy gate structure is not greater than the width of the gate spacer.
  • the present invention also provides a semiconductor device including a gate insulating layer of a high-k material on a substrate, a substrate, a T-type metal gate structure on a gate insulating layer, and a T-type metal gate structure. Source and drain areas on both sides.
  • the semiconductor device manufacturing method of the present invention by forming the T-type dummy gate and the T-type gate trench, the suspension phenomenon and the hole formation in the subsequent metal gate filling process are avoided, and the improvement is improved. Device performance. DRAWINGS
  • a dummy gate stack structure 2 is formed on the substrate 1, and a sidewall material layer 3 is formed on the dummy gate stack structure 2 and the substrate 1.
  • a substrate 1 is provided, such as a silicon-based material, including bulk silicon (S i ), silicon-on-insulator (SOI), S iGe, S iC, strained silicon, silicon nanotubes, and the like.
  • the substrate 1 may be other semiconductor materials such as Ge, GeOI, S iGe, II IV compounds, and I I-VI compounds.
  • bulk silicon or SOI is selected as the substrate 1 for compatibility with a CMOS process.
  • an isolation region 1A composed of an oxidized material corresponding to the substrate 1 (for example, an insulating material such as silicon oxide) is formed, for example. Encloses and defines the active area of the device.
  • the gate insulating layer is sequentially deposited on the substrate 1 (in the active region) by conventional methods such as LPCVD, HDPCVD, ALD, MBE, cathode ray deposition, radio frequency sputtering, ion beam deposition, MVPECVD, RFPECVD, and the like. 2A, dummy gate layer 2B, and then etched to form a dummy gate stack.
  • the gate insulating layer 2A may be a conventional silicon oxide, that is, as a pad oxide layer, in the back gate process for protecting the bottom channel region from being overetched, removing the dummy gate 2B and the gate insulating layer 2A.
  • the gate trench is then refilled with a high-k material to form the final gate insulating layer.
  • the gate insulating layer 2A may also be a high-k material, which is not removed after formation, but is directly retained as the final gate insulating layer 2A.
  • High-k materials include, but are not limited to, nitrides (eg, S iN, A 1N, T iN ), metal oxides (mainly sub-group and lanthanide metal element oxides such as A 1 2 0 3 , Ta 2 0 5 , Ti0) 2 , ZnO, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3 , La 2 0 3 ), a perovskite phase oxide (for example, PbZrxTihO PZT ), Ba.Sr ⁇ Ti Os (BST )).
  • nitrides eg, S iN, A 1N, T iN
  • metal oxides mainly sub-group and lanthanide metal element oxides such as A 1 2 0 3 , Ta 2 0 5 , Ti0
  • the dummy gate layer 2B is a silicon-based material or a carbon-based material, including polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous carbon, hydrogenated amorphous carbon, and combinations thereof.
  • the dummy gate layer 2B is made of a material homologous to the substrate 1, that is, the same as the Si-based material, except that the crystal morphology is different.
  • the width and thickness of the gate insulating layer 2A and the dummy gate layer 2B are selected in accordance with device performance requirements.
  • the first source-drain ion implantation is performed in the active region of the village on both sides of the dummy gate stack structure to form a lightly doped source-drain extension region (LDD) 1B and / or ha (source) leakage source doped region 1C.
  • LDD lightly doped source-drain extension region
  • source source
  • the type, dose, and energy of the doping ions depend on the type of MOSFET and the depth of the junction, and are not described here.
  • a sidewall material layer 3 the material of which is, for example, silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC), and combinations thereof, further providing stress in the gate sidewall insulating isolation to preferably enhance the channel Area Carrier mobility.
  • the sidewall material layer 3 covers the STI 1A, the source/drain extension region 1B, and the dummy gate layer 2B.
  • the sidewall material layer 3 is etched to form a gate spacer 3A, wherein the height of the gate spacer 3A is smaller than the height of the dummy gate stack 2.
  • Etching the sidewall material layer 3 by an anisotropic dry etching process such as plasma etching, reactive ion etching (RIE), and/or an isotropic wet etching process, and preferably performing overetching
  • the etch (for example, 5% - 10%) causes the height of the gate sidewall 3A obtained by etching to be smaller than the height of the dummy gate stack 2, that is, the top of the gate spacer 3A is lower than the top of the dummy gate layer 2B.
  • the height of the exposed region of the dummy gate layer 2B may be 1/3 or less of the height of the dummy gate layer 2B, preferably 1 /4 to 1 / 6 , in order to well control the shape of the epitaxial region, and further The shape of the T-type dummy gate and the T-type gate trench is controlled later.
  • a T-type dummy gate structure is formed.
  • a dummy gate epitaxial layer 2C and a source/drain epitaxial layer 1D are formed on top of the dummy gate layer 2B and on top of the source/drain extension region 1B, respectively.
  • the pseudo gate epitaxial layer 2C and the source/drain epitaxial layer 1D of the silicon material are selectively epitaxially grown on the top of both.
  • the pseudo gate epitaxial layer 2C and the dummy gate layer 2B are configured to form a T-type dummy gate structure for avoiding the suspension phenomenon and low source-drain contact resistance.
  • the dummy gate layer 2B is different from the material of the substrate 1, for example, the dummy gate layer 2B is a carbon-based material and the substrate 1 is a silicon-based material, and the pseudo gate epitaxial layer having different materials can be selectively epitaxially grown twice.
  • dummy gate epitaxial layer 2C and dummy gate layer 2B are both amorphous carbon, hydrogenated amorphous carbon, source-drain epitaxial layer 1D and village bottom 1 (source-drain extension region 1B) Silicon-based materials (polysilicon, amorphous silicon), mis-base materials (polycrystalline germanium, amorphous germanium) or the same compound materials.
  • in-situ doping may be performed on the source-drain epitaxial layer 1 D while epitaxial growth to obtain a source-drain heavily doped region 1 having a higher doping concentration. D, or may be formed after performing an additional ion implantation process to dope such that the source-drain epitaxial region (and a portion of the underside thereof) constitute a source-drain heavily doped region (not shown).
  • an interlayer dielectric layer 4 is deposited over the entire device structure.
  • An interlayer dielectric layer (ILD) of low-k material is formed, for example, by LPCVD, PECVD, spin coating, spray coating, screen printing, etc., and low-k materials include, but are not limited to, organic low-k materials (eg, aryl-containing or polycyclic rings).
  • ILD4 is silicon oxide or silicon oxynitride.
  • the ILD 4 may be planarized by an overetch or CMP process until the dummy gate layer 2B is exposed. At this time, as shown in FIG. 5, the dummy gate epitaxial layer 2C located above the top of the dummy gate layer 2B is removed, leaving only the partial dummy gate epitaxial layers 2C, 2C of the side of the dummy gate layer 2B. 2B—same form a T-type dummy gate structure.
  • the difference in width between the top and bottom of the T-type dummy gate structure and the difference in height between the gate spacer 3A and the dummy gate stack 2 are too small to suppress the suspension phenomenon, and when the width difference is too large (for example, exceeding the gate)
  • the width of the side wall 3A itself is easy to make the overlap of the final gate and the source and drain regions in the top view too large, resulting in an increase in parasitic capacitance and a decrease in device performance.
  • the gate spacer 3A is usually corroded too much, losing its shadow blocking effect.
  • the height difference and/or the width difference is not larger than the width of the gate spacer 3A. 5 ⁇ 1. 0 ⁇ The height difference and / or width difference is 0. 5 ⁇ 1. 0 times the width of the gate spacer 3A.
  • the T-type dummy gate structure 2B/2C' is etched away, leaving a T-type gate trench 2D.
  • the T-type dummy gate structure can be etched away by wet or dry methods, except that different materials use different solutions or gases.
  • the same is dry etching, for the dummy gate epitaxial layer 2C which is silicon-based material, and the T-type dummy gate structure composed of the dummy gate layer 2B, which can be etched by using a halogen-based gas;
  • the T-type dummy gate structure of the carbon-based material may be etched using an oxygen plasma to remove the dummy gate leaving the gate trench 2D.
  • the gate insulating layer 2A when the gate insulating layer 2A is a silicon oxide used as a pad oxide layer, the gate insulating layer 2A may be removed together until the substrate 1 (channel region) is exposed and then a high-k material is deposited; When the insulating layer 2A itself is a high-k material, the gate trench is etched on the top surface of the gate insulating layer 2A.
  • a first metal layer 5 is formed over the entire device.
  • the first metal layer 5A is deposited on the ILD 4 and the T-type gate trench 2D by sputtering, MOSCVD, ALD, or the like, for example, as a work function adjusting layer or a metal barrier layer.
  • the material of the first metal layer 5A is, for example, TiN, TaN, and a combination thereof, and the thickness thereof is selected in accordance with the adjustment of the work function. It is worth noting that due to the special shape of the T-type gate trench, the suspension phenomenon does not occur when the first metal layer 5A is deposited.
  • a second metal layer 7B is deposited on the first metal layer 5A.
  • the second metal layer 5B is formed on the first metal layer 5A (including continuing to be filled in the gate trench) to be used as a metal gate filling layer by sputtering, M0CVD, ALD, etc., for example, Ti, Ta , W, Al, Cu, Mo, etc. and combinations thereof. Since the suspension phenomenon does not occur when the first metal layer 5A shown in FIG. 7 is deposited, the second metal layer 5B can smoothly completely fill the remaining portion of the gate trench without leaving any holes in the gate, thus ensuring The gate resistance does not increase, ultimately improving device performance. As shown in FIG.
  • the first metal layer 5A and the second metal layer 5B collectively constitute a T-type metal gate structure that is compatible with the T-type gate trench.
  • a contact etch stop layer (CESL) 6 such as S iN, S iON material is deposited on the entire device, a second ILD 7 is deposited, and the second ILD 7, CESL6, and I LD4 are etched to form a source/drain contact hole, in contact with the source and drain.
  • a metallization layer 8 (for example, a metal silicide such as NiS i, PtS i , CoS i , etc.) is formed on/in the exposed source/drain epitaxial layer 1 D in the hole to reduce source-drain contact resistance, filling metal and/or metal nitride forming source.
  • the drain contact plug 9 is deposited, and the third ILD 10 is deposited and etched to form a lead hole.
  • the lead hole is filled with metal to form a lead 11 to form a word line or a bit line of the device to complete the final device structure. As shown in FIG.
  • the final MOSFET device structure includes at least the gate insulating layer 2A on the substrate 1, the bottom 1 of the village, the T-type metal gate structure 5A/5B, and the source and drain regions on both sides of the T-type metal gate structure.
  • the remaining components of the MOSFET and the corresponding materials have been listed in detail in the above description of the method, and are not described herein again.
  • the semiconductor device manufacturing method of the present invention by forming the T-type dummy gate and the T-type gate trench, the suspension phenomenon and the hole formation in the subsequent metal gate filling process are avoided, and the device performance is improved.

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Abstract

提供一种半导体器件制造方法，包括：在衬底（1）上形成T型伪栅极结构（2B/2C'）；去除T型伪栅极结构（2B/2C'），留下T型栅极沟槽（2D）；在T型栅极沟槽（2D）中填充金属层（5A，5B），形成T型金属栅极结构（5A/5B）。如此通过形成T型伪栅极以及T型栅极沟槽，避免了后续金属栅极填充工艺中的悬挂现象及孔洞形成，提高了器件性能。

Description

半导体器件及其制造方法
[0001] 本申请要求了 2012年 7月 3日提交的、 申请号为 201210229543. 1、 发 明名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内 容通过引用结合在本申请中。 技术领域
[0002] 本发明涉及一种半导体器件及其制造方法， 特别是涉及一种避免在 金属栅极中形成孔洞的半导体器件制造方法以及使用该方法制造的半导体 器件。 背景技术
[0003] 随着 M0SFET特征尺寸持续等比例缩减，对栅极绝缘隔离效果以及 栅极对沟道区控制能力的要求越来越高， 传统的氧化硅栅绝缘层在厚度 逐渐变薄的情况下已经难以继续提供足够的绝缘隔离， 而多晶硅栅极也 难以精确控制功函数以调节器件阈值电压。 高 k 材料作为栅极绝缘层、 并且金属材料填充作为栅极导电层的高 k-金属栅结构已经成为目前 M0SFET的主流。 由于高 k材料特性易在高温或者离子轰击条件下变化， 先沉积栅极堆叠结构而后离子注入并激活退火形成源漏区的前栅工艺发 展受到限制。 先沉积伪栅极堆叠、 注入形成源漏区， 再刻蚀去除伪栅极 形成栅极沟槽、 在栅极沟槽中沉积栅极堆叠， 这种后栅工艺逐渐占据主 导地位。
[0004] 然而， 随着尺寸进一步缩减， 小尺寸的器件使得栅极沟槽的深宽 比越来越大， 后栅工艺中填充栅极沟槽成为制约工艺发展的一个重要瓶 颈。 正如 US 2012/ 012948 A1 中所公开的， 由于栅极沟槽宽度相对于其 深度而言过窄， 在沉积功函数调节层 /金属阻挡层时， 该第一层金属材料 会在栅极沟槽的上边沿形成 "悬挂"， 也即在上边沿处第一金属层会形成 朝向栅极沟槽中心、 超越了栅极侧墙的局部突起。 在后续沉积金属填充 层时， 第二层金属材料会由于该局部突起而在顶部过早闭合、 结束沉积 填充， 相应地在中部和底部形成了未完全填充而引发的孔洞。 这些孔洞 使得整个金属栅的电阻率不必要地增大， 降低了器件的性能。 发明内容
[0005] 由上所述， 本发明的目的在于提供一种能够避免在金属栅极中形成 孔洞的半导体器件制造方法以及使用该方法制造的半导体器件。
[0006] 为此， 本发明提供了一种半导体器件制造方法， 包括： 在村底上形 成 T型伪栅极结构； 去除 T型伪栅极结构， 留下 T型栅极沟槽； 在 T型栅极沟槽 中填充金属层， 形成 τ型金属栅极结构。
[0007] 其中， 形成 T型伪栅极结构的步骤进一步包括： 在村底上形成栅极 绝缘层与伪栅极层构成的伪栅极堆叠结构； 在伪栅极堆叠结构两侧形成栅极 侧墙， 栅极侧墙的高度小于伪栅极堆叠结构的高度， 从而暴露出伪栅极堆叠 结构顶部； 在暴露出的伪栅极堆叠结构顶部上以及侧面形成伪栅极外延层， 伪栅极外延层与伪栅极层共同构成 T型伪栅极结构。
[0008] 其中， 形成伪栅极外延层的同时， 在栅极侧墙两侧形成源漏外延层。
[0009] 其中， 形成源漏外延层的同时或者之后， 对源漏外延层掺杂形成源 漏重掺杂区。
[001 0] 其中， 形成栅极侧墙的步骤进一步包括： 在村底以及伪栅极层上形 成侧墙材料层； 过刻蚀侧墙材料层， 使得形成的栅极侧墙的高度小于伪栅极 堆叠结构的高度。
[001 1 ] 其中， 在形成伪栅极堆叠结构之后、 形成栅极侧墙之前， 在伪栅极 堆叠结构两侧村底中形成源漏扩展区和 /或晕状源漏区。
[0012] 其中， 形成 T型伪栅极结构之后、 去除 T型伪栅极结构之前， 在村底
[001 3] 其中， 金属层包括功函数调节层与金属栅填充层。
[0014] 其中， 功函数调节层包括 TiN、 TaN及其组合， 金属栅填充层包括 Ti、 Ta、 W、 Al、 Cu、 Mo及其组合。
[0015] 其中， 栅极绝缘层包括高 k材料。
[0016] 其中， 伪栅极层包括多晶硅、 非晶硅、 微晶硅、 非晶碳、 氢化非晶 碳及其组合。
[0017] 其中， 栅极侧墙包括氮化硅、 氮氧化硅、 DLC及其组合。
[0018] 其中， T型伪栅极结构的顶部与底部的宽度差不大于栅极侧墙的宽 度。
[0019] 本发明还提供了一种半导体器件， 包括村底、 村底上的高 k材料的栅 极绝缘层、 栅极绝缘层上的 T型金属栅极结构、 以及 T型金属栅极结构两侧的 源漏区。
[0020] 依照本发明的半导体器件制造方法， 通过形成 T型伪栅极以及 T型栅 极沟槽， 避免了后续金属栅极填充工艺中的悬挂现象以及孔洞形成， 提高了 器件性能。 附图说明
[0021] 以下参照附图来详细说明本发明的技术方案， 其中： 意图。 具体实施方式
[0023] 以下参照附图并结合示意性的实施例来详细说明本发明技术方案的 特征及其技术效果，公开了能够避免在金属栅极中形成孔洞的半导体器件制 造方法以及使用该方法制造的半导体器件。 需要指出的是， 类似的附图标记 表示类似的结构， 本申请中所用的术语 "第一"、 "第二"、 "上"、 "下" 等等 可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修 饰器件结构或制造工序的空间、 次序或层级关系。 意图。
[0025] 参照图 1 , 在村底 1上形成伪栅极堆叠结构 2 , 在伪栅极堆叠结构 2以 及村底 1上形成侧墙材料层 3。提供村底 1 , 例如为硅基材料， 包括体硅（S i )、 绝缘体上硅（SOI )、 S iGe、 S iC、 应变硅、 硅纳米管等等。 此外， 村底 1也可 以是其他半导体材料， 例如 Ge、 GeOI、 S iGe、 I I I-V族化合物、 I I-VI族化合 物。 优选地， 选用体硅或 S0I作为村底 1 , 以便与 CMOS工艺兼容。 优选地， 形 成由村底 1对应的氧化材料（例如氧化硅等绝缘材料）构成的隔离区 1A, 例 包围并限定出了器件的有源区。 如图 1所示， 在村底 1上 （有源区中） 采用 LPCVD、 HDPCVD , ALD、 MBE、 阴极射线沉积、射频溅射、 离子束沉积、 MVPECVD, RFPECVD等常规方法依次沉积栅极绝缘层 2A、 伪栅极层 2B , 并随后刻蚀形成 伪栅极堆叠。 栅极绝缘层 2A可以是常规的氧化硅， 也即作为垫氧化层， 在后 栅工艺中用于保护村底沟道区不被过刻蚀，去除伪栅极 2B以及栅极绝缘层 2A 形成栅极沟槽之后再重新填充高 k材料形成最终的栅极绝缘层。 栅极绝缘层 2A也可以是高 k材料， 形成之后不再去除， 而是直接保留作为最终的栅极绝 缘层 2A。 高 k材料包括但不限于氮化物 （例如 S iN、 A 1N、 T iN )、 金属氧化物 (主要为副族和镧系金属元素氧化物， 例如 A 1203、 Ta205、 Ti02、 ZnO、 Zr02、 Hf02、 Ce02、 Y203、 La203 )、钙钛矿相氧化物（例如 PbZrxTihO PZT )、 Ba.Sr^Ti Os ( BST ) )。 伪栅极层 2B为硅基材料或者碳基材料， 包括多晶硅、 非晶硅、 微 晶硅、 非晶碳、 氢化非晶碳及其组合。 优选地， 伪栅极层 2B采用与村底 1同 源的材料， 也即同为 S i基材料， 只是晶体形态不同。 栅极绝缘层 2A与伪栅极 层 2B的宽度、 厚度依照器件性能需要而选定。 以伪栅极堆叠 2A/2B为掩模， 在伪栅极堆叠结构两侧的村底有源区中进行第一次源漏离子注入， 形成轻掺 杂的源漏延伸区 （LDD ) 1B和 /或晕状（ha lo )源漏掺杂区 1C。 掺杂离子的种 类、 剂量、 能量依照 M0SFET类型以及结深而定， 在此不再赘述。 采用 LPCVD、 HDPCVD, ALD、 MBE、阴极射线沉积、射频溅射、离子束沉积、 MVPECVD, RFPECVD 等常规沉积方法，在整个器件上——也即伪栅极堆叠结构 2以及两侧村底 1上 形成侧墙材料层 3 ,其材质例如为氮化硅、氮氧化硅、类金刚石无定形碳（ DLC ) 及其组合，提供栅极侧壁绝缘隔离之外还可以优选地施加应力以提高沟道区 载流子迁移率。 此时， 如图 1所示， 侧墙材料层 3覆盖了 STI 1A、 源漏扩展区 1B、 伪栅极层 2B。
[0026] 如图 2所示， 刻蚀侧墙材料层 3 , 形成栅极侧墙 3A, 其中栅极侧墙 3A 的高度小于伪栅极堆叠结构 2的高度。 采用等离子体刻蚀、 反应离子刻蚀 ( RIE )等各向异性干法刻蚀工艺和 /或各向同性的湿法刻蚀工艺相结合刻蚀 侧墙材料层 3 , 并且优选地执行过刻蚀 （例如 5 % - 10 % )， 使得刻蚀得到的 栅极侧墙 3A的高度小于伪栅极堆叠结构 2的高度， 也即栅极侧墙 3A的顶部低 于伪栅极层 2B的顶部， 从而使得伪栅极层 2B顶部的一部分区域（顶部以及侧 面）暴露出来， 以用于稍后的外延。 如图 2所示， 伪栅极层 2B暴露的区域的 高度可以是伪栅极层 2B高度的 1 / 3以下， 优选地为 1 /4 ~ 1 / 6 , 以便良好控制 外延区域的形状， 进一步控制稍后 T型伪栅极、 T型栅极沟槽的形状。
[0027] 如图 3所示， 形成 T型伪栅极结构。 例如， 选择性外延生长， 在伪栅 极层 2B顶部以及源漏扩展区 1B顶部分别形成伪栅极外延层 2C和源漏外延层 1D。 对于伪栅极层 2B与村底 1 (源漏扩展区 1B ) 均为 S i基材料的情形， 同时 在两者顶部选择性外延生长硅材料的伪栅极外延层 2C和源漏外延层 1D, 其中 伪栅极外延层 2C与伪栅极层 2B—同构成 T型伪栅极结构以用于避免悬挂现象 低源漏接触电阻。 当伪栅极层 2B与村底 1材质不同时， 例如伪栅极层 2B为碳 基材料而村底 1为硅基材料， 可分两次选择性外延生长出材料不同的伪栅极 外延层 2C和源漏外延层 1D, 例如伪栅极外延层 2C与伪栅极层 2B均为非晶碳、 氢化非晶碳， 源漏外延层 1D与村底 1 (源漏扩展区 1B ) 均为硅基材料（多晶 硅、 非晶硅）、 错基材料（多晶锗、 非晶锗）或者相同的化合物材料。 优选 地， 为提高源漏区域掺杂浓度降低源漏区域接触电阻， 可以在外延生长的同 时对于源漏外延层 1 D施行原位掺杂而获得掺杂浓度更高的源漏重掺杂区 1 D , 或者也可以形成之后执行额外的离子注入工艺来掺杂使得源漏外延区（以及 其下方的部分村底）构成源漏重掺杂区 （未示出）。
[0028] 如图 4所示， 在整个器件结构上沉积形成层间介质层 4。 例如通过 LPCVD、 PECVD、 旋涂、 喷涂、 丝网印刷等方式， 形成低 k材料的层间介质层 ( ILD ) 4 , 低 k材料包括但不限于有机低 k材料（例如含芳基或者多元环的 有机聚合物）、 无机低 k材料（例如无定形碳氮薄膜、 多晶硼氮薄膜、 氟硅 玻璃、 BSG、 PSG、 BPSG )、 多孔低 k材料（例如二硅三氧烷（ SSQ )基多孔低 k材料、 多孔二氧化硅、 多孔 S iOCH、 掺 C二氧化硅、 掺 F多孔无定形碳、 多孔金刚石、 多孔有机聚合物）。 优选地， ILD4为氧化硅或者氮氧化硅。
[0029] 如图 5所示， 可以采用过刻蚀或者 CMP工艺， 平坦化 ILD4 , 直至暴 露伪栅极层 2B。 此时， 如图 5所示， 位于伪栅极层 2B顶部以上部分的伪栅 极外延层 2C被去除， 而仅留下伪栅极层 2B侧面的部分伪栅极外延层 2C，， 2C 与 2B—同构成 T型伪栅极结构。 T型伪栅极结构顶部与底部之间的宽度 差与栅极侧墙 3A与伪栅极堆叠结构 2的高度差过小时难以抑制悬挂现象， 而当该宽度差过大时 （例如超过栅极侧墙 3A本身宽度）则容易使得最终栅 极与源漏区在顶视图中重叠部分过大造成寄生电容增大而降低器件性能。此 夕卜， 当伪栅极外延层 2C， 底部与伪栅极层 2B底部之间的高度差过大时栅极 侧墙 3A通常会被腐蚀的过于严重， 失去其遮蔽阻挡的作用。 因此， 优选地， 该高度差和 /或宽度差不大于栅极侧墙 3A的宽度。 具体地， 前述的高度差和 /或宽度差是栅极侧墙 3A宽度的 0. 5 ~ 1. 0倍。 [0030] 如图 6所示， 刻蚀去除 T型伪栅极结构 2B/ 2C'， 留下 T型栅极沟槽 2D。 可采用湿法或干法可刻蚀去除 T型伪栅极结构， 只是不同的材料采用不 同的溶液或气体。 例如， 同样是干法刻蚀， 对于均是硅基材质的伪栅极外延 层 2C， 与伪栅极层 2B构成的 T型伪栅极结构，可采用卤素基气体进行刻蚀； 对于材质为碳基材料的 T型伪栅极结构可采用氧等离子体刻蚀，去除伪栅极 而留下栅极沟槽 2D。特别地， 当栅极绝缘层 2A是用作垫氧化层的氧化硅时， 可以一并去除栅极绝缘层 2A直至暴露村底 1(沟道区）并随后沉积高 k材料； 而当栅极绝缘层 2A本身就是高 k材料时， 则刻蚀栅极沟槽时停止在栅极绝 缘层 2A的顶表面上。
[0031 ] 如图 7所示，在整个器件上形成第一金属层 5。例如通过溅射、 M0CVD、 ALD等方式， 在 ILD 4上以及 T型栅极沟槽 2D中沉积形成第一金属层 5A , 用作功函数调节层或者金属阻挡层。 第一金属层 5A的材质例如是 TiN、 TaN 及其组合， 其厚度依照功函数调节需要而选定。 值得注意的是， 由于 T型栅 极沟槽的特殊形态， 使得沉积第一金属层 5A时不会发生悬挂现象。
[0032] 如图 8所示， 在第一金属层 5A上沉积第二金属层 7B。 例如通过溅射、 M0CVD、 ALD等方式， 在第一金属层 5A上（包括继续填充在栅极沟槽中）形成 第二金属层 5B以用作金属栅填充层， 其材质例如为 Ti、 Ta、 W、 Al、 Cu、 Mo 等等及其组合。 由于图 7所示的第一金属层 5A沉积时没有发生悬挂现象， 因 此第二金属层 5B得以顺利完全填充了栅极沟槽的剩余部分， 没有在栅极中留 下任何孔洞， 因此确保了栅极电阻不会增大， 最终提高了器件性能。 如图 8 所示， 第一金属层 5A、 第二金属层 5B共同构成了与 T型栅极沟槽共型的 T型金 属栅极结构。 [0033] 最后， 如图 9所示， 完成后续工艺。在整个器件上沉积例如 S iN、 S iON 材质的接触刻蚀停止层（CESL ) 6 , 沉积第二 ILD 7 , 刻蚀第二 ILD 7、 CESL6 以及 I LD4形成源漏接触孔， 在源漏接触孔中暴露的源漏外延层 1 D上 /中形成 金属化层 8 (例如 NiS i、 PtS i、 CoS i等金属硅化物） 以降低源漏接触电阻， 填充金属和 /或金属氮化物形成源漏接触塞 9 , 沉积第三 ILD 10并刻蚀形成引 线孔， 在引线孔中填充金属形成引线 11 , 构成器件的字线或位线， 完成最终 的器件结构。 如图 9所示， 最终的 M0SFET器件结构至少包括村底 1、 村底 1上 的栅极绝缘层 2A、 T型金属栅极结构 5A/5B、 T型金属栅极结构两侧的源漏区 (源漏扩展区 1B、 晕状源漏区 1C、 源漏外延层 ID )、 源漏区上的金属化层 8。 M0SFET其余各个部件结构以及相应的材料在上述方法描述中已经详细列出， 在此不再赘述。
[0034] 依照本发明的半导体器件制造方法， 通过形成 T型伪栅极以及 T型栅 极沟槽， 避免了后续金属栅极填充工艺中的悬挂现象以及孔洞形成， 提高了 器件性能。
[0035] 尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人员 可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方 式。 此外， 由所公开的教导可做出许多可能适于特定情形或材料的修改而不 最佳实施方式而公开的特定实施例， 而所公开的器件结构及其制造方法将包 括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种半导体器件制造方法， 包括：
在村底上形成 τ型伪栅极结构；
去除 T型伪栅极结构， 留下 T型栅极沟槽；
在 T型栅极沟槽中填充金属层， 形成 T型金属栅极结构。
2. 如权利要求 1的方法， 其中， 形成 T型伪栅极结构的步骤进一步包括： 在村底上形成栅极绝缘层与伪栅极层构成的伪栅极堆叠结构； 在伪栅极堆叠结构两侧形成栅极侧墙， 栅极侧墙的高度小于伪栅极堆 叠结构的高度， 从而暴露出伪栅极堆叠结构顶部；
在暴露出的伪栅极堆叠结构顶部上以及侧面形成伪栅极外延层， 伪栅 极外延层与伪栅极层共同构成 T型伪栅极结构。
3. 如权利要求 2的方法， 其中， 形成伪栅极外延层的同时， 在栅极侧墙两 侧形成源漏外延层。
4. 如权利要求 3的方法， 其中， 形成源漏外延层的同时或者之后， 对源漏 外延层掺杂形成源漏重掺杂区。
5. 如权利要求 2的方法， 其中， 形成栅极侧墙的步骤进一步包括： 在村底 以及伪栅极层上形成侧墙材料层； 过刻蚀侧墙材料层， 使得形成的栅 极侧墙的高度小于伪栅极堆叠结构的高度。
6. 如权利要求 2的方法， 其中， 在形成伪栅极堆叠结构之后、 形成栅极侧 墙之前，在伪栅极堆叠结构两侧村底中形成源漏扩展区和 /或晕状源漏 区。
7. 如权利要求 1的方法， 其中， 形成 T型伪栅极结构之后、 去除 T型伪栅极 型伪栅极结构。
8. 如权利要求 1的方法，其中，金属层包括功函数调节层与金属栅填充层。
9. 如权利要求 8的方法， 其中， 功函数调节层包括 TiN、 TaN及其组合， 金 属栅填充层包括 Ti、 Ta、 W、 Al、 Cu、 Mo及其组合。
10. 如权利要求 2的方法， 其中， 栅极绝缘层包括高 k材料。
11. 如权利要求 2的方法， 其中， 伪栅极层包括多晶硅、 非晶硅、 微晶硅、 非晶碳、 氢化非晶碳及其组合。
12. 如权利要求 2的方法， 其中， 栅极侧墙包括氮化硅、 氮氧化硅、 DLC及 其组合。
1 3. 如权利要求 2的方法， 其中， T型伪栅极结构的顶部与底部的宽度差不 大于栅极侧墙的宽度。
14. 一种半导体器件， 包括村底、 村底上的高 k材料的栅极绝缘层、 栅极绝 缘层上的 T型金属栅极结构、 以及 T型金属栅极结构两侧的源漏区。
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