WO2014071650A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014071650A1
WO2014071650A1 PCT/CN2012/084814 CN2012084814W WO2014071650A1 WO 2014071650 A1 WO2014071650 A1 WO 2014071650A1 CN 2012084814 W CN2012084814 W CN 2012084814W WO 2014071650 A1 WO2014071650 A1 WO 2014071650A1
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Prior art keywords
layer
semiconductor layer
substrate
semiconductor
fin
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PCT/CN2012/084814
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English (en)
French (fr)
Inventor
朱慧珑
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中国科学院微电子研究所
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Priority to US14/440,463 priority Critical patent/US9397096B2/en
Publication of WO2014071650A1 publication Critical patent/WO2014071650A1/zh

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Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method of fabricating the same. Background technique
  • a stereotype semiconductor device such as a FinFET (Fin Field Effect Transistor) has been proposed.
  • a FinFET Fin Field Effect Transistor
  • a FinFET includes a fin that is formed vertically on a substrate and a gate that intersects the fin. Therefore, the channel region is formed in the fin, and its width is mainly determined by the height of the fin.
  • a method of fabricating a semiconductor device comprising: sequentially forming a first semiconductor layer and a second semiconductor layer on a substrate; patterning the second semiconductor layer to form an initial fin; a semiconductor layer is anisotropically etched to form a meandering lateral recess therein; an isolation layer is formed on the substrate, the spacer layer filling the lateral recess, and in addition to filling the laterally recessed portion Additionally, a top surface of the isolation layer is between the top surface and the bottom surface of the first semiconductor layer to define a fin above the isolation layer; a gate stack spanning the fin is formed on the isolation layer.
  • a semiconductor device comprising: a substrate; a patterned first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, wherein the first semiconductor layer includes a second semiconductor a lateral recess of the layer; an isolation layer formed on the substrate, the isolation fills the lateral recess, and the isolation layer is filled a top surface of the portion other than the lateral recess is lower than a top surface of the first semiconductor layer, higher than a bottom surface of the first semiconductor layer, thereby defining a fin above the isolation layer; and a fin extending over the isolation layer
  • the gate stack comprising: a substrate; a patterned first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, wherein the first semiconductor layer includes a second semiconductor a lateral recess of the layer; an isolation layer formed on the substrate, the isolation fills the lateral recess, and the isolation layer is filled a top surface of the portion other than the lateral recess is lower than a top surface of the first semiconductor layer, higher than a bottom
  • FIGS. 1-15 are schematic views showing a flow of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. detailed description
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • At least one semiconductor layer may be formed on a substrate, for example, by epitaxy.
  • the depth of etching into the substrate can be reduced relative to conventional techniques (even zero, in which case, at least through the A semiconductor layer is formed to form the fins, so that the uniformity of the etching depth can be more easily controlled.
  • the thickness uniformity of the epitaxial layer can be controlled relatively easily, and as a result, the uniformity of the thickness of the finally formed fin can be improved.
  • the at least one semiconductor layer comprises two or more semiconductor layers.
  • adjacent semiconductor layers may have etch selectivity with respect to each other, so that each semiconductor layer can be selectively etched.
  • one of the layers (or layers) may be selectively etched to be narrowed (recessed) laterally.
  • a ⁇ -shaped lateral recess can be formed, for example, by anisotropic etching. This kind The ⁇ -type lateral recess helps to reduce process inconsistencies due to etch recesses.
  • the isolation layer is formed such that the isolation layer can fill the lateral recess, and the isolation layer causes a portion of the one (or more) layer that is narrowed (recessed) to protrude (relative to the top surface of the isolation layer) .
  • the one layer (or layers) narrowed (recessed) is located at the bottom where the fin is finally formed (the portion where the initial fin is located below the one or more layers is surrounded by the isolation layer, thereby no longer functioning The true fin used to form the channel).
  • the subsequently formed barrier between the gate and the fin is thick due to the lateral recess, so that the parasitic capacitance formed is relatively small.
  • the isolation layer may be formed by depositing a dielectric layer on the substrate and then etching back.
  • the dielectric layer can substantially cover the initial fin formed, and the thickness of the dielectric layer at the top of the initial fin is sufficiently smaller than the thickness of the dielectric layer on the substrate, for example, the thickness of the dielectric layer at the top of the initial fin can be less than the thickness of the dielectric layer on the substrate.
  • HDP high density plasma
  • the thickness of the dielectric layer on the top surface of each of the initial fins may be less than one-half the spacing between the fins adjacent thereto.
  • the etching depth can be reduced, so that the etching control precision can be increased.
  • a substrate 1000 is provided.
  • the substrate 1000 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a SiGe substrate, or the like.
  • a bulk Si substrate will be described as an example for convenience of explanation.
  • the surface crystal orientation of the substrate 1000 is taken as, for example, [100].
  • an n-type well 1000-1 and a p-type well 1000-2 may be formed for subsequently forming a p-type device and an n-type device therein, respectively.
  • the n-type well 1000-1 can be formed by implanting an n-type impurity such as P or As in the substrate 1000
  • the p-type well 1000-2 can be formed by implanting a p-type impurity such as B into the substrate 1000. If necessary, annealing can also be performed after the injection.
  • annealing can also be performed after the injection.
  • a first semiconductor layer 1002 is formed on the substrate 1000, for example, by epitaxial growth.
  • the first semiconductor layer 1002 may include SiGe (Ge atom percentage is, for example, about 5-20%) and a thickness of about 10-50 nm.
  • the surface crystal orientation of the first semiconductor layer 1002 is taken as, for example, [100].
  • Epitaxial growth of the first half In the process of the bulk layer it may be doped in situ, for example by B, and doped to p-type. Doping concentration of the first semiconductor layer may be doped with p-type well concentration below the above example can be lE18 - 2E19 cm_ 3. According to an example, to reduce B diffusion, C may be implanted into the p-type first semiconductor layer 1002.
  • a first semiconductor layer on the p-type well region may be shielded by a photoresist (not shown), and an n-type impurity such as As or P may be implanted into the first semiconductor layer on the n-type well region to A semiconductor layer is converted to an n-type and its doping concentration can be higher than the doping concentration of the n-type well below.
  • implant concentration may be 2E18 - 4E19 cm_ 3.
  • the photoresist can then be removed.
  • the n-type first semiconductor layer 1002-1 and the p-type first semiconductor layer 1002-2 are formed
  • the second semiconductor layer 1004 is formed.
  • the second semiconductor layer 1004 may include Si having a thickness of about 20 to 100 nm.
  • the first semiconductor layer may also include Si, and may also be doped as described above.
  • the first semiconductor layer and the underlying substrate and the second semiconductor layer thereon also include the Si material, a certain etch selectivity can be achieved between them due to the difference in doping concentration.
  • a protective layer 1006 may be formed on the second semiconductor layer 1004.
  • the protective layer 1006 may, for example, comprise an oxide (e.g., silicon oxide) having a thickness of about 10-50 nm. This protective layer 1006 can protect the ends of the fins in subsequent processing.
  • the second semiconductor layer 1004 thus formed may be patterned to form an initial fin.
  • a patterned photoresist 1008 is formed as designed on the protective layer 1006.
  • photoresist 1008 is patterned into a series of parallel equally spaced lines.
  • the patterned photoresist 1008 is used as a mask to selectively etch, for example, a reactive ion etching (RIE) protective layer 1006 and a second semiconductor layer 1004 to form an initial fin. Thereafter, the photoresist 1008 can be removed.
  • RIE reactive ion etching
  • the shape of the groove (between the initial fins) formed by etching is shown as a regular rectangular shape, the present disclosure is not limited thereto.
  • the groove may be a frustum shape that tapers from top to bottom.
  • the position and number of initial fins formed are not limited to the example shown in FIG. 2.
  • the first semiconductor layer 1002 may be selectively etched to be laterally recessed with respect to the second semiconductor layer 1004.
  • a protective layer may be formed on the side of the initial fin.
  • a protective layer 1012 may be formed on the sidewall of the initial fin, for example, in the form of a side wall.
  • the protective layer 1012 can include a nitride (eg, silicon nitride) having a thickness of about 5-10 nm.
  • the protective layer 1012 may be formed in the form of a side wall without being formed in the initial fin the top of.
  • the present disclosure is not limited thereto, and a suitable protective layer 1012 may be formed in various forms.
  • a meandering lateral recess is preferably formed in the second semiconductor layer.
  • the amorphized region 1030 may be formed in the first semiconductor layer by ion implantation (indicated by an arrow in FIG. 4). Due to the presence of the initial fins, such amorphized regions 1030 are located substantially between adjacent initial fins; and due to diffusion, extend slightly below the fins, the end faces being substantially C-shaped.
  • Such ion implantation may be accomplished by injecting Ge, implantation depth of about of 5-10 nm, the implantation dose is greater than about 3E14 cm_ 2.
  • the amorphized region 1030 may be selectively etched with respect to the crystal portion in the first semiconductor layer 1002, thereby forming a C-type lateral recess in the first semiconductor layer 1002.
  • the first semiconductor layer 1002 may be further anisotropically etched by such a C-type lateral recess, and thus a meandering lateral recess is formed.
  • anisotropic etching can be performed, for example, by a TMAH solution.
  • the substrate 1000 is also subjected to a certain degree of etching.
  • the laterally concave side walls of the ⁇ type are, for example, along the ⁇ 111 ⁇ crystal plane.
  • the manner of forming the C-shaped lateral recess is not limited to the above example.
  • an isotropic etching for example, wet etching of an oxidizing agent plus an HF-based acidic solution, or isotropic dry etching
  • an anisotropic dry etching such as RIE may be used first. Isotropic dry etching, and so on.
  • the photoresist 1010 may be formed on the substrate, and the photoresist 1010 may be patterned to expose a certain area around the interface between the n-type region and the p-type region. Then, the protective layer, the second semiconductor layer, and the first semiconductor layer existing in the region are removed by selective etching such as RIE. It is also possible to further selectively etch a substrate such as RIE. Thereby an isolation zone is formed between the n-type region and the p-type region, which isolation region can then be filled with a dielectric. Then, the photoresist 1010 can be removed.
  • an initial fin is also formed at the interface between the n-type well 1000-1 and the p-type well 1000-2. This initial fin is also removed due to the isolation forming process shown in FIG. Thus, the structure shown in Fig. 8 is obtained.
  • a gate stack spanning the fins may be formed and the final semiconductor device formed.
  • an isolation layer is first formed on the substrate.
  • Such an isolation layer can be formed, for example, by depositing a dielectric material on the substrate and then performing etch back. In this way, the isolation layer will fill the lateral recess.
  • the etch back depth is controlled such that the etched back dielectric material enables the first semiconductor layer A portion (relative to the top surface of the dielectric layer) protrudes. That is, (except for the portion filling the lateral recess) the top surface of the spacer layer is located below the top surface of the first semiconductor layer and over the bottom surface of the first semiconductor layer.
  • the isolation layer can include a high density plasma (HDP) oxide (eg, silicon oxide).
  • the dielectric material 1014 substantially covers the initial fin (in the case of a plurality of initial fins, substantially filling the gap between the initial fins).
  • the dielectric layer thickness of the initial fin top may be sufficiently smaller than the dielectric layer thickness on the substrate, and generally the dielectric layer thickness of the initial fin top is smaller than the dielectric on the substrate.
  • One third of the layer thickness preferably one quarter.
  • the thickness of the dielectric layer on the top of each initial fin is generally not more than 20 nm, and the thickness of the dielectric layer on the substrate is about 100 nm.
  • the dielectric material 1014 may include an oxide (e.g., silicon oxide) formed by high density plasma (HDP) deposition. Due to the nature of the HDP, the thickness of the dielectric layer (in the direction perpendicular to the substrate) and the dielectric layer of the initial fin side (in the direction parallel to the substrate, ie lateral) can be made during the deposition process. Less than the thickness of the dielectric layer (along the direction perpendicular to the substrate) on the substrate between the initial fins. Because of this property of HDP, HDP deposition is generally not used in conventional techniques to make oxidative isolation.
  • HDP high density plasma
  • the thickness on the top of each initial fin may be less than One-half the spacing between adjacent initial fins. If the spacing between the initial fins is not the same, the thickness of the dielectric layer 1014 at the top of each of the initial fins can be made less than one-half of the smaller of the spacing between the initial fins adjacent thereto.
  • the dielectric material 1014 is etched back. Since the etch back depth of the dielectric material 1014 is relatively small, the control of the etch is relatively easy, and thus the top surface of the fin (in this example, the top surface of the second semiconductor layer 1004) can be more precisely controlled.
  • the distance of the top surface of the isolation layer 1014 (at least partially determines the fin height of the final device and thus the channel width of the final device) is such that the distance remains substantially uniform across the substrate.
  • the isolation layer defines the fins above it. In the example in which the first semiconductor layers 1002-1 and 1002-2 are doped as described above, the corresponding threshold voltage thereof is higher than the threshold voltage corresponding to the second semiconductor layer 1004.
  • the second semiconductor layer can be turned on and the first semiconductor layer cannot be turned on.
  • the fin ultimately used as the device may include only the second semiconductor layer 1004, and the first semiconductor layer may serve as a punch-through barrier to prevent punch-through between the source and drain.
  • protective layer 1006 and dielectric material 1014 comprise the same material, such as an oxide. Therefore, during the etch back of the dielectric material 1014, the protective layer 1006 may be removed at the same time, as shown in FIG. Thereafter, the protective layer 1012 can be removed.
  • a gate stack across the fins can be formed over the isolation layer 1014.
  • this can be done as follows. Specifically, as shown in Fig. 11 (Fig. 11 (b) shows a cross-sectional view taken along line BB' in Fig. 11 (a)), a gate dielectric layer 1016 is formed, for example, by deposition.
  • the gate dielectric layer 1016 can include an oxide having a thickness of about 0.8-1.5 nm. In the example shown in Fig. 11, only the gate dielectric layer 1016 of the " ⁇ " shape is shown. However, the gate dielectric layer 1016 may also include a portion extending over the surface of the isolation layer 1014.
  • gate conductor layer 1018 is formed, for example, by deposition.
  • gate conductor layer 1018 can comprise polysilicon.
  • the gate conductor layer 1018 may fill the gap between the fins and may be subjected to a planarization process such as chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the gate conductor layer 1018 is patterned to form a gate stack.
  • the gate conductor layer 1018 is patterned into a strip shape that intersects the fins.
  • the patterned gate conductor layer 1018 can also be used as a mask to further pattern the gate dielectric layer 1016.
  • a halo implant and an extension implant may be performed using the gate conductor as a mask.
  • a spacer 1020 may be formed on the sidewall of the gate conductor layer 1018.
  • the spacer 1020 can be formed by depositing a nitride having a thickness of about 5 to 30 nm and then performing RIE on the nitride.
  • the side wall 1020 is not substantially formed on the side wall of the fin.
  • source/drain (S/D) implants can be performed using the gate conductors and sidewall spacers as masks. Subsequently, the implanted ions can be activated by annealing to form source/drain regions. Thus, the semiconductor device according to this embodiment is obtained. As shown in FIG.
  • the semiconductor device may include: a substrate; a patterned first semiconductor layer and a second semiconductor layer sequentially formed on the substrate, wherein the first semiconductor layer includes a lateral shape transverse to the second semiconductor layer a spacer formed on the substrate, the isolation filling the lateral recess, the top surface of the portion of the isolation layer except the filling lateral recess is lower than the top surface of the first semiconductor layer, higher than the first semiconductor a bottom surface of the layer to define a fin above the isolation layer; and a gate stack across the fin formed on the isolation layer.
  • an n-type impurity may be doped in the first semiconductor layer
  • a p-type impurity may be doped in the first semiconductor layer.
  • the doped first semiconductor layer can serve as a feedthrough barrier.
  • the gate stack is directly formed.
  • the present disclosure is not limited to this.
  • an alternative gate process is equally applicable to the present disclosure.
  • the gate dielectric layer 1016 and the gate conductor layer 1018 formed in FIG. 11 are a sacrificial gate dielectric layer and a sacrificial gate conductor layer.
  • the processing can be performed in the same manner as described above in connection with Figs.
  • a dielectric layer 1022 is formed, for example, by deposition.
  • the dielectric layer 1022 can comprise, for example, an oxide.
  • the dielectric layer 1022 is subjected to a planarization process such as CMP.
  • the CMP can be stopped at the sidewall spacer 1020 to expose the sacrificial gate conductor 1018.
  • Fig. 14 shows a cross-sectional view taken along line BB' in Fig. 14 (a)
  • Fig. 14 (c) shows a cross-sectional view taken along line CC' in Fig. 14 (a)
  • the sacrificial gate conductor 1018 is selectively removed, such as by a TMAH solution, such that a void 1024 is formed inside the sidewall spacer 1020.
  • the sacrificial gate dielectric layer 1016 can be further removed.
  • a final gate stack is formed by forming a gate dielectric layer 1026 and a gate conductor layer 1028 in the voids 1024.
  • the gate dielectric layer 1026 can comprise a high K gate dielectric such as HfO 2 having a thickness of about 1-5 nm.
  • Gate conductor layer 1028 can include a metal gate conductor.
  • a function adjustment layer (not shown) can also be formed between the gate dielectric layer 1022 and the gate conductor layer 1024.
  • the gate dielectric layer 1026 is shown as a thin layer at the bottom of the void 1024. However, the gate dielectric layer 1026 may also be formed on the sidewalls of the void 1024 to surround the gate conductor layer 1028.
  • the semiconductor device is substantially identical in structure to the semiconductor device shown in Fig. 11 except that the gate stack is formed in a different manner.

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Abstract

一种半导体器件结构及其制造方法，包括：在衬底（1000）上依次形成第一半导体层（1002）和第二半导体层（1004）；对第二半导体层进行构图，以形成初始鳍；对第一半导体层进行各向异性蚀刻，在其中形成∑型横向凹入；在衬底上形成隔离层（1014），填充横向凹入，隔离层除填充横向凹入之外的部分的顶面，位于第一半导体层的顶面和底面之间，从而限定出位于隔离层上方的鳍；以及在隔离层上形成横跨鳍的栅堆叠。

Description

半导体器件及其制造方法
本申请要求了 2012年 11月 9日提交的、 申请号为 201210447834.8、 发明名称为
"半导体器件及其制造方法"的中国专利申请的优先权， 其全部内容通过引用结合在 本申请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及一种半导体器件及其制造方法。 背景技术
随着平面型半导体器件的尺寸越来越小， 短沟道效应愈加明显。 为此， 提出了立 体型半导体器件如 FinFET (鰭式场效应晶体管）。 一般而言， FinFET包括在衬底上竖 直形成的鰭以及与鰭相交的栅极。 因此， 沟道区形成于鰭中， 且其宽度主要由鰭的高 度决定。 然而， 在集成电路制造工艺中， 难以控制晶片上形成的鰭的高度相同， 从而 导致晶片上器件性能的不一致性。
另一方面， 在鰭的底部， 栅与体由于之间的电介质而形成寄生电容。 这种寄生电 容过大， 会使得器件的响应时间过长。 发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面， 提供了一种制造半导体器件的方法， 包括： 在衬底上依 次形成第一半导体层和第二半导体层； 对第二半导体层进行构图， 以形成初始鰭； 对 第一半导体层进行各向异性刻蚀，以在其中形成∑型横向凹入；在衬底上形成隔离层， 所述隔离层填充所述横向凹入， 且除了填充所述横向凹入的部分之外， 所述隔离层的 顶面位于第一半导体层的顶面和底面之间， 从而限定出位于隔离层上方的鰭； 在隔离 层上形成横跨鰭的栅堆叠。
根据本公开的另一方面， 提供了一种半导体器件， 包括： 衬底； 在衬底上依次形 成的构图的第一半导体层和第二半导体层， 其中第一半导体层包括相对于第二半导体 层的∑型横向凹入； 在衬底上形成的隔离层， 该隔离填充所述横向凹入， 隔离层除填 充横向凹入之外的部分的顶面低于第一半导体层的顶面、 高于第一半导体层的底面， 从而限定出位于隔离层上方的鰭； 以及在隔离层上形成的横跨鰭的栅堆叠。 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和 优点将更为清楚， 在附图中：
图 1-15是示出了根据本公开实施例的制造半导体器件流程的示意图。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是示例性 的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知结构和技术的 描述， 以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。 这些图并非是按比例绘制 的， 其中为了清楚表达的目的， 放大了某些细节， 并且可能省略了某些细节。 图中所 示出的各种区域、 层的形状以及它们之间的相对大小、 位置关系仅是示例性的， 实际 中可能由于制造公差或技术限制而有所偏差， 并且本领域技术人员根据实际所需可以 另外设计具有不同形状、 大小、 相对位置的区域 /层。
在本公开的上下文中， 当将一层 /元件称作位于另一层 /元件 "上" 时， 该层 /元件 可以直接位于该另一层 /元件上， 或者它们之间可以存在居中层 /元件。 另外， 如果在 一种朝向中一层 /元件位于另一层 /元件"上"， 那么当调转朝向时， 该层 /元件可以位于 该另一层 /元件 "下"。
根据本公开的实施例，可以在衬底上例如通过外延形成至少一个半导体层。这样， 在例如通过刻蚀来构图鰭时， 为形成相同高度的鰭， 刻蚀进入衬底中的深度相对于常 规技术可以减小 （甚至可以为零， 这种情况下， 完全通过所述至少一个半导体层来形 成鰭）， 从而可以更加容易控制刻蚀深度的一致性。 此外， 外延层的厚度一致性可以 相对容易地控制， 结果， 可以改善最终形成的鰭的厚度的一致性。
根本公开的优选实施例， 所述至少一个半导体层包括两个或更多的半导体层。 在 这些半导体层中， 相邻的半导体层可以相对于彼此具有刻蚀选择性， 从而可以选择性 刻蚀每一半导体层。 在形成鰭之后， 可以选择性刻蚀其中的某一层 （或多层）， 使其 横向变窄 （凹入）。 特别是， 例如可以通过各向异性刻蚀， 来形成∑型横向凹入。 这种 ∑型横向凹入有助于减小由于刻蚀凹入而导致的工艺不一致性。
另外， 如此形成隔离层， 使得隔离层可以填充所述横向凹入， 并且隔离层使得变 窄 （凹入） 的所述一层 （或多层） 的一部分 （相对于该隔离层顶面） 突出。 从而， 变 窄 （凹入） 的所述一层 （或多层） 位于最终形成鰭的底部 （初始形成鰭位于所述一层 或多层之下的部分由于被隔离层包围， 从而不再充当用来形成沟道的真正鰭）。
这样， 在最终形成鰭的底部， 由于所述横向凹入， 随后形成的栅与鰭之间的隔离 层较厚， 从而形成的寄生电容相对较小。
根据本公开的实施例， 隔离层可以通过在衬底上淀积电介质层然后回蚀来形成。 电介质层可以基本上覆盖所形成的初始鰭， 且位于初始鰭顶部的电介质层厚度充分小 于位于衬底上的电介质层厚度， 例如初始鰭顶部的电介质层厚度可以小于位于衬底上 的电介质层厚度的三分之一， 优选为四分之一。 例如， 这可以通过高密度等离子体 (HDP) 淀积来实现。 另外， 在形成多个初始鰭的情况下， 位于每一初始鰭的顶面之 上的电介质层的厚度可以小于与其相邻的鰭之间间距的二分之一。 这样， 在随后的回 蚀中， 可以减少刻蚀深度， 从而能够增加刻蚀控制精度。
本公开可以各种形式呈现， 以下将描述其中一些示例。
如图 1所示， 提供衬底 1000。 该衬底 1000可以是各种形式的衬底， 例如但不限于 体半导体材料衬底如体 Si衬底、 绝缘体上半导体 （SOI) 衬底、 SiGe衬底等。 在以下 的描述中， 为方便说明， 以体 Si衬底为例进行描述。 在本发明的一个实施例中， 衬底 1000的表面晶向例如取为 [100]。
在衬底 1000中， 可以形成 n型阱 1000-1和 p型阱 1000-2， 以供随后在其中分别形成 p 型器件和 n型器件。 例如， n型阱 1000-1可以通过在衬底 1000中注入 n型杂质如 P或 As来 形成， p型阱 1000-2可以通过在衬底 1000中注入 p型杂质如 B来形成。 如果需要， 在注 入之后还可以进行退火。 本领域技术人员能够想到多种方式来形成 n型阱、 p型阱， 在 此不再赘述。
这里需要指出的是， 尽管在以下描述中说明了分别在 n型阱和 p型阱中形成互补器 件的工艺， 但是本公开不限于此。 例如， 本公开同样适用于非互补工艺。 而且， 以下 涉及互补器件的一些处理， 在某些实现方式中并非是必须的。
在衬底 1000上， 例如通过外延生长， 形成第一半导体层 1002。 例如， 第一半导体 层 1002可以包括 SiGe (Ge原子百分比例如为约 5-20%)， 厚度为约 10-50nm。 在本发明 的一个实施例中， 第一半导体层 1002的表面晶向例如取为 [100]。在外延生长第一半导 体层的过程中， 可以对其进行原位掺杂， 例如通过 B而掺杂为 p型。 第一半导体层的掺 杂浓度可以高于之下的 p型阱的掺杂浓度， 例如可为 lE18 - 2E19 cm_3。 根据一示例， 为降低 B扩散， 可以在 p型第一半导体层 1002中注入 C。
然后， 可以通过光刻胶 （未示出） 遮挡 p型阱区上的第一半导体层， 并向 n型阱区 上的第一半导体层注入 n型杂质如 As或 P， 以将该部分第一半导体层转换为 n型， 且其 掺杂浓度可以高于之下的 n型阱的掺杂浓度。 注入浓度例如可以是 2E18 - 4E19 cm_3。 之后可以去除光刻胶。 于是， 形成了 n型第一半导体层 1002-1和 p型第一半导体层 1002-2
接下来， 在第一半导体层 1002 (包括 1002-1和 1002-2) 上， 例如通过外延生长， 形成第二半导体层 1004。 例如， 第二半导体层 1004可以包括 Si， 厚度为约 20-100nm。
根据本公开的另一实施例， 第一半导体层也可以包括 Si， 并且也可以同样地如上 所述进行掺杂。 尽管第一半导体层与之下的衬底和之上的第二半导体层同样包括 Si材 料， 但是由于掺杂浓度的不同， 它们之间也可以实现一定的刻蚀选择性。
在第二半导体层 1004上， 可以形成保护层 1006。 保护层 1006例如可以包括氧化物 (例如， 氧化硅）， 厚度为约 10-50nm。 这种保护层 1006可以在随后的处理中保护鰭的 端部。
随后， 可以对如此形成的第二半导体层 1004进行构图， 以形成初始鰭。 例如， 这 可以如下进行。 具体地， 在保护层 1006上按设计形成构图的光刻胶 1008。 通常， 光刻 胶 1008被构图为一系列平行的等间距线条。 然后， 如图 2所示， 以构图的光刻胶 1008 为掩模， 依次选择性刻蚀例如反应离子刻蚀 （RIE)保护层 1006、 第二半导体层 1004， 从而形成初始鰭。 之后， 可以去除光刻胶 1008。
这里需要指出的是， 尽管在图 2的示例中， 将通过刻蚀所形成的 （初始鰭之间的） 沟槽的形状示出为规则矩形形状， 但本公开不限于此。 例如， 沟槽可以是从上到下逐 渐变小的锥台形。 另外， 所形成的初始鰭的位置和数目不限于图 2所示的示例。
为了减小最终形成鰭底部的寄生电容， 可以对第一半导体层 1002进行选择性刻 蚀， 以使其相对于第二半导体层 1004横向凹入。 为了确保在对第一半导体层 1002进行 刻蚀过程中不损坏初始鰭， 可以在初始鰭的侧面上形成保护层。 具体地， 如图 3所示， 例如可以按侧墙的形式， 在初始鰭的侧壁上形成保护层 1012。 例如， 保护层 1012可以 包括氮化物 （例如， 氮化硅）， 厚度为约 5-10nm。 在图 3所示的示例中， 由于初始鰭的 顶部已经存在保护层 1006， 因此保护层 1012可以侧墙形式形成， 而没有形成在初始鰭 的顶部。 但是， 本公开不限于此， 可以各种形式形成适当的保护层 1012。
当然， 如果对第一半导体层的刻蚀剂相对于第二半导体层、 衬底具有足够的刻蚀 选择性， 可以省略这种保护层。
为了降低工艺变化， 优选地在第二半导体层中形成∑型横向凹入。 本领域中存在 多种方式来形成∑型横向凹入， 以下仅描述一种示例。 具体地， 如图 4所示， 可以通过 离子注入 （图 4中箭头所示）， 来在第一半导体层中形成非晶化区域 1030。 由于初始鰭 的存在， 这种非晶化区域 1030基本上位于相邻的初始鰭之间； 且由于扩散， 而略微延 伸到鰭之下， 端面基本上呈 C型。 例如， 这种离子注入可以通过注入 Ge来完成， 注入 深度为约 5-10nm， 注入剂量大于约 3E14 cm_2。 然后， 如图 5所示， 可以相对于第一半 导体层 1002中的晶体部分， 来选择性刻蚀非晶化区域 1030， 从而在第一半导体层 1002 中形成 C型横向凹入。 之后， 如图 6所示， 可以通过这种 C型横向凹入， 进一步对第一 半导体层 1002进行各向异性刻蚀， 并因此形成∑型横向凹入。 这种各向异性刻蚀例如 可以通过 TMAH溶液来进行。 在这种情况下， 衬底 1000也经受了一定程度的刻蚀。 在 本发明的一个实施例中， ∑型横向凹入的侧壁例如沿着 { 111 }晶面。
这里需要指出的是， 形成 C型横向凹入的方式不限于上述示例。 例如， 可以采用 各向同性的刻蚀 (例如，氧化剂加 HF基酸性溶液的湿法刻蚀，或者各向同性干法刻蚀）， 或者先采用 RIE等各向异性的干法刻蚀然后采用各向同性干法刻蚀， 等等。
另外， 在互补工艺的情况下， 还可以如图 7所示， 来在 n型区域和 p型区域之间形 成隔离。 具体地， 可以在衬底上形成光刻胶 1010， 并对光刻胶 1010进行构图， 以露出 n型区域和 p型区域之间界面周围的一定区域。 然后， 通过选择性刻蚀例如 RIE， 去除 该区域存在的保护层、第二半导体层、第一半导体层。也可以进一步选择性刻蚀如 RIE 衬底。 从而在 n型区域和 p型区域之间形成隔离地带， 该隔离地带随后可以被电介质所 填充。 然后， 可以去除光刻胶 1010。
在图 2所示的示例中， 在 n型阱 1000-1和 p型阱 1000-2之间的界面处， 也形成了初始 鰭。 由于图 7所示的隔离形成工艺， 该初始鰭也被去除。 于是， 得到了图 8所示的结构。
在通过上述处理形成具有横向凹入的鰭之后， 可以形成横跨鰭的栅堆叠， 并形成 最终的半导体器件。
为了隔离栅堆叠和衬底， 在衬底上首先形成隔离层。 这种隔离层例如可以通过在 衬底上淀积电介质材料， 且然后进行回蚀来形成。 这样， 隔离层会填充横向凹入。 另 外， 在回蚀过程中， 控制回蚀深度， 使得回蚀后的电介质材料能够使第一半导体层的 一部分 （相对于电介质层的顶面） 突出。 也即， （除了填充横向凹入的部分之外） 隔 离层的顶面位于第一半导体层的顶面之下， 且位于第一半导体层的底面之上。 例如， 隔离层可以包括高密度等离子体 （HDP) 氧化物 （例如， 氧化硅）。
在此， 为了改善回蚀之后电介质层 （顶面的） 高度的一致性， 并因此改善最终形 成的鰭的高度的一致性， 如图 9所示， 在淀积电介质材料 1014的过程中， 使得电介质 材料 1014基本上覆盖初始鰭 （在多个初始鰭的情况下， 基本上填充初始鰭之间的间 隙）。 根据本公开的实施例， 可以如此淀积， 使得初始鰭顶部的电介质层厚度充分小 于位于衬底上的电介质层厚度， 并且一般来说初始鰭顶部的电介质层厚度都小于位于 衬底上的电介质层厚度的三分之一， 优选为四分之一。 例如， 每一初始鰭顶部的电介 质层厚度一般不大于 20nm， 而位于衬底上的电介质层厚度可达 lOOnm左右。
根据本公开的一示例， 电介质材料 1014可以包括通过高密度等离子体 （HDP) 淀 积形成的氧化物 （例如， 氧化硅）。 由于 HDP的特性， 在淀积过程中可以使得初始鰭 顶部的电介质层 （沿垂直于衬底方向的） 厚度和初始鰭侧面的电介质层 （沿平行于衬 底的方向， 即横向的） 厚度要小于初始鰭之间衬底上的电介质层 （沿垂直于衬底方向 的） 厚度。 因为 HDP的这种特性， 在常规技术中通常并不采用 HDP淀积来制作氧化隔 离。
在此，例如可以通过控制淀积条件，使得电介质层 1014在基本上覆盖初始鰭时（或 者， 基本上填充初始鰭之间的空隙时）， 位于每一初始鰭顶部上的厚度可以小于与其 相邻的初始鰭之间间距的二分之一。 如果初始鰭之间的间距并不相同， 则可以使电介 质层 1014位于每一初始鰭顶部的厚度小于与其相邻的初始鰭之间间距中较小间距的 二分之一。
随后， 如图 10所示， 对电介质材料 1014进行回蚀。 由于电介质材料 1014的回蚀深 度相对较小， 从而对该刻蚀的控制相对容易， 并因此可以更加精确地控制从鰭的顶面 (在该示例中， 第二半导体层 1004的顶面） 到隔离层 1014的顶面的距离 （至少部分地 决定最终器件的鰭高度并因此决定最终器件的沟道宽度）， 使得该距离在衬底上基本 保持一致。 这样， 隔离层就限定了位于其上方的鰭。 在第一半导体层 1002-1和 1002-2 是如上所述进行掺杂的示例中， 其对应的阈值电压要高于第二半导体层 1004对应的阈 值电压。 因此， 通过控制栅极控制电压， 可以使得第二半导体层导通而第一半导体层 并不能导通。 这样， 最终用作器件的鰭可以仅包括第二半导体层 1004， 且第一半导体 层可以充当穿通阻挡层， 防止源漏之间的穿通。 在一个示例中，保护层 1006和电介质材料 1014包括相同的材料， 如氧化物。因此， 在对电介质材料 1014回蚀的过程中，可能同时去除了保护层 1006， 如图 10所示。之后， 可以去除保护层 1012。
随后， 可以在隔离层 1014上形成横跨鰭的栅堆叠。 例如， 这可以如下进行。 具体 地， 如图 11所示 （图 11 (b) 示出了沿图 11 ( a) 中 BB'线的截面图）， 例如通过淀积， 形成栅介质层 1016。 例如， 栅介质层 1016可以包括氧化物， 厚度为约 0.8-1.5nm。 在图 11所示的示例中， 仅示出了 " Π "形的栅介质层 1016。 但是， 栅介质层 1016也可以包 括在隔离层 1014的表面上延伸的部分。 然后， 例如通过淀积， 形成栅导体层 1018。 例 如， 栅导体层 1018可以包括多晶硅。 栅导体层 1018可以填充鰭之间的间隙， 并可以进 行平坦化处理例如化学机械抛光 （CMP)。 之后， 对栅导体层 1018进行构图， 以形成 栅堆叠。 在图 8的示例中， 栅导体层 1018被构图为与鰭相交的条形。 根据另一实施例， 还可以构图后的栅导体层 1018为掩模， 进一步对栅介质层 1016进行构图。
如图 11 (b) 中的椭圆虚线圈所示， 在鰭的底部与栅导体 1018之间存在相对较厚 的隔离层 1014， 从而产生的寄生电容相对较小。
在形成构图的栅导体之后， 例如可以栅导体为掩模， 进行暈圈 （halo) 注入和延 伸区 （extension) 注入。
接下来， 如图 12 (图 12 (b) 示出了沿图 12 ( a) 中 BB'线的截面图） 所示， 可以 在栅导体层 1018的侧壁上形成侧墙 1020。 例如， 可以通过淀积形成厚度约为 5-30nm的 氮化物， 然后对氮化物进行 RIE， 来形成侧墙 1020。 本领域技术人员知道多种方式来 形成这种侧墙， 在此不再赘述。
在鰭之间的沟槽为从上到下逐渐变小的锥台形时 （由于刻蚀的特性， 通常为这样 的情况）， 侧墙 1020基本上不会形成于鰭的侧壁上。
在形成侧墙之后， 可以栅导体及侧墙为掩模， 进行源 /漏 ( S/D) 注入。 随后， 可 以通过退火， 激活注入的离子， 以形成源 /漏区。 这样， 就得到了根据该实施例的半导 体器件。 如图 12所示， 该半导体器件可以包括： 衬底； 在衬底上依次形成的构图的第 一半导体层和第二半导体层， 其中第一半导体层包括相对于第二半导体层的∑型横向 凹入； 在衬底上形成的隔离层， 该隔离填充所述横向凹入， 隔离层除填充横向凹入之 外的部分的顶面低于第一半导体层的顶面、 高于第一半导体层的底面， 从而限定出位 于隔离层上方的鰭； 以及在隔离层上形成的横跨鰭的栅堆叠。 对于 p型器件， 第一半 导体层中可以掺杂 n型杂质； 对于 n型器件， 第一半导体层中可以掺杂 p型杂质。 这种 掺杂的第一半导体层可以充当穿通阻挡层。
在上述实施例中， 在形成鰭之后， 直接形成了栅堆叠。 本公开不限于此。 例如， 替代栅工艺同样适用于本公开。
根据本公开的另一实施例， 在图 11中形成的栅介质层 1016和栅导体层 1018为牺牲 栅介质层和牺牲栅导体层。 接下来， 可以同样按以上结合图 11、 12描述的方法来进行 处理。
接下来， 如图 13 (图 13 (b) 示出了沿图 13 (a) 中 BB'线的截面图） 所示， 例如 通过淀积， 形成电介质层 1022。 该电介质层 1022例如可以包括氧化物。 随后， 对该电 介质层 1022进行平坦化处理例如 CMP。该 CMP可以停止于侧墙 1020， 从而露出牺牲栅 导体 1018。
随后， 如图 14 (图 14 (b) 示出了沿图 14 (a) 中 BB'线的截面图， 图 14 (c) 示出 了沿图 14 (a) 中 CC'线的截面图） 所示， 例如通过 TMAH溶液， 选择性去除牺牲栅导 体 1018， 从而在侧墙 1020内侧形成了空隙 1024。 根据另一示例， 还可以进一步去除牺 牲栅介质层 1016。
然后， 如图 15 (图 15 (b) 示出了沿图 15 (a) 中 BB'线的截面图， 图 15 (c) 示出 了沿图 15 (a) 中 CC'线的截面图） 所示， 通过在空隙 1024中形成栅介质层 1026和栅导 体层 1028， 形成最终的栅堆叠。 栅介质层 1026可以包括高 K栅介质例如 Hf02， 厚度为 约 l-5nm。 栅导体层 1028可以包括金属栅导体。 优选地， 在栅介质层 1022和栅导体层 1024之间还可以形成功函数调节层 （未示出）。
这里需要指出的是， 在图 15中， 将栅介质层 1026示出为空隙 1024底部的一薄层。 但是， 栅介质层 1026还可以形成在空隙 1024的侧壁上， 从而包围栅导体层 1028。
这样， 就得到了根据该实施例的半导体器件。 该半导体器件与图 11所示的半导体 器件在结构上基本相同， 除了栅堆叠按不同方式形成之外。
在以上的描述中， 对于各层的构图、 刻蚀等技术细节并没有做出详细的说明。 但 是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。 另外， 为了形成同一结构， 本领域技术人员还可以设计出与以上描述的方法并不完全 相同的方法。 另外， 尽管在以上分别描述了各实施例， 但是这并不意味着各个实施例 中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。 但是， 这些实施例仅仅是为了说明的目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价物限定。 不脱 离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这些替代和修改都应落 在本公开的范围之内。

Claims

权 利 要 求
1. 一种制造半导体器件的方法， 包括：
在衬底上依次形成第一半导体层和第二半导体层；
对第二半导体层进行构图， 以形成初始鰭；
对第一半导体层进行各向异性刻蚀， 以在其中形成∑型横向凹入；
在衬底上形成隔离层， 所述隔离层填充所述横向凹入， 且除了填充所述横向凹入 的部分之外， 所述隔离层的顶面位于第一半导体层的顶面和底面之间， 从而限定出位 于隔离层上方的鰭；
在隔离层上形成横跨鰭的栅堆叠。
2. 根据权利要求 1所述的方法， 其中， 对第一半导体层进行各向异性刻蚀包 括：
对第一半导体层进行刻蚀， 以在其中形成 c型横向凹入； 以及
通过所述 C型横向凹入， 对第一半导体层进行各向异性刻蚀， 以形成∑型横向凹 入。
3. 根据权利要求 2所述的方法， 其中， 形成 C型横向凹入包括：
通过离子注入， 在第一半导体层中形成非晶化区域； 以及
去除所述非晶化区域， 以形成 C型横向凹入。
4. 根据权利要求 1所述的方法， 其中， 在形成初始鰭之后， 在对第一半导体 层进行各向异性刻蚀之前， 该方法还包括：
在鰭的侧面上形成保护层。
5. 根据权利要求 1所述的方法， 其中， 在构图初始鰭之前， 该方法还包括： 在第二半导体层上形成保护层。
6. 根据权利要求 1所述的方法， 其中， 形成隔离层包括：
在衬底上淀积电介质层， 使得电介质层实质上覆盖初始鰭， 其中位于初始鰭顶部 的电介质层厚度充分小于位于衬底上的电介质层厚度； 以及
对电介质层进行回蚀。
7. 根据权利要求 6所述的方法， 其中， 位于初始鰭顶部的电介质层厚度小于 位于衬底上的电介质层厚度的三分之一。
8. 根据权利要求 6所述的方法， 其中， 通过高密度等离子体（HDP)淀积形 成电介质层。
9. 根据权利要求 6所述的方法， 其中， 在衬底上形成多个初始鰭， 且位于每 一初始鰭顶部的电介质层厚度小于与其相邻的初始鰭之间间距的二分之一。
10. 根据权利要求 1所述的方法， 其中， 对于 p型器件， 第一半导体层中掺杂 n型杂质； 对于 n型器件， 第一半导体层中掺杂 p型杂质。
11. 一种半导体器件， 包括：
衬底；
在衬底上依次形成的构图的第一半导体层和第二半导体层， 其中第一半导体层包 括相对于第二半导体层的∑型横向凹入；
在衬底上形成的隔离层， 该隔离填充所述横向凹入， 隔离层除填充横向凹入之外 的部分的顶面低于第一半导体层的顶面、 高于第一半导体层的底面， 从而限定出位于 隔离层上方的鰭； 以及
在隔离层上形成的横跨鰭的栅堆叠。
12. 根据权利要求 11所述的半导体器件， 其中，
衬底包括体 Si;
第一半导体层包括 Si或 SiGe， 且被掺杂形成穿通阻挡部；
第二半导体层包括 Si。
13. 根据权利要求 12所述的半导体器件， 其中， 对于 p型器件， 第一半导体 层中掺杂 n型杂质； 对于 n型器件， 第一半导体层中掺杂 p型杂质。
14. 根据权利要求 11所述的半导体器件， 其中该半导体器件包括多个鰭， 其 中每一鰭的顶面大致持平， 隔离层的顶面大致持平。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2947695A1 (en) * 2014-05-23 2015-11-25 Broadcom Corporation Finfet with undoped body bulk
US9812394B2 (en) 2015-10-12 2017-11-07 International Business Machines Corporation Faceted structure formed by self-limiting etch

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150017774A1 (en) * 2013-07-10 2015-01-15 Globalfoundries Inc. Method of forming fins with recess shapes
US10290636B2 (en) * 2014-08-18 2019-05-14 Stmicroelectronics, Inc. Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods
CN105428238B (zh) * 2014-09-17 2019-01-22 中芯国际集成电路制造(上海)有限公司 一种FinFET器件及其制作方法和电子装置
US9954107B2 (en) 2015-05-05 2018-04-24 International Business Machines Corporation Strained FinFET source drain isolation
US10903210B2 (en) * 2015-05-05 2021-01-26 International Business Machines Corporation Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture
US9853101B2 (en) 2015-10-07 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Strained nanowire CMOS device and method of forming
CN106816379B (zh) * 2015-11-27 2021-09-07 联华电子股份有限公司 具有外延结构的半导体元件及其制作方法
US9608069B1 (en) 2016-04-13 2017-03-28 Intenational Business Machines Corporation Self aligned epitaxial based punch through control
US9647123B1 (en) * 2016-10-14 2017-05-09 International Business Machines Corporation Self-aligned sigma extension regions for vertical transistors
US10388763B2 (en) * 2016-12-15 2019-08-20 Taiwan Semiconductor Manufacturing Co., Ltd. Manufacturing of semiconductor fin structure and manufacturing method of semiconductor device
DE102017127354A1 (de) * 2016-12-15 2018-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-bauelement und herstellungsverfahren dafür
US11908863B2 (en) * 2018-12-31 2024-02-20 Unist(Ulsan National Institute Of Science And Technology) Transistor element, ternary inverter apparatus comprising same, and method for producing same
CN112786452B (zh) * 2019-11-08 2023-12-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040150029A1 (en) * 2003-02-04 2004-08-05 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
CN102446974A (zh) * 2010-10-13 2012-05-09 台湾积体电路制造股份有限公司 Finfet及其制造方法
CN102656699A (zh) * 2009-12-23 2012-09-05 英特尔公司 非平面锗量子阱装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6787854B1 (en) * 2003-03-12 2004-09-07 Advanced Micro Devices, Inc. Method for forming a fin in a finFET device
US7709341B2 (en) * 2006-06-02 2010-05-04 Micron Technology, Inc. Methods of shaping vertical single crystal silicon walls and resulting structures
US8264032B2 (en) * 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8729627B2 (en) * 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
DE102010064283B4 (de) * 2010-12-28 2012-12-27 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zur Herstellung eines selbstjustierten Steg-Transistors auf einem Vollsubstrat durch eine späte Stegätzung
US20120199888A1 (en) * 2011-02-09 2012-08-09 United Microelectronics Corporation Fin field-effect transistor structure
US8916909B2 (en) * 2012-03-06 2014-12-23 Infineon Technologies Austria Ag Semiconductor device and method for fabricating a semiconductor device
CN103545212B (zh) * 2012-07-16 2016-09-21 中国科学院微电子研究所 半导体器件制造方法
US9299837B2 (en) * 2013-05-22 2016-03-29 Globalfoundries Inc. Integrated circuit having MOSFET with embedded stressor and method to fabricate same
CN103346086B (zh) * 2013-05-31 2016-08-10 上海华力微电子有限公司 嵌入式锗硅结构的制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040150029A1 (en) * 2003-02-04 2004-08-05 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
CN102656699A (zh) * 2009-12-23 2012-09-05 英特尔公司 非平面锗量子阱装置
CN102446974A (zh) * 2010-10-13 2012-05-09 台湾积体电路制造股份有限公司 Finfet及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2947695A1 (en) * 2014-05-23 2015-11-25 Broadcom Corporation Finfet with undoped body bulk
US9812394B2 (en) 2015-10-12 2017-11-07 International Business Machines Corporation Faceted structure formed by self-limiting etch

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