CN103811341A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103811341A
CN103811341A CN201210447834.8A CN201210447834A CN103811341A CN 103811341 A CN103811341 A CN 103811341A CN 201210447834 A CN201210447834 A CN 201210447834A CN 103811341 A CN103811341 A CN 103811341A
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semiconductor layer
fin
substrate
separator
layer
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CN103811341B (zh
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朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to PCT/CN2012/084814 priority patent/WO2014071650A1/zh
Priority to US14/440,463 priority patent/US9397096B2/en
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Abstract

本发明公开了一种半导体器件及其制造方法。一示例方法可以包括：在衬底上依次形成第一半导体层和第二半导体层；对第二半导体层进行构图，以形成初始鳍；对第一半导体层进行各向异性刻蚀，以在其中形成∑型横向凹入；在衬底上形成隔离层，所述隔离层填充所述横向凹入，且除了填充所述横向凹入的部分之外，所述隔离层的顶面位于第一半导体层的顶面和底面之间，从而限定出位于隔离层上方的鳍；在隔离层上形成横跨鳍的栅堆叠。

Description

半导体器件及其制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种半导体器件及其制造方法。
背景技术
随着平面型半导体器件的尺寸越来越小，短沟道效应愈加明显。为此，提出了立体型半导体器件如FinFET(鳍式场效应晶体管)。一般而言，FinFET包括在衬底上竖直形成的鳍以及与鳍相交的栅极。因此，沟道区形成于鳍中，且其宽度主要由鳍的高度决定。然而，在集成电路制造工艺中，难以控制晶片上形成的鳍的高度相同，从而导致晶片上器件性能的不一致性。
另一方面，在鳍的底部，栅与体由于之间的电介质而形成寄生电容。这种寄生电容过大，会使得器件的响应时间过长。
发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上依次形成第一半导体层和第二半导体层；对第二半导体层进行构图，以形成初始鳍；对第一半导体层进行各向异性刻蚀，以在其中形成∑型横向凹入；在衬底上形成隔离层，所述隔离层填充所述横向凹入，且除了填充所述横向凹入的部分之外，所述隔离层的顶面位于第一半导体层的顶面和底面之间，从而限定出位于隔离层上方的鳍；在隔离层上形成横跨鳍的栅堆叠。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底；在衬底上依次形成的构图的第一半导体层和第二半导体层，其中第一半导体层包括相对于第二半导体层的∑型横向凹入；在衬底上形成的隔离层，该隔离填充所述横向凹入，隔离层除填充横向凹入之外的部分的顶面低于第一半导体层的顶面、高于第一半导体层的底面，从而限定出位于隔离层上方的鳍；以及在隔离层上形成的横跨鳍的栅堆叠。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-15是示出了根据本公开实施例的制造半导体器件流程的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，可以在衬底上例如通过外延形成至少一个半导体层。这样，在例如通过刻蚀来构图鳍时，为形成相同高度的鳍，刻蚀进入衬底中的深度相对于常规技术可以减小(甚至可以为零，这种情况下，完全通过所述至少一个半导体层来形成鳍)，从而可以更加容易控制刻蚀深度的一致性。此外，外延层的厚度一致性可以相对容易地控制，结果，可以改善最终形成的鳍的厚度的一致性。
根本公开的优选实施例，所述至少一个半导体层包括两个或更多的半导体层。在这些半导体层中，相邻的半导体层可以相对于彼此具有刻蚀选择性，从而可以选择性刻蚀每一半导体层。在形成鳍之后，可以选择性刻蚀其中的某一层(或多层)，使其横向变窄(凹入)。特别是，例如可以通过各向异性刻蚀，来形成∑型横向凹入。这种∑型横向凹入有助于减小由于刻蚀凹入而导致的工艺不一致性。
另外，如此形成隔离层，使得隔离层可以填充所述横向凹入，并且隔离层使得变窄(凹入)的所述一层(或多层)的一部分(相对于该隔离层顶面)突出。从而，变窄(凹入)的所述一层(或多层)位于最终形成鳍的底部(初始形成鳍位于所述一层或多层之下的部分由于被隔离层包围，从而不再充当用来形成沟道的真正鳍)。
这样，在最终形成鳍的底部，由于所述横向凹入，随后形成的栅与鳍之间的隔离层较厚，从而形成的寄生电容相对较小。
根据本公开的实施例，隔离层可以通过在衬底上淀积电介质层然后回蚀来形成。电介质层可以基本上覆盖所形成的初始鳍，且位于初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度，例如初始鳍顶部的电介质层厚度可以小于位于衬底上的电介质层厚度的三分之一，优选为四分之一。例如，这可以通过高密度等离子体(HDP)淀积来实现。另外，在形成多个初始鳍的情况下，位于每一初始鳍的顶面之上的电介质层的厚度可以小于与其相邻的鳍之间间距的二分之一。这样，在随后的回蚀中，可以减少刻蚀深度，从而能够增加刻蚀控制精度。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1所示，提供衬底1000。该衬底1000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在本发明的一个实施例中，衬底1000的表面晶向例如取为[100]。
在衬底1000中，可以形成n型阱1000-1和p型阱1000-2，以供随后在其中分别形成p型器件和n型器件。例如，n型阱1000-1可以通过在衬底1000中注入n型杂质如P或As来形成，p型阱1000-2可以通过在衬底1000中注入p型杂质如B来形成。如果需要，在注入之后还可以进行退火。本领域技术人员能够想到多种方式来形成n型阱、p型阱，在此不再赘述。
这里需要指出的是，尽管在以下描述中说明了分别在n型阱和p型阱中形成互补器件的工艺，但是本公开不限于此。例如，本公开同样适用于非互补工艺。而且，以下涉及互补器件的一些处理，在某些实现方式中并非是必须的。
在衬底1000上，例如通过外延生长，形成第一半导体层1002。例如，第一半导体层1002可以包括SiGe(Ge原子百分比例如为约5-20％)，厚度为约10-50nm。在本发明的一个实施例中，第一半导体层1002的表面晶向例如取为[100]。在外延生长第一半导体层的过程中，可以对其进行原位掺杂，例如通过B而掺杂为p型。第一半导体层的掺杂浓度可以高于之下的p型阱的掺杂浓度，例如可为1E18-2E19cm-3。根据一示例，为降低B扩散，可以在p型第一半导体层1002中注入C。
然后，可以通过光刻胶(未示出)遮挡p型阱区上的第一半导体层，并向n型阱区上的第一半导体层注入n型杂质如As或P，以将该部分第一半导体层转换为n型，且其掺杂浓度可以高于之下的n型阱的掺杂浓度。注入浓度例如可以是2E18-4E19cm-3。之后可以去除光刻胶。于是，形成了n型第一半导体层1002-1和p型第一半导体层1002-2。
接下来，在第一半导体层1002(包括1002-1和1002-2)上，例如通过外延生长，形成第二半导体层1004。例如，第二半导体层1004可以包括Si，厚度为约20-100nm。
根据本公开的另一实施例，第一半导体层也可以包括Si，并且也可以同样地如上所述进行掺杂。尽管第一半导体层与之下的衬底和之上的第二半导体层同样包括Si材料，但是由于掺杂浓度的不同，它们之间也可以实现一定的刻蚀选择性。
在第二半导体层1004上，可以形成保护层1006。保护层1006例如可以包括氧化物(例如，氧化硅)，厚度为约10-50nm。这种保护层1006可以在随后的处理中保护鳍的端部。
随后，可以对如此形成的第二半导体层1004进行构图，以形成初始鳍。例如，这可以如下进行。具体地，在保护层1006上按设计形成构图的光刻胶1008。通常，光刻胶1008被构图为一系列平行的等间距线条。然后，如图2所示，以构图的光刻胶1008为掩模，依次选择性刻蚀例如反应离子刻蚀(RIE)保护层1006、第二半导体层1004，从而形成初始鳍。之后，可以去除光刻胶1008。
这里需要指出的是，尽管在图2的示例中，将通过刻蚀所形成的(初始鳍之间的)沟槽的形状示出为规则矩形形状，但本公开不限于此。例如，沟槽可以是从上到下逐渐变小的锥台形。另外，所形成的初始鳍的位置和数目不限于图2所示的示例。
为了减小最终形成鳍底部的寄生电容，可以对第一半导体层1002进行选择性刻蚀，以使其相对于第二半导体层1004横向凹入。为了确保在对第一半导体层1002进行刻蚀过程中不损坏初始鳍，可以在初始鳍的侧面上形成保护层。具体地，如图3所示，例如可以按侧墙的形式，在初始鳍的侧壁上形成保护层1012。例如，保护层1012可以包括氮化物(例如，氮化硅)，厚度为约5-10nm。在图3所示的示例中，由于初始鳍的顶部已经存在保护层1006，因此保护层1012可以侧墙形式形成，而没有形成在初始鳍的顶部。但是，本公开不限于此，可以各种形式形成适当的保护层1012。
当然，如果对第一半导体层的刻蚀剂相对于第二半导体层、衬底具有足够的刻蚀选择性，可以省略这种保护层。
为了降低工艺变化，优选地在第二半导体层中形成∑型横向凹入。本领域中存在多种方式来形成∑型横向凹入，以下仅描述一种示例。具体地，如图4所示，可以通过离子注入(图4中箭头所示)，来在第一半导体层中形成非晶化区域1030。由于初始鳍的存在，这种非晶化区域1030基本上位于相邻的初始鳍之间；且由于扩散，而略微延伸到鳍之下，端面基本上呈C型。例如，这种离子注入可以通过注入Ge来完成，注入深度为约5-10nm，注入剂量大于约3E14cm-2。然后，如图5所示，可以相对于第一半导体层1002中的晶体部分，来选择性刻蚀非晶化区域1030，从而在第一半导体层1002中形成C型横向凹入。之后，如图6所示，可以通过这种C型横向凹入，进一步对第一半导体层1002进行各向异性刻蚀，并因此形成∑型横向凹入。这种各向异性刻蚀例如可以通过TMAH溶液来进行。在这种情况下，衬底1000也经受了一定程度的刻蚀。在本发明的一个实施例中，∑型横向凹入的侧壁例如沿着{111}晶面。
这里需要指出的是，形成C型横向凹入的方式不限于上述示例。例如，可以采用各向同性的刻蚀(例如，氧化剂加HF基酸性溶液的湿法刻蚀，或者各向同性干法刻蚀)，或者先采用RIE等各向异性的干法刻蚀然后采用各向同性干法刻蚀，等等。
另外，在互补工艺的情况下，还可以如图7所示，来在n型区域和p型区域之间形成隔离。具体地，可以在衬底上形成光刻胶1010，并对光刻胶1010进行构图，以露出n型区域和p型区域之间界面周围的一定区域。然后，通过选择性刻蚀例如RIE，去除该区域存在的保护层、第二半导体层、第一半导体层。也可以进一步选择性刻蚀如RIE衬底。从而在n型区域和p型区域之间形成隔离地带，该隔离地带随后可以被电介质所填充。然后，可以去除光刻胶1010。
在图2所示的示例中，在n型阱1000-1和p型阱1000-2之间的界面处，也形成了初始鳍。由于图7所示的隔离形成工艺，该初始鳍也被去除。于是，得到了图8所示的结构。
在通过上述处理形成具有横向凹入的鳍之后，可以形成横跨鳍的栅堆叠，并形成最终的半导体器件。
为了隔离栅堆叠和衬底，在衬底上首先形成隔离层。这种隔离层例如可以通过在衬底上淀积电介质材料，且然后进行回蚀来形成。这样，隔离层会填充横向凹入。另外，在回蚀过程中，控制回蚀深度，使得回蚀后的电介质材料能够使第一半导体层的一部分(相对于电介质层的顶面)突出。也即，(除了填充横向凹入的部分之外)隔离层的顶面位于第一半导体层的顶面之下，且位于第一半导体层的底面之上。例如，隔离层可以包括高密度等离子体(HDP)氧化物(例如，氧化硅)。
在此，为了改善回蚀之后电介质层(顶面的)高度的一致性，并因此改善最终形成的鳍的高度的一致性，如图9所示，在淀积电介质材料1014的过程中，使得电介质材料1014基本上覆盖初始鳍(在多个初始鳍的情况下，基本上填充初始鳍之间的间隙)。根据本公开的实施例，可以如此淀积，使得初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度，并且一般来说初始鳍顶部的电介质层厚度都小于位于衬底上的电介质层厚度的三分之一，优选为四分之一。例如，每一初始鳍顶部的电介质层厚度一般不大于20nm，而位于衬底上的电介质层厚度可达100nm左右。
根据本公开的一示例，电介质材料1014可以包括通过高密度等离子体(HDP)淀积形成的氧化物(例如，氧化硅)。由于HDP的特性，在淀积过程中可以使得初始鳍顶部的电介质层(沿垂直于衬底方向的)厚度和初始鳍侧面的电介质层(沿平行于衬底的方向，即横向的)厚度要小于初始鳍之间衬底上的电介质层(沿垂直于衬底方向的)厚度。因为HDP的这种特性，在常规技术中通常并不采用HDP淀积来制作氧化隔离。
在此，例如可以通过控制淀积条件，使得电介质层1014在基本上覆盖初始鳍时(或者，基本上填充初始鳍之间的空隙时)，位于每一初始鳍顶部上的厚度可以小于与其相邻的初始鳍之间间距的二分之一。如果初始鳍之间的间距并不相同，则可以使电介质层1014位于每一初始鳍顶部的厚度小于与其相邻的初始鳍之间间距中较小间距的二分之一。
随后，如图10所示，对电介质材料1014进行回蚀。由于电介质材料1014的回蚀深度相对较小，从而对该刻蚀的控制相对容易，并因此可以更加精确地控制从鳍的顶面(在该示例中，第二半导体层1004的顶面)到隔离层1014的顶面的距离(至少部分地决定最终器件的鳍高度并因此决定最终器件的沟道宽度)，使得该距离在衬底上基本保持一致。这样，隔离层就限定了位于其上方的鳍。在第一半导体层1002-1和1002-2是如上所述进行掺杂的示例中，其对应的阈值电压要高于第二半导体层1004对应的阈值电压。因此，通过控制栅极控制电压，可以使得第二半导体层导通而第一半导体层并不能导通。这样，最终用作器件的鳍可以仅包括第二半导体层1004，且第一半导体层可以充当穿通阻挡层，防止源漏之间的穿通。
在一个示例中，保护层1006和电介质材料1014包括相同的材料，如氧化物。因此，在对电介质材料1014回蚀的过程中，可能同时去除了保护层1006，如图10所示。之后，可以去除保护层1012。
随后，可以在隔离层1014上形成横跨鳍的栅堆叠。例如，这可以如下进行。具体地，如图11所示(图11(b)示出了沿图11(a)中BB′线的截面图)，例如通过淀积，形成栅介质层1016。例如，栅介质层1016可以包括氧化物，厚度为约0.8-1.5nm。在图11所示的示例中，仅示出了“∏”形的栅介质层1016。但是，栅介质层1016也可以包括在隔离层1014的表面上延伸的部分。然后，例如通过淀积，形成栅导体层1018。例如，栅导体层1018可以包括多晶硅。栅导体层1018可以填充鳍之间的间隙，并可以进行平坦化处理例如化学机械抛光(CMP)。之后，对栅导体层1018进行构图，以形成栅堆叠。在图8的示例中，栅导体层1018被构图为与鳍相交的条形。根据另一实施例，还可以构图后的栅导体层1018为掩模，进一步对栅介质层1016进行构图。
如图11(b)中的椭圆虚线圈所示，在鳍的底部与栅导体1018之间存在相对较厚的隔离层1014，从而产生的寄生电容相对较小。
在形成构图的栅导体之后，例如可以栅导体为掩模，进行晕圈(halo)注入和延伸区(extension)注入。
接下来，如图12(图12(b)示出了沿图12(a)中BB′线的截面图)所示，可以在栅导体层1018的侧壁上形成侧墙1020。例如，可以通过淀积形成厚度约为5-30nm的氮化物，然后对氮化物进行RIE，来形成侧墙1020。本领域技术人员知道多种方式来形成这种侧墙，在此不再赘述。
在鳍之间的沟槽为从上到下逐渐变小的锥台形时(由于刻蚀的特性，通常为这样的情况)，侧墙1020基本上不会形成于鳍的侧壁上。
在形成侧墙之后，可以栅导体及侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以形成源/漏区。这样，就得到了根据该实施例的半导体器件。如图12所示，该半导体器件可以包括：衬底；在衬底上依次形成的构图的第一半导体层和第二半导体层，其中第一半导体层包括相对于第二半导体层的∑型横向凹入；在衬底上形成的隔离层，该隔离填充所述横向凹入，隔离层除填充横向凹入之外的部分的顶面低于第一半导体层的顶面、高于第一半导体层的底面，从而限定出位于隔离层上方的鳍；以及在隔离层上形成的横跨鳍的栅堆叠。对于p型器件，第一半导体层中可以掺杂n型杂质；对于n型器件，第一半导体层中可以掺杂p型杂质。这种掺杂的第一半导体层可以充当穿通阻挡层。
在上述实施例中，在形成鳍之后，直接形成了栅堆叠。本公开不限于此。例如，替代栅工艺同样适用于本公开。
根据本公开的另一实施例，在图11中形成的栅介质层1016和栅导体层1018为牺牲栅介质层和牺牲栅导体层。接下来，可以同样按以上结合图11、12描述的方法来进行处理。
接下来，如图13(图13(b)示出了沿图13(a)中BB′线的截面图)所示，例如通过淀积，形成电介质层1022。该电介质层1022例如可以包括氧化物。随后，对该电介质层1022进行平坦化处理例如CMP。该CMP可以停止于侧墙1020，从而露出牺牲栅导体1018。
随后，如图14(图14(b)示出了沿图14(a)中BB′线的截面图，图14(c)示出了沿图14(a)中CC′线的截面图)所示，例如通过TMAH溶液，选择性去除牺牲栅导体1018，从而在侧墙1020内侧形成了空隙1024。根据另一示例，还可以进一步去除牺牲栅介质层1016。
然后，如图15(图15(b)示出了沿图15(a)中BB′线的截面图，图15(c)示出了沿图15(a)中CC′线的截面图)所示，通过在空隙1024中形成栅介质层1026和栅导体层1028，形成最终的栅堆叠。栅介质层1026可以包括高K栅介质例如HfO2，厚度为约1-5nm。栅导体层1028可以包括金属栅导体。优选地，在栅介质层1022和栅导体层1024之间还可以形成功函数调节层(未示出)。
这里需要指出的是，在图15中，将栅介质层1026示出为空隙1024底部的一薄层。但是，栅介质层1026还可以形成在空隙1024的侧壁上，从而包围栅导体层1028。
这样，就得到了根据该实施例的半导体器件。该半导体器件与图11所示的半导体器件在结构上基本相同，除了栅堆叠按不同方式形成之外。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (14)

1.一种制造半导体器件的方法，包括：
在衬底上依次形成第一半导体层和第二半导体层；
对第二半导体层进行构图，以形成初始鳍；
对第一半导体层进行各向异性刻蚀，以在其中形成∑型横向凹入；
在衬底上形成隔离层，所述隔离层填充所述横向凹入，且除了填充所述横向凹入的部分之外，所述隔离层的顶面位于第一半导体层的顶面和底面之间，从而限定出位于隔离层上方的鳍；
在隔离层上形成横跨鳍的栅堆叠。
2.根据权利要求1所述的方法，其中，对第一半导体层进行各向异性刻蚀包括：
对第一半导体层进行刻蚀，以在其中形成C型横向凹入；以及
通过所述C型横向凹入，对第一半导体层进行各向异性刻蚀，以形成∑型横向凹入。
3.根据权利要求2所述的方法，其中，形成C型横向凹入包括：
通过离子注入，在第一半导体层中形成非晶化区域；以及
去除所述非晶化区域，以形成C型横向凹入。
4.根据权利要求1所述的方法，其中，在形成初始鳍之后，在对第一半导体层进行各向异性刻蚀之前，该方法还包括：
在鳍的侧面上形成保护层。
5.根据权利要求1所述的方法，其中，在构图初始鳍之前，该方法还包括：
在第二半导体层上形成保护层。
6.根据权利要求1所述的方法，其中，形成隔离层包括：
在衬底上淀积电介质层，使得电介质层实质上覆盖初始鳍，其中位于初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度；以及
对电介质层进行回蚀。
7.根据权利要求6所述的方法，其中，位于初始鳍顶部的电介质层厚度小于位于衬底上的电介质层厚度的三分之一。
8.根据权利要求6所述的方法，其中，通过高密度等离子体(HDP)淀积形成电介质层。
9.根据权利要求6所述的方法，其中，在衬底上形成多个初始鳍，且位于每一初始鳍顶部的电介质层厚度小于与其相邻的初始鳍之间间距的二分之一。
10.根据权利要求1所述的方法，其中，对于p型器件，第一半导体层中掺杂n型杂质；对于n型器件，第一半导体层中掺杂p型杂质。
11.一种半导体器件，包括：
衬底；
在衬底上依次形成的构图的第一半导体层和第二半导体层，其中第一半导体层包括相对于第二半导体层的∑型横向凹入；
在衬底上形成的隔离层，该隔离填充所述横向凹入，隔离层除填充横向凹入之外的部分的顶面低于第一半导体层的顶面、高于第一半导体层的底面，从而限定出位于隔离层上方的鳍；以及
在隔离层上形成的横跨鳍的栅堆叠。
12.根据权利要求11所述的半导体器件，其中，
衬底包括体Si；
第一半导体层包括Si或SiGe，且被掺杂形成穿通阻挡部；
第二半导体层包括Si。
13.根据权利要求12所述的半导体器件，其中，对于p型器件，第一半导体层中掺杂n型杂质；对于n型器件，第一半导体层中掺杂p型杂质。
14.根据权利要求11所述的半导体器件，其中该半导体器件包括多个鳍，其中每一鳍的顶面大致持平，隔离层的顶面大致持平。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097935A (zh) * 2014-05-23 2015-11-25 美国博通公司 具有无掺杂本体块的鳍式场效应晶体管
CN105428238A (zh) * 2014-09-17 2016-03-23 中芯国际集成电路制造(上海)有限公司 一种FinFET器件及其制作方法和电子装置
CN106816379A (zh) * 2015-11-27 2017-06-09 联华电子股份有限公司 具有外延结构的半导体元件及其制作方法
CN108231896A (zh) * 2016-12-15 2018-06-29 台湾积体电路制造股份有限公司 半导体装置
CN112786452A (zh) * 2019-11-08 2021-05-11 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150017774A1 (en) * 2013-07-10 2015-01-15 Globalfoundries Inc. Method of forming fins with recess shapes
US10290636B2 (en) * 2014-08-18 2019-05-14 Stmicroelectronics, Inc. Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods
US9954107B2 (en) * 2015-05-05 2018-04-24 International Business Machines Corporation Strained FinFET source drain isolation
US10903210B2 (en) * 2015-05-05 2021-01-26 International Business Machines Corporation Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture
US9853101B2 (en) 2015-10-07 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Strained nanowire CMOS device and method of forming
US9812394B2 (en) * 2015-10-12 2017-11-07 International Business Machines Corporation Faceted structure formed by self-limiting etch
US9608069B1 (en) 2016-04-13 2017-03-28 Intenational Business Machines Corporation Self aligned epitaxial based punch through control
US9647123B1 (en) * 2016-10-14 2017-05-09 International Business Machines Corporation Self-aligned sigma extension regions for vertical transistors
DE102017127354A1 (de) * 2016-12-15 2018-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-bauelement und herstellungsverfahren dafür
US11908863B2 (en) * 2018-12-31 2024-02-20 Unist(Ulsan National Institute Of Science And Technology) Transistor element, ternary inverter apparatus comprising same, and method for producing same
WO2021137433A1 (ko) * 2019-12-30 2021-07-08 울산과학기술원 터널 전계효과트랜지스터 및 이를 포함하는 삼진 인버터

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6787854B1 (en) * 2003-03-12 2004-09-07 Advanced Micro Devices, Inc. Method for forming a fin in a finFET device
US20100109120A1 (en) * 2006-06-02 2010-05-06 Micron Technology, Inc. Single crystal silicon structures
CN102005477A (zh) * 2009-09-01 2011-04-06 台湾积体电路制造股份有限公司 集成电路、鳍式场效应晶体管及其制造方法
CN102244098A (zh) * 2010-05-14 2011-11-16 台湾积体电路制造股份有限公司 半导体装置及其制造方法
US20120199888A1 (en) * 2011-02-09 2012-08-09 United Microelectronics Corporation Fin field-effect transistor structure

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885055B2 (en) * 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8283653B2 (en) 2009-12-23 2012-10-09 Intel Corporation Non-planar germanium quantum well devices
DE102010064283B4 (de) * 2010-12-28 2012-12-27 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zur Herstellung eines selbstjustierten Steg-Transistors auf einem Vollsubstrat durch eine späte Stegätzung
US8916909B2 (en) * 2012-03-06 2014-12-23 Infineon Technologies Austria Ag Semiconductor device and method for fabricating a semiconductor device
CN103545212B (zh) * 2012-07-16 2016-09-21 中国科学院微电子研究所 半导体器件制造方法
US9299837B2 (en) * 2013-05-22 2016-03-29 Globalfoundries Inc. Integrated circuit having MOSFET with embedded stressor and method to fabricate same
CN103346086B (zh) * 2013-05-31 2016-08-10 上海华力微电子有限公司 嵌入式锗硅结构的制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6787854B1 (en) * 2003-03-12 2004-09-07 Advanced Micro Devices, Inc. Method for forming a fin in a finFET device
US20100109120A1 (en) * 2006-06-02 2010-05-06 Micron Technology, Inc. Single crystal silicon structures
CN102005477A (zh) * 2009-09-01 2011-04-06 台湾积体电路制造股份有限公司 集成电路、鳍式场效应晶体管及其制造方法
CN102244098A (zh) * 2010-05-14 2011-11-16 台湾积体电路制造股份有限公司 半导体装置及其制造方法
US20120199888A1 (en) * 2011-02-09 2012-08-09 United Microelectronics Corporation Fin field-effect transistor structure

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097935A (zh) * 2014-05-23 2015-11-25 美国博通公司 具有无掺杂本体块的鳍式场效应晶体管
CN105097935B (zh) * 2014-05-23 2018-05-29 安华高科技通用Ip(新加坡)公司 具有无掺杂本体块的鳍式场效应晶体管
CN105428238A (zh) * 2014-09-17 2016-03-23 中芯国际集成电路制造(上海)有限公司 一种FinFET器件及其制作方法和电子装置
CN105428238B (zh) * 2014-09-17 2019-01-22 中芯国际集成电路制造(上海)有限公司 一种FinFET器件及其制作方法和电子装置
CN106816379A (zh) * 2015-11-27 2017-06-09 联华电子股份有限公司 具有外延结构的半导体元件及其制作方法
CN106816379B (zh) * 2015-11-27 2021-09-07 联华电子股份有限公司 具有外延结构的半导体元件及其制作方法
CN108231896A (zh) * 2016-12-15 2018-06-29 台湾积体电路制造股份有限公司 半导体装置
CN108231896B (zh) * 2016-12-15 2022-11-18 台湾积体电路制造股份有限公司 半导体装置
CN112786452A (zh) * 2019-11-08 2021-05-11 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112786452B (zh) * 2019-11-08 2023-12-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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