CN102005477A - 集成电路、鳍式场效应晶体管及其制造方法 - Google Patents

集成电路、鳍式场效应晶体管及其制造方法 Download PDF

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CN102005477A
CN102005477A CN2010102638023A CN201010263802A CN102005477A CN 102005477 A CN102005477 A CN 102005477A CN 2010102638023 A CN2010102638023 A CN 2010102638023A CN 201010263802 A CN201010263802 A CN 201010263802A CN 102005477 A CN102005477 A CN 102005477A
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fin formula
raceway groove
effect transistor
field effect
formula field
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CN102005477B (zh
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叶致锴
张智胜
万幸仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种集成电路、鳍式场效应晶体管及其制造方法，该鳍式场效应晶体管包括一基材及一鳍式结构于此基材上。此鳍式结构包含一沟道，位于一源极及一漏极之间，其中此源极、此漏极及此沟道具有一第一型掺杂。此沟道包含锗、锗化硅或III-V族半导体。一栅极介电层涂布于此沟道上，且一栅极位于此栅极介电层上。本发明可抑制界面缺陷的影响，还可掺入锗化硅应力源至锗的鳍式场效应晶体管NMOS中，以增进效能。

Description

集成电路、鳍式场效应晶体管及其制造方法
技术领域
本发明涉及一种半导体装置，尤其涉及一种累积型(accumulation type)鳍式场效应晶体管。
背景技术
随着集成电路尺寸微缩，需克服因尺寸微缩所面临的问题。例如，金属氧化物半导体场效应晶体管(MOSFET)因沟道长度缩减而造成效能降低，包括漏电流增加。因此，业界需要新颖的方法及结构来改善金属氧化物半导体场效应晶体管的效能。
发明内容
为了解决现有技术的问题，本发明提供一种鳍式场效应晶体管，包括：一基材；一鳍式结构，位于此基材上，此鳍式结构包含一沟道，位于一源极及一漏极之间，其中此源极、此漏极及此沟道具有一第一型掺杂，且此沟道包含锗、锗化硅或III-V族半导体至少其一；一栅极介电层，位于此沟道上；以及一栅极，位于此栅极介电层上。
本发明也提供一种鳍式场效应晶体管的制造方法，包括：形成一鳍式结构于一基材上，此鳍式结构包含一沟道，位于一源极及一漏极之间，其中此源极、此漏极及此沟道具有一第一型掺杂，且此源极、此漏极及此沟道包含锗、锗化硅或III-V族半导体；形成一栅极介电层于此沟道上；以及形成一栅极于此栅极介电层上。
本发明还提供一种集成电路，包括：一基材；一虚置图案，包含至少一第一鳍式结构于此基材上，此第一鳍式结构包含一第一沟道，位于一第一源极及一第一漏极之间，其中此第一源极、此第一漏极及此第一沟道具有一第一型掺杂；以及一鳍式场效应晶体管，位于此基材上，此鳍式场效应晶体管包含：一第二鳍式结构，位于此基材上，此第二鳍式结构包含一第二沟道，位于一第二源极及一第二漏极之间，其中此第二源极、此第二漏极及此第二沟道具有一第二型掺杂，且此第二沟道包含锗、锗化硅或III-V族半导体至少其一；一栅极介电层，位于此第二沟道上；及一栅极，位于此栅极介电层上。
本发明可抑制界面缺陷的影响，还可掺入锗化硅应力源至锗的鳍式场效应晶体管NMOS中，以增进效能。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1A显示为鳍式场效应晶体管，并显示用于图1B及图1C的不同的剖面方向；
图1B～图1C显示为依照本发明一实施例的累积型鳍式场效应晶体管的剖面图；
图2显示为依照本发明一实施例的累积型鳍式场效应晶体管与传统装置的开电流Ion的比较；
图3显示为本发明一实施例的累积型鳍式场效应晶体管与传统装置的内部电子密度的比较；
图4显示为依照本发明另一实施例的形成累积型鳍式场效应晶体管的工艺；及
图5显示为依照本发明又一实施例的具有虚置图案及含多个累积型鳍式场效应晶体管结构的鳍式场效应晶体管装置的集成电路的剖面图。
其中，附图标记说明如下：
106～源极108～沟道
107～硅化物110～漏极
111～硅化物112～阱区
114～栅极介电层115～氧化层
116～栅极117～氮化间隔层
118～浅沟槽隔离120～基材
502～虚置图案
504～鳍式场效应晶体管装置
506～鳍式场效应晶体管装置
508～沟道
具体实施方式
以下将详细讨论本发明各种实施例的制造及使用方法。然而值得注意的是，本发明所提供的许多可行的发明概念可实施在各种特定范围中。这些特定实施例仅用于举例说明本发明的制造及使用方法，但非用于限定本发明的范围。
某些使用材料不同于硅的平面金属氧化物半导体场效应晶体管相较于传统的硅平面金属氧化物半导体装置(Si planar MOS device)具有优势，例如锗平面金属氧化物半导体装置(Ge planar MOS device)，其载流子(电子/空穴)迁移率较硅高约2.64倍。经发现，锗平面MOS装置面临下列问题：(1)较低的能隙间距Eg及高次临界漏电流Isub(subthreshold leakage current)、(2)高介电常数ε及短沟道效应(short channel effect，SCE)、(3)高界面缺陷(Nit)导致锗的NMOS中的载流子迁移率μ不佳。
当沟道长度缩短时，平面金属氧化物半导体场效应晶体管可具有的沟道长度与源极及漏极所接合的耗尽层的宽度具有相同的数量级。相较于其他金属氧化物半导体场效应晶体管，短沟道效应使平面金属氧化物半导体场效应晶体管的效能更加衰退。当缩短沟道长度以同时增加操作速度及芯片积集度时，短沟道效应也会增加。短沟道效应可归因于两种物理现象：(1)沟道中的电子漂移有其限制，及(2)由于沟道缩短而修改了临界电压。短沟道效应包含：(1)漏极引致势垒下降(drain-induced barrier lowering，DIBL)、(2)表面散射、(3)速度饱和、(4)撞击游离及(5)热电子。特别的是，由于锗平面型MOS具有较高的介电常数ε，显示出更糟的漏极引致势垒下降(DIBL)。
在锗的NMOS中，发现到在介电层及靠近锗的导带(Ec)之间的界面有高密度的界面缺陷(Nit)，而大幅降低电子迁移率。相较于二氧化硅与硅的系统，氧化锗(或其他介电层)及锗不具有理想的界面，二氧化硅/硅具有良好的界面而提供硅的MOS所需的界面品质及低界面缺陷。
如上所述，业界所需的是金属氧化物半导体场效应晶体管结构及其制造方法。在本发明实施例中，提供一种累积型鳍式场效应晶体管(accumulation-type FinFET)装置100，以增进金属氧化物半导体场效应晶体管的效能。图1A显示为一实施例的鳍式场效应晶体管。在图1A中，鳍式场效应晶体管100可包含鳍式结构102。图1B及图1C各自显示图1A所示的鳍式场效应晶体管100沿着线段1B及1C的剖面图。在图1A-图1B中，显示累积型鳍式场效应晶体管100具有基材120及鳍式结构102于基材120上。鳍式结构102包含位于源极106及漏极110之间的沟道108。源极106、漏极110及沟道108具有第一型掺杂。位于源极106、漏极110及沟道108之下的阱区112具有第二型掺杂。沟道108包含锗、锗化硅或III-V族半导体。栅极介电层114位于沟道108上。栅极116位于栅极介电层114上。
在一形成锗的N型累积型鳍式场效应晶体管(N-type accumulation GeFinFET)的实施例中，源极106(例如n+源极区)可通过硅化物107连接至源极电压VS。沟道108(例如n-沟道区)可例如包含锗鳍式区(Ge fin region)。漏极110(例如n+漏极区)可通过硅化物111连接至漏极电压VD。阱区112(例如p型阱区)可提供与其他装置电性隔离。栅极介电层114可包含氧化物、氮化物、氮氧化物、高介电常数介电质或前述的任意组合。栅极116(例如金属栅极)可连接至栅极电压VG。氧化层115及氮化间隔物117显示位于栅极116后方。基材120可包含硅、锗、锗化硅、III-V族半导体及/或前述的组合。高介电常数材料可例如包含硅酸铪(HfSiO)、硅酸锆(ZrSiO4)、二氧化锆、其他高介电常数介电材料或前述的任意组合。在其他实施例中，沟道108可包含锗化硅或III-V族半导体，例如AlGaAs、InGaAs等。
图1C显示为累积型鳍式场效应晶体管100的剖面图，其具有沟道108、栅极介电层114及栅极116。位于鳍底下的阱区112提供电性隔离。在一实施例中，沟道108(例如n-沟道)包含锗鳍式区。阱区112(例如p型阱区)提供电性隔离。栅极116可设置于栅极介电层114上。浅沟槽隔离118可形成邻近于阱区112。在其他实施例中，沟道108可包含锗化硅或III-V族半导体，例如AlGaAs、InGaAs等。
在N型累积型鳍式场效应晶体管102中，沟道108、源极106及漏极110可具有n型掺杂。在另一实施例中，P型累积型PMOS装置的沟道108、源极106及漏极110可具有p型掺杂。累积型鳍式场效应晶体管可改变电子/空穴轮廓(electron/hole profile)及费米能阶(EF)位置，其可抑制界面缺陷(Nit)的影响。此外，可掺入锗化硅应力源至锗的鳍式场效应晶体管NMOS中，以增进效能。
于传统反转型(inversion type)NMOS(具有p-沟道)中，电子堆积在界面层，且装置可能会因界面缺陷而降低迁移率。然而，累积型NMOS与传统反转型NMOS相反，块材反转(bulk inversion)减少了可造成降低次临界电流摆幅及电子迁移率的界面缺陷。块材反转(bulk inversion)意指大多数的反转电荷位于图1C所示的鳍中的块材鳍状区(bulk Fin region)作为内部电子(bulk electrons)。然而，在传统的表面反转型装置中，大多数电子堆积于栅极介电质/鳍的表面作为表面电子。使用等同于电源供应电压的栅极电压(VG＝VDD)，累积的费米能阶较靠近能隙(Eg)中间值(mid-bandgap)，且可实质上减少界面缺陷(Nit)的影响。
经发现，沟道掺杂浓度及/或施予漏极110的电源供应电压VDD可影响累积型鳍式场效应晶体管100的电性效能。例如，在NMOS/PMOS的一实施例中，沟道中的反掺杂密度(counter doping density)为n型/p型1e18cm-3～3e18cm-3，电源供应电压VDD为0.5V。在NMOS累积型装置中，n型沟道可减少费米能阶(EF)，增加内部电子密度(bulk electron density)，因此减少表面界面缺陷(Nit)的影响。例如，在一累积型NMOS的实施例中，电子密度为7.1e12cm-2，相比较的反转型NMOS的电子密度为6.7e12cm-2。此外，低的电源供应电压VDD使费米能阶EF移向能隙中间值，增加内部电子/空穴百分比，及减少在NMOS/PMOS中的表面界面缺陷(Nit)的影响。
锗及III-V族半导体沟道材料，例如AlGaAs、InGaAs等，可提供较硅高的载流子迁移率。鳍式场效应晶体管结构提供较佳的栅极控制、较低的漏电流及较佳的尺寸可调性(scalability)。基材120可为硅或锗基材晶片。在一实施例中，可在基材120上进行锗的外延，以形成用于沟道108的锗鳍(Ge-fin)。在NMOS的实施例中，由于锗化硅或硅的源极/漏极可在沟道108中(例如锗沟道)具有拉伸应力以提高电子迁移率，较佳可选择锗化硅或硅的源极/漏极。在P型金属氧化物半导体导体的实施例中，也可使用锗的源极/漏极区，但较佳为GeSn、SiGeSn或III-V族半导体，由于GeSn、SiGeSn或III-V族半导体源极/漏极可在沟道108(例如锗沟道)中具有压缩应力以提高空穴迁移率。
具有锗鳍式沟道区108的鳍式场效应晶体管结构可帮助降低由高介电常数ε所导致的短沟道效应(SCE)。在累积型装置中，鳍式场效应晶体管结构可显著抑制漏电流。相较于平面装置，鳍式场效应晶体管结构可借由较低的沟道掺杂(例如1e17cm-3)及降低的电源供应电压VDD来显著减少能带穿遂(Band to band tunneling，BTBT)漏电流。
图2显示本发明一实施例的锗的累积型鳍式场效应晶体管与传统装置的开电流Ion(turn-on current)的比较。结果呈现在NMOS中，鳍的表面区域的电子迁移率降低了80％，这是由于在锗装置中的界面缺陷Nit(陷阱)的影响。
在图2中，显示传统无界面缺陷(Nit)的硅反转型鳍式场效应晶体管NMOS的开电流Ion。将锗的鳍式场效应晶体管的开电流Ion正规化并与硅的反转型鳍式场效应晶体管相比，具有界面缺陷的锗的反转型鳍式场效应晶体管NMOS装置仅有74％的开电流Ion，这是由于电子迁移率在鳍表面上因锗的界面缺陷而降低。换言之，由TACD模拟可显示出，相较于硅的场效应晶体管(反转模式)，界面缺陷造成了开电流Ion降低26％。上述的锗的反转型鳍式场效应晶体管NMOS，非为累积型态且不具有应力源。然而，具有累积型态的锗的反转型鳍式场效应晶体管NMOS装置，虽然同样具有锗的界面缺陷，但开电流Ion增加至108％。因此，使用累积型沟道可实现34％增益的开电流Ion，也表示锗的累积型沟道的开电流Ion较硅的鳍式场效应晶体管高8％。另外，当加入锗化硅(SiGe)应力源，开电流Ion更增进至132％。在一些实施例中，还可使用表面钝化技术以进一步降低锗累积型鳍式场效应晶体管的界面缺陷。
在累积型装置中，鳍区(Wfin)的宽度较窄，可抑制闭路漏电流Ioff及改善装置效能因短沟道效应(SCE)/漏极引致势垒下降(DIBL)的影响。在一实施例中，鳍宽度小于30nm而具有较佳的效能。在鳍区(Wfin)较宽的平面结构中，需高浓度袋状掺杂(pocket doping)且实际上较难制造累积型沟道。
此外，累积型装置显示在块材区域具有较高的电子密度，特别是在低的电源供应电压VDD及栅极电压VG(例如0.5V)。图3显示本发明一实施例的块材内部电子密度与传统装置的比较。如图3所示，在一实施例中，在栅极电压为0.5V的条件下，锗的累积型鳍式场效应晶体管约有70％的内部电子密度，相较之下，反转型装置则具有约40％的内部电子体积密度。锗的累积型鳍式场效应晶体管NMOS装置具有约1e18cm-3(N型)的沟道掺杂密度，及漏极引致势垒下降(DIBL)为105mV/V，然而，反转型态装置的沟道掺杂浓度为5e18cm-3(p型)。
图4显示依照本发明另一实施例制造鳍式场效应晶体管的工艺流程图。于步骤402，形成鳍式结构于基材120上，其中鳍式结构包含位于源极106及漏极110之间的沟道108(源极106、漏极110及沟道108皆具有相同型态的半导体，且沟道108包含锗、锗化硅或III-V族半导体)。于步骤404，形成栅极介电层104(例如氧化物及/或高介电常数介电质)于沟道108上。于步骤406，形成栅极116于栅极介电层114上。此工艺可还包含沉积及蚀刻浅沟槽隔离(shallow trench isolation，STI)118层，其可提供与邻近装置的隔离。
此工艺可还包含在源极106、漏极110及沟道108下方形成阱区112，其中阱区112具有第二型掺杂。沟道108可具有约1e18cm-3至3e18cm-3的掺杂浓度。栅极116能接收电压，且此电压能使沟道的费米能阶移向沟道的能隙中间值。形成鳍式结构可包含定义沟道108的宽度。在一实施例中，沟道108的宽度可为约30nm或更小。源极106或漏极110至少其一包含用于NMOS装置的锗、锗化硅或硅。源极106或漏极110至少其一包含用于NMOS装置的锗、锗化硅、硅或III-V族半导体。
图5显示为依照本发明又一实施例的包含虚置图案及含多个累积型鳍式场效应晶体管结构的鳍式场效应晶体管装置的集成电路。集成电路包含基材120、虚置图案502及鳍式场效应晶体管装置504、506。虚置图案502包含至少一鳍式结构于基材上。鳍式结构包含位于第一源极及第一漏极之间的沟道508。此源极、漏极及沟道508具有第一型掺杂。阱区112具有第二型掺杂，并提供与其他邻近装置的电性隔离。
位于基材120上的鳍式场效应晶体管装置504、506也包含位于基材120上的鳍式结构。鳍式结构包含位于源极及漏极之间的沟道。此源极、漏极及第二沟道108具有第一型掺杂。沟道108包含锗、锗化硅或III-V族半导体。栅极介电层114位于沟道108上。栅极116位于栅极介电层114上。在此实施例中，在同一装置中使用多个沟道108。
此装置具有累积型沟道，因而鳍式场效应晶体管装置504、506具有相同型态的半导体的沟道108、源极、漏极，例如各自用于NMOS/PMOS的n型/p型半导体。用于NMOS的阱区112为p型，而用于PMOS的阱区112为n型，此阱区112与浅沟槽隔离(STI)各自用作装置间的电性隔离及物理隔离。也可设置无栅极116的虚置图案502，以利于化学机械研磨(CMP)、蚀刻或鳍式轮廓的一致性。此装置可形成于硅或锗基材120上。
如前述，累积型鳍式场效应晶体管可提供所需电子或空穴迁移率，而可增进装置效能。借由使用累积型鳍式场效应晶体管结构，漏电流、界面缺陷(陷阱)及短沟道效应等先前传统锗平面装置所具有的缺点，已不复存于本发明实施例中。在本实施中，不仅可应用于锗沟道、也可应用于锗化硅或其他III-V族沟道材料。
另外，在同一装置中可使用多个鳍式结构，而可提供每单位面积有较高的电流。例如，既然锗及硅之间有晶格失配(lattice mismatch)，较窄的鳍相较于较宽的鳍易于成长良好品质的锗外延层。晶格失配导致的应力可由宽度较窄的鳍及缺陷及错位较少的锗外延层获得抒解。例如，当用于传统锗装置的鳍宽度为50nm时，其可被分隔成两个25nm的鳍。本领域普通技术人员可知本发明还具有许多其他变化实施例。
虽然本发明已以数个优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰。此外，本发明的范围不限定于现有或未来所发展的特定程序、机器、制造、物质的组合、功能、方法或步骤，其实质上进行与依照本发明所述的实施例相同的功能或达成相同的结果。因此，本发明的保护范围当视所附的权利要求所界定的范围为准。此外，每个权利要求建构成一独立的实施例，且各种权利要求及实施例的组合均介于本发明的范围内。

Claims (10)

1.一种鳍式场效应晶体管，包括：
一基材；
一鳍式结构，位于该基材上，该鳍式结构包含一沟道，位于一源极及一漏极之间，其中该源极、该漏极及该沟道具有一第一型掺杂，且该沟道包含锗、锗化硅或III-V族半导体至少其一；以及
一栅极介电层，位于该沟道上；以及
一栅极，位于该栅极介电层上。
2.如权利要求1所述的鳍式场效应晶体管，其中该沟道的掺杂浓度介于约1e18cm-3至3e18cm-3之间。
3.如权利要求1所述的鳍式场效应晶体管，其中该栅极能接受一电压，且该电压能使该沟道的费米能阶移向该沟道的能隙中间值。
4.如权利要求1所述的鳍式场效应晶体管，其中该鳍式场效应晶体管为一N型鳍式场效应晶体管，且该源极及该漏极至少其一包含锗、锗化硅或硅至少其一。
5.如权利要求1所述的鳍式场效应晶体管，其中该鳍式场效应晶体管为一P型鳍式场效应晶体管，且该源极及该漏极至少其一包含Ge、GeSn、SiGeSn或III-V族半导体至少其一。
6.一种鳍式场效应晶体管的制造方法，包括：
形成一鳍式结构于一基材上，该鳍式结构包含一沟道，位于一源极及一漏极之间，其中该源极、该漏极及该沟道具有一第一型掺杂，且该源极、该漏极及该沟道包含锗、锗化硅或III-V族半导体；
形成一栅极介电层于该沟道上；以及
形成一栅极于该栅极介电层上。
7.如权利要求6所述的鳍式场效应晶体管的制造方法，其中该沟道的掺杂浓度介于约1e18cm-3至3e18cm-3之间。
8.一种集成电路，包括：
一基材；
一虚置图案，包含至少一第一鳍式结构于该基材上，该第一鳍式结构包含一第一沟道，位于一第一源极及一第一漏极之间，其中该第一源极、该第一漏极及该第一沟道具有一第一型掺杂；以及
一鳍式场效应晶体管，位于该基材上，该鳍式场效应晶体管包含：
一第二鳍式结构，位于该基材上，该第二鳍式结构包含一第二沟道，位于一第二源极及一第二漏极之间，其中该第二源极、该第二漏极及该第二沟道具有一第二型掺杂，且该第二沟道包含锗、锗化硅或III-V族半导体至少其一；
一栅极介电层，位于该第二沟道上；及
一栅极，位于该栅极介电层上。
9.如权利要求8所述的集成电路，其中该第二沟道的掺杂浓度介于约1e18cm-3至3e18cm-3之间。
10.如权利要求8所述的集成电路，其中该第二源极及该第二漏极至少其一包含锗、锗化硅、硅、GeSn、SiGeSn或III-V族半导体至少其一。
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