CN102832135A - 锗、三五族半导体材料衬底上制备FinFET的方法 - Google Patents

锗、三五族半导体材料衬底上制备FinFET的方法 Download PDF

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CN102832135A
CN102832135A CN2012103264676A CN201210326467A CN102832135A CN 102832135 A CN102832135 A CN 102832135A CN 2012103264676 A CN2012103264676 A CN 2012103264676A CN 201210326467 A CN201210326467 A CN 201210326467A CN 102832135 A CN102832135 A CN 102832135A
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germanium
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finfet
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silicon nitride
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黄如
樊捷闻
许晓燕
李佳
王润声
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Peking University
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Priority to PCT/CN2013/079018 priority patent/WO2014036855A1/zh
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Abstract

本发明公开了一种锗、三五族半导体材料衬底上制备FinFET的方法，主要的工艺流程包括：形成源漏和连接源漏的细条状的图形结构；形成氧化隔离层；形成栅结构和源漏结构；形成金属接触和金属互联。采用此方法可以在锗、三五族半导体材料衬底上很容易的形成FinFET，而且整个工艺流程虽然在锗、三五族半导体材料上完成，但是完全与常规硅基超大规模集成电路制造技术类似，制备工艺具有简单、方便、周期短的特点。此外，采用此工艺制备出的FinFET最小宽度可以控制在二十纳米左右，多栅结构可以提供很好的栅控制能力，非常适合于制备超短沟器件，进一步缩小器件尺寸。且采用本发明制备形成的FinFET，具有较低的功耗。

Description

锗、三五族半导体材料衬底上制备FinFET的方法
技术领域
本发明提出了锗、三五族半导体材料衬底上制备FinFET的方法，属于超大规模集成电路制造技术领域。
背景技术
当今半导体制造业在摩尔定律的指导下迅速发展，不断地提高集成电路的性能和集成密度，同时尽可能的减小集成电路的功耗。因此，制备高性能，低功耗的超短沟器件将成为未来半导体制造业的焦点。当进入到22纳米技术节点以后，传统平面场效应晶体管的泄漏电流不断增加，以及日益严重的短沟道效应，漏致势垒降低（DIBL）效应，不能很好的适应半导体制造的发展。为了克服上述一系列问题，一大批新结构半导体器件开始崭露头角，如DoubleGate FET，FinFET，Tri-Gate FET，Gate-all-around(GAA)Nanowire(NW)FET等，逐渐引起广泛的关注。通过多栅结构，能够很好的加强栅对于沟道的控制能力，使得电场线难以从漏端直接穿过沟道到达源端，这样就能大幅度的改善漏致势垒降低效应，减小泄漏电流，并且很好的抑制短沟道效应。正是由于栅结构导致良好的栅控能力，沟道区域不需要像传统平面场效应晶体管一样进行重掺杂来抑制短沟道效应，轻掺杂沟道区域的优势在于减小了散射带来的迁移率的下降，从而使多栅结构器件的迁移率得到大幅度改善。因此，FinFET作为一种新结构器件，将是一个很有潜力的能够替代传统平面场效应晶体管的选择。
Hasimoto等人在1998年的IEDM会议上提出了“folded-channel MOSFETs”的概念。1999年，Heang等人在IEDM会议上公布50nm以下沟道长度的FinFET。这是FinFET第一次采用传统硅工艺，被成功的集成在衬底上。
Hu等人的U.S.Pat.No.6413802中揭开了FinFET的结构，以及制备FinFET的工艺。在SOI衬底上最容易形成FinFET，工艺相对简单，只需要在SOI衬底的顶硅层上光刻刻蚀出Fin条形状，然后再经过一系列栅工艺，源漏工艺以及后端的介质层和金属互联就可以形成FinFET。但是它的缺点是：（1）工艺成本太高，SOI衬底相当昂贵；（2）需要进行源漏抬升技术，否则源漏的扩展电阻过大导致开态电流过小，器件性能较差；（3）没有体引出，这样就无法通过衬底偏置效应调节阈值电压。在锗，三五族体衬底上形成FinFET，具有如下优点：（1）工艺成本相对较小，因为均在体衬底上完成，相比SOI片廉价很多；（2）由于采用锗、三五族衬底，所以器件的迁移率比较高，因此可以获得较大的开态电流；（3）在体衬底上制备FinFET，可以获得体引出，从而可以通过衬底偏置效应调节器件的阈值电压。
发明内容
本发明的目的在于提出了与常规硅基超大规模集成电路制造技术兼容的锗、三五族半导体材料衬底上制备FinFET的方法，
本发明通过如下技术方案予以实现：一种锗、三五族半导体材料衬底上制备FinFET的方法，包括如下步骤：
a)形成源漏和连接源漏的细条状（Fin条）的图形结构
该步骤主要目的是利用电子束光刻在硬掩膜上形成源漏和连接源漏的细条状图形结构，利用电子束光刻可以使形成的细条状结构宽度20-40纳米左右。
i.在硅衬底上采用离子增强化学气相淀积氧化硅、氮化硅作为硬掩膜；
ii通过一次电子束光刻，刻蚀氮化硅、氧化硅工艺，在硬掩膜上形成源漏和连接源漏的Fin条的图形结构；
iii.去掉电子束光刻胶；
iv.各向异性干法刻蚀锗、三五族衬底，将硬掩膜上的图形结构转移到衬底材料上；
b)形成氧化隔离层
该步骤主要目的是在Fin条下面和Fin条两侧衬底表面形成氧化层，使得这层氧化隔离层能够起到抑制了衬底平面晶体管的开启，防止电流从源端通过衬底到达漏端的作用。从而降低泄露电流，降低器件的功耗。
方案一：
i.采用离子增强化学气相淀积一层新的氧化硅，作为氧化隔离层；
ii CMP化学机械抛光，使氧化硅平坦化，并且停止在Fin条顶部氮化硅硬掩膜表面；
iii.利用湿法腐蚀回刻新淀积的氧化硅直Fin条露出设计的高度作为沟道区域；
方案二：
i.淀积一层新的氮化硅；
ii利用各项异性干法刻蚀刻蚀新的氮化硅，在Fin条两侧形成氮化硅侧墙；
iii.利用各项异性干法刻蚀刻蚀Fin条两侧裸露出来的锗、三五族衬底；
iv.利用各项同性干法刻蚀刻蚀Fin条两侧裸露凹陷下去的锗、三五族衬底和Fin条底部的锗、三五族半导体材料衬底；
如果完全刻蚀掉Fin条底部的锗、三五族半导体材料，使得Fin条不再与衬底相连，那么可以更好的抑制短沟道效应；如果部分刻蚀掉Fin条底部的锗、三五族半导体材料，使得Fin条仍然与衬底相连，那么可以使器件具有衬底偏置效应，更容易设计阈值电压。
v.采用离子增强化学气相淀积一层新的氧化硅，作为氧化隔离层；
vi.CMP化学机械抛光，使氧化硅平坦化，并且停止在Fin条顶部氮化硅硬掩膜表面；
vii利用湿法腐蚀回刻新淀积的氧化硅直Fin条露出设计的高度作为沟道区域；
c)制备栅结构和源漏结构
该步骤主要目的是形成栅结构，其中栅结构需要用电子束光刻来定义，这主要是因为电子束光刻能容易的将栅线条宽度控制在22纳米左右，这是我们需要的沟道长度。另外，如果增加CMP化学机械抛光使得Fin条两侧的栅结果分离，相互独立，从而得到独立双栅结构的FinFET。
i.ALD淀积一层栅介质层；
ii PVD淀积一层栅材料；
iii.通过电子束光刻，刻蚀栅材料，形成栅线条；
iv.通过离子增强化学汽相淀积以及回刻，形成氧化硅的侧墙；
v.进行离子注入和退火，形成源漏结构；
该步骤中，如果在光刻栅材料之前先进行一次CMP使得栅材料平坦化，并且平面表面为Fin条顶部氧化硅硬掩膜表面，然后再通过光刻刻蚀技术，在Fin条两侧形成两个相互不连接，独立的栅线条，从而成为多阈值电压器件。
d)形成金属接触和金属互联
该步骤主要目的是引出源漏端和栅端，方便测试和形成大规模电路结构。本发明具有如下技术效果：
该工艺流程完全与常规硅基超大规模集成电路制造技术兼容，制备过程具有简单、方便、周期短的特点。此外，采用此工艺制备出的FinFET最小宽度可以控制在二十纳米左右，多栅结构可以提供很好的栅控制能力，非常适合于制备超短沟器件，进一步缩小器件尺寸。最后，此方法制备形成的FinFET，具有较低的功耗，这主要由两个原因：一是因为Fin条下面和Fin条两侧衬底表面形成氧化层起到隔离作用，抑制了衬底平面晶体管的开启，防止电流从源端通过衬底到达漏端；二是因为独立双栅结构可以用于制备动态阈值电压场效应晶体管，在保持高性能的同时进一步降低功耗。
附图说明
图1-11是本发明提出的锗、三五族半导体材料衬底上制备FinFET的工艺流程示意图。工艺流程的简要说明如下：图1为淀积氧化硅氮化硅薄膜作为硬掩膜以后的结构示意图；图2为进行电子束光刻图形，并通过各项异性干法刻蚀将图形转移到锗、三五族半导体材料衬底上之后的结构示意图；图3为方案一中淀积氧化硅并进行CMP之后的结构示意图；图4为方案一中中各向同性湿法腐蚀氧化硅至露出一定高度的Fin条之后的结构示意图；图5为方案二中淀积氮化硅并各向异性干法刻蚀氮化硅，形成氮化硅侧墙之后的结构示意图；图6为方案二中各项异性干法刻蚀锗、三五族半导体材料衬底之后的结构示意图；图7为方案二中各项同性干法刻蚀锗、三五族半导体材料衬底，使Fin条悬空之后的结构示意图；图8为方案二中去掉氮化硅层之后的结构示意图；图9为方案二中淀积氧化硅、进行CMP、然后各向同性湿法腐蚀氧化硅至露出一定高度的Fin条之后的结构示意图；图10为进过栅介质层淀积，栅材料淀积以及后续的CMP工艺之后，对栅线条进行电子束光刻和各项异性干法刻蚀之后的结构示意图；图11为进行侧墙工艺以及源漏注入、退火工艺之后的最终器件结构示意图。
图中：1—锗、三五族半导体材料衬底；2—氧化硅：3—氮化硅；4—氮化钛。
具体实施方式
下面结合附图和具体实施例对本发明进行详细说明，具体给出一实现本发明提出的锗、三五族半导体材料衬底上制备FinFET的工艺方案，但不以任何方式限制本发明的范围。
根据下列步骤制备Fin条厚度约为20纳米，沟道长度约为32纳米的n型锗、三五族FinFET的方案一：
1.在硅衬底上离子增强化学气相沉积氧化硅300
Figure GDA00002100567200041
2.在氧化硅上离子增强化学气相沉积氮化硅1000
Figure GDA00002100567200042
如图1所示；
3.电子束光刻定义源漏和连接源漏的细条状图形结构，其中细条状图形结构的宽度为20纳米；
4.各向异性干法刻蚀1000
Figure GDA00002100567200043
氮化硅；
5.各向异性干法刻蚀300
Figure GDA00002100567200044
氧化硅；
6.去掉光刻胶；
7.各项异性干法刻蚀1000
Figure GDA00002100567200045
锗、三五族衬底，将图形转移到硅衬底上，如图2所示；
8.在硅衬底上离子增强化学气相沉积氧化硅5000
Figure GDA00002100567200046
9.CMP化学机械抛光，使氧化硅平坦化，并且停止在Fin条顶部氮化硅硬掩膜表面，如图3所示；
10.各向同性湿法腐蚀氧化硅，直至裸露出500高度的Fin条，如图4所示；
11.用HF溶液对Fin条进行表面清洗；
12.ALD淀积High-k材料，如HfO2，厚度为5nm；
13.溅射1000
Figure GDA00002100567200051
氮化钛，作为栅材料；
14.电子束光刻定义栅细线条，栅条的宽度为32纳米；
15.各项异性干法刻蚀1000
Figure GDA00002100567200052
氮化钛，形成栅细线条，如图10所示；
16.离子增强化学汽相沉积氧化硅200作为侧墙材料；
17.各向异性干法刻蚀200
Figure GDA00002100567200054
氧化层，形成侧墙；
18.源漏离子注入，注As，注入能量为50keV，注入剂量为4e15cm-2；
19.RTP退火，1050度，5秒，在氮气氛围下，如图11所示；
根据下列步骤制备Fin条厚度约为30纳米，沟道长度约为32纳米的n型锗、三五族FinFET的方案二：
1.在硅衬底上离子增强化学气相沉积氧化硅300
Figure GDA00002100567200055
2.在氧化硅上离子增强化学气相沉积氮化硅1000
Figure GDA00002100567200056
如图1所示；
3.电子束光刻定义源漏和连接源漏的细条状图形结构，其中细条状图形结构的宽度为20纳米；
4.各向异性干法刻蚀1000
Figure GDA00002100567200057
氮化硅；
5.各向异性干法刻蚀300
Figure GDA00002100567200058
氧化硅；
6.去掉光刻胶；
7.各项异性干法刻蚀1000
Figure GDA00002100567200059
锗、三五族衬底，将图形转移到硅衬底上，如图2所示；
8.在硅衬底上离子增强化学气相沉积氮化硅500
9.各向异性干法刻蚀氮化硅500
Figure GDA000021005672000511
如图5所示，在Fin条两侧形成氮化硅侧墙；
10.各向异性干法刻蚀1000锗、三五族衬底，如图6所示，刻蚀Fin条两侧裸露出来的锗、三五族衬底；
11.各向同性干法刻蚀1000
Figure GDA000021005672000513
锗、三五族衬底，如图7所示，刻蚀Fin条两侧裸露凹陷下去的锗、三五族衬底和Fin条底部的锗、三五族半导体材料衬底。如果完全刻蚀掉Fin条底部的锗、三五族半导体材料，使得Fin条不再与衬底相连，那么可以更好的抑制短沟道效应；如果部分刻蚀掉Fin条底部的锗、三五族半导体材料，使得Fin条仍然与衬底相连，那么可以使器件具有衬底偏置效应，更容易设计阈值电压。
12.各向同性湿法腐蚀去掉1000
Figure GDA000021005672000514
氮化硅，如图8所示；
13.在硅衬底上离子增强化学气相沉积氧化硅5000
14.CMP化学机械抛光，使氧化硅平坦化，并且停止在Fin条顶部氮化硅硬掩膜表面；
15.各向同性湿法腐蚀氧化硅，直至裸露出500高度的Fin条，如图9所示；
16.用HF溶液对Fin条进行表面清洗；
17.ALD淀积High-k材料，如HfO2，厚度为5nm；
18.溅射1000
Figure GDA00002100567200063
氮化钛，作为栅材料；
19.电子束光刻定义栅细线条，栅条的宽度为32纳米；
20.各项异性干法刻蚀1000
Figure GDA00002100567200064
氮化钛，形成栅细线条，如图10所示；
21.离子增强化学汽相沉积氧化硅200
Figure GDA00002100567200065
作为侧墙材料；
22.各向异性干法刻蚀200
Figure GDA00002100567200066
氧化层，形成侧墙；
23.源漏离子注入，注As，注入能量为50keV，注入剂量为4e15cm-2；
24.RTP退火，1050度，5秒，在氮气氛围下，如图11所示。
最后需要注意的是，公布实施方式的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附的权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。

Claims (7)

1.一种锗、三五族半导体材料衬底上制备FinFET的方法，包括如下步骤：
a)形成源漏和连接源漏的细条状的图形结构
i.在锗、三五族衬底上采用离子增强化学气相淀积氧化硅、氮化硅作为硬掩膜；
ii.通过一次电子束光刻，刻蚀氮化硅、氧化硅工艺，在硬掩膜上形成源漏和连接源漏的Fin条的图形结构；
iii.去掉电子束光刻胶；
iv.各向异性干法刻蚀锗、三五族衬底，将硬掩膜上的图形结构转移到衬底材料上；
b)形成氧化隔离层的方案
i.采用离子增强化学气相淀积一层新的氧化硅，作为氧化隔离层；
ii.CMP化学机械抛光，使氧化硅平坦化，并且停止在Fin条顶部氮化硅硬掩膜表面；
iii.利用湿法腐蚀回刻新淀积的氧化硅直Fin条露出设计的高度作为沟道区域；
c)形成栅结构和源漏结构
i.ALD淀积一层栅介质层；
ii.PVD淀积一层栅材料；
iii.通过电子束光刻，刻蚀栅材料，形成栅线条；
iv.通过离子增强化学汽相淀积以及回刻；
v.进行离子注入和退火，形成源漏结构。
2.一种锗、三五族半导体材料衬底上制备FinFET的方法，包括如下步骤：
a)形成源漏和连接源漏的细条状的图形结构
i.在硅衬底上采用离子增强化学气相淀积氧化硅、氮化硅作为硬掩膜；
ii.通过一次电子束光刻，刻蚀氮化硅、氧化硅工艺，在硬掩膜上形成源漏和连接源漏的Fin条的图形结构；
iii.去掉电子束光刻胶；
iv.各向异性干法刻蚀锗、三五族衬底，将硬掩膜上的图形结构转移到衬底材料上；
b)形成氧化隔离层的方案
i.淀积一层新的氮化硅；
ii.利用各项异性干法刻蚀刻蚀新的氮化硅，在Fin条两侧形成氮化硅侧墙；
iii.利用各项异性干法刻蚀刻蚀Fin条两侧裸露出来的锗、三五族半导体材料衬底；
iv.利用各项同性干法刻蚀刻蚀Fin条两侧裸露凹陷下去的锗、三五族半导体材料衬底，以及完全刻蚀掉或部分刻蚀掉Fin条底部的锗、三五族半导体材料衬底；
v.采用离子增强化学气相淀积一层新的氧化硅，作为氧化隔离层；
vi.CMP化学机械抛光，使氧化硅平坦化，并且停止在Fin条顶部氮化硅硬掩膜表面；
vii.利用湿法腐蚀回刻新淀积的氧化硅直Fin条露出设计的高度作为沟道区域；
c)形成栅结构和源漏结构
i.ALD淀积一层栅介质层；
ii.PVD淀积一层栅材料；
iii.通过电子束光刻，刻蚀栅材料，形成栅线条；
iv.通过离子增强化学汽相淀积以及回刻；
v.进行离子注入和退火，形成源漏结构。
3.如权利要求1或2所述的锗、三五族半导体材料衬底上制备FinFET的方法，其特征在于：所属步骤c)中，High-k栅介质和金属栅材料分别由ALD和PVD完成。
4.如权利要求1或2所述的锗、三五族半导体材料衬底上制备FinFET的方法，其特征在于：所属步骤c)中，在光刻栅材料之前先进行一次CMP使得栅材料平坦化，并且平面表面为Fin条顶部氧化硅硬掩膜表面，然后再通过光刻刻蚀技术，在Fin条两侧形成两个相互不连接，独立的栅线条。
5.如权利要求1或2所述的锗、三五族半导体材料衬底上制备FinFET的方法，其特征在于：所述步骤a)、c)中，光刻形成源漏和连接源漏的细条状图形结构，采用电子束光刻技术形成细栅图形结构。
6.如权利要求1或2所述的锗、三五族半导体材料衬底上制备FinFET的方法，其特征在于：所述步骤a)、b)中，淀积工艺采用PECVD技术。
7.如权利要求1或2所述的锗、三五族半导体材料衬底上制备FinFET的方法，其特征在于：所述步骤c)中，涉及的退火工艺为低温退火，退火温度范围为300℃-500℃。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9196711B2 (en) 2014-03-07 2015-11-24 International Business Machines Corporation Fin field effect transistor including self-aligned raised active regions
US9859430B2 (en) * 2015-06-30 2018-01-02 International Business Machines Corporation Local germanium condensation for suspended nanowire and finFET devices
EP3244447A1 (en) 2016-05-11 2017-11-15 IMEC vzw Method for forming a gate structure and a semiconductor device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060038129A (ko) * 2004-10-29 2006-05-03 한국과학기술원 비대칭적인 일함수를 갖는 이중 게이트 구조를 이용한2비트 비휘발성 메모리 소자 제조 방법 및 그 구조
CN101060136A (zh) * 2007-06-05 2007-10-24 北京大学 一种双鳍型沟道围栅场效应晶体管及其制备方法
US20080308850A1 (en) * 2007-06-18 2008-12-18 Jorg Berthold Transistor with reduced charge carrier mobility and associated methods
US20100197099A1 (en) * 2005-11-14 2010-08-05 Samsung Electronics Co., Ltd. SCHOTTKY BARRIER FiNFET DEVICE AND FABRICATION METHOD THEREOF
CN102005477A (zh) * 2009-09-01 2011-04-06 台湾积体电路制造股份有限公司 集成电路、鳍式场效应晶体管及其制造方法
CN102136428A (zh) * 2011-01-25 2011-07-27 北京大学 一种锗基肖特基n型场效应晶体管的制备方法
CN102646599A (zh) * 2012-04-09 2012-08-22 北京大学 一种大规模集成电路中FinFET的制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
US7060539B2 (en) * 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
US7173312B2 (en) * 2004-12-15 2007-02-06 International Business Machines Corporation Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification
US7485520B2 (en) * 2007-07-05 2009-02-03 International Business Machines Corporation Method of manufacturing a body-contacted finfet
US8349732B2 (en) * 2008-07-18 2013-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Implanted metal silicide for semiconductor device
CN102832135A (zh) * 2012-09-05 2012-12-19 北京大学 锗、三五族半导体材料衬底上制备FinFET的方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060038129A (ko) * 2004-10-29 2006-05-03 한국과학기술원 비대칭적인 일함수를 갖는 이중 게이트 구조를 이용한2비트 비휘발성 메모리 소자 제조 방법 및 그 구조
US20100197099A1 (en) * 2005-11-14 2010-08-05 Samsung Electronics Co., Ltd. SCHOTTKY BARRIER FiNFET DEVICE AND FABRICATION METHOD THEREOF
CN101060136A (zh) * 2007-06-05 2007-10-24 北京大学 一种双鳍型沟道围栅场效应晶体管及其制备方法
US20080308850A1 (en) * 2007-06-18 2008-12-18 Jorg Berthold Transistor with reduced charge carrier mobility and associated methods
CN102005477A (zh) * 2009-09-01 2011-04-06 台湾积体电路制造股份有限公司 集成电路、鳍式场效应晶体管及其制造方法
CN102136428A (zh) * 2011-01-25 2011-07-27 北京大学 一种锗基肖特基n型场效应晶体管的制备方法
CN102646599A (zh) * 2012-04-09 2012-08-22 北京大学 一种大规模集成电路中FinFET的制备方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014036855A1 (zh) * 2012-09-05 2014-03-13 北京大学 锗、三五族半导体材料衬底上制备FinFET的方法
WO2014166146A1 (zh) * 2013-04-08 2014-10-16 中国科学院微电子研究所 FinFET及其制造方法
CN104103517B (zh) * 2013-04-08 2017-03-29 中国科学院微电子研究所 FinFET及其制造方法

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