WO2014036855A1 - 锗、三五族半导体材料衬底上制备FinFET的方法 - Google Patents

锗、三五族半导体材料衬底上制备FinFET的方法 Download PDF

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WO2014036855A1
WO2014036855A1 PCT/CN2013/079018 CN2013079018W WO2014036855A1 WO 2014036855 A1 WO2014036855 A1 WO 2014036855A1 CN 2013079018 W CN2013079018 W CN 2013079018W WO 2014036855 A1 WO2014036855 A1 WO 2014036855A1
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drain
source
etching
gate
germanium
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PCT/CN2013/079018
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French (fr)
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黄如
樊捷闻
许晓燕
李佳
王润声
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北京大学
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Priority to US14/400,511 priority Critical patent/US20150140758A1/en
Publication of WO2014036855A1 publication Critical patent/WO2014036855A1/zh

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Definitions

  • the invention provides a method for preparing a FinFET on a substrate of a bismuth and a tri-five semiconductor material, and belongs to the technical field of ultra-large scale integrated circuit fabrication. Background technique
  • Hasimoto et al. proposed the concept of "folded-channel MOSFETs" at the 1998 IEDM conference.
  • Heang et al. announced a FinFET with a channel length below 50 nm at the IEDM conference. This is the first time FinFET has been successfully integrated on a substrate using a conventional silicon process.
  • the structure of a FinFET and the process of fabricating a FinFET are disclosed in US Pat. No. 6413802 to Hu et al.
  • the FinFET is the easiest to form on an SOI substrate.
  • the process is relatively simple. It only needs to lithographically etch the Fin strip shape on the top silicon layer of the SOI substrate, and then pass through a series of gate processes, source and drain processes, and the dielectric layer at the back end.
  • a FinFET can be formed by interconnecting with a metal.
  • a FinFET is formed on a three-five-body substrate, which has the following advantages: (1) The process cost is relatively small, because it is completed on the bulk substrate, which is much cheaper than the SOI sheet; (2) due to the use of ⁇ , III The five-group substrate, so the mobility of the device is relatively high, so that a large on-state current can be obtained; (3) FinFET can be fabricated on the bulk substrate, and the body can be extracted, so that the device can be adjusted by the substrate bias effect. Threshold voltage.
  • a method for preparing a FinFET on a substrate of a germanium, a three-five-group semiconductor material comprising the following steps:
  • the main purpose of this step is to form a thin strip-like pattern of source and drain and connection source and drain on the hard mask by electron beam lithography.
  • the thin strip structure can be formed by electron beam lithography to a width of about 20 to 40 nanometers.
  • the main purpose of this step is to form an oxide layer under the Fin strip and on the surface of the substrate on both sides of the Fin strip, so that the oxide isolation layer can suppress the opening of the substrate planar transistor and prevent current from passing from the source end to the drain end through the substrate. effect. This reduces the leakage current and reduces the power consumption of the device.
  • the germanium and tri-five semiconductor materials at the bottom of the Fin strip are completely etched, so that the Fin strip is no longer connected to the substrate, the short channel effect can be better suppressed; if the bottom of the Fin strip is partially etched, the third and third The Group V semiconductor material, which allows the Fin strip to remain attached to the substrate, allows the device to have a substrate biasing effect, making it easier to design a threshold voltage.
  • the main purpose of this step is to form a gate structure in which the gate structure needs to be defined by electron beam lithography, mainly because electron beam lithography can easily control the gate line width to about 22 nm, which is the channel length we need. .
  • CMP chemical mechanical polishing is added, the gate results on both sides of the Fin strip are separated and independent of each other, resulting in a FinFET of independent double gate structure.
  • PVD deposits a layer of gate material
  • the planar surface is a surface of the Fin strip top silicon oxide hard mask, and then formed by lithography on both sides of the Fin strip. Two separate lines that are not connected to each other, thus becoming a multi-threshold voltage device.
  • the main purpose of this step is to lead the source and drain terminals and the gate terminal to facilitate testing and formation of large-scale circuit structures.
  • the present invention has the following technical effects:
  • the process is completely compatible with conventional silicon-based VLSI manufacturing technology, and the preparation process is simple. Single, convenient, and short cycle features.
  • the minimum width of the FinFET prepared by this process can be controlled to about 20 nanometers.
  • the multi-gate structure can provide good gate control capability, which is very suitable for preparing ultra-short trench devices and further reducing the device size.
  • the FinFET formed by this method has lower power consumption, which is mainly caused by two reasons: First, the formation of an oxide layer under the Fin strip and the surface of the substrate on both sides of the Fin strip serves as an isolation, suppressing the substrate plane. The transistor is turned on to prevent current from passing from the source to the drain through the substrate; the second is because the independent double-gate structure can be used to fabricate dynamic threshold voltage FETs, while maintaining high performance while further reducing power consumption.
  • FIGS. 1-11 are schematic diagrams showing a process flow for fabricating a FinFET on a substrate of a bismuth, a three-five-group semiconductor material proposed by the present invention.
  • FIG. 1 is a schematic view of the structure after depositing a silicon oxide silicon nitride film as a hard mask
  • Figure 2 is an electron beam lithography pattern, and transferring the pattern by anisotropic dry etching
  • FIG. 3 is a schematic view showing the structure after depositing silicon oxide and performing CMP in the first embodiment
  • FIG. 4 is an isotropic wet etching silicon oxide in the first embodiment.
  • FIG. 5 is a schematic structural view of the second embodiment after depositing silicon nitride and anisotropic dry etching of silicon nitride to form a silicon nitride sidewall
  • FIG. 8 is a schematic structural view of the second embodiment after removing the silicon nitride layer
  • FIG. 9 is a second embodiment of depositing silicon oxide, performing CMP, and then isotropic wet etching of silicon oxide to expose Schematic diagram of the structure after a certain height of the Fin strip
  • Figure 10 shows the electron beam lithography and the anisotropic dry etching of the gate lines after deposition of the gate dielectric layer, gate material deposition and subsequent CMP processes.
  • Schematic diagram of the structure Figure 11 is a schematic diagram of the final device structure after the sidewall process and source-drain implantation and annealing processes.
  • Electron beam lithography defines a thin strip-like pattern structure of source and drain and connection source and drain, wherein the strip-like pattern structure has a width of 20 nm;
  • ALD deposits a High-k material, such as Hf0 2 , with a thickness of 5 nm;
  • Electron beam lithography defines a fine line of gates with a width of 32 nm
  • Source and sink ion implantation Note As, the implantation energy is 50keV, and the implantation dose is 4el5cm- 2 ;
  • the second scheme of the n-type ⁇ and three-five FinFETs with a Fin strip thickness of about 30 nm and a channel length of about 32 nm is prepared:
  • Electron beam lithography defines a thin strip-like pattern structure of source and drain and connection source and drain, wherein the strip-like pattern structure has a width of 20 nm;
  • Isotropic wet etching removes 1000A silicon nitride, as shown in Figure 8;
  • ALD deposits a High-k material, such as Hf0 2 , having a thickness of 5 nm;
  • Electron beam lithography defines a fine line of gates with a width of 32 nm
  • Source and sink ion implantation Note As, the implantation energy is 50keV, and the implantation dose is 4el5cm- 2 ;

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  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种锗、三五族半导体材料衬底上制备FinFET的方法，主要的工艺流程包括：形成源漏和连接源漏的细条状的图形结构；形成氧化隔离层；形成栅结构和源漏结构；形成金属接触和金属互联。采用此方法可以在锗、三五族半导体材料衬底上很容易的形成FinFET，而且整个工艺流程虽然在锗、三五族半导体材料上完成，但是完全与常规硅基超大规模集成电路制造技术类似，制备工艺具有简单、方便、周期短的特点。此外，采用此工艺制备出的FinFET最小宽度可以控制在二十纳米左右，多栅结构可以提供很好的栅控制能力，非常适合于制备超短沟器件，进一步缩小器件尺寸。且采用本发明制备形成的FinFET，具有较低的功耗。

Description

锗、 三五族半导体材料衬底上制备 FinFET的方法 相关申请的交叉引用
本申请要求于 2012年 9月 5 日提交的中国专利申请 （201210326467.6) 的优先 权， 其全部内容通过引用合并于此。 技术领域
本发明提出了锗、 三五族半导体材料衬底上制备 FinFET的方法， 属于超大规模 集成电路制造技术领域。 背景技术
当今半导体制造业在摩尔定律的指导下迅速发展，不断地提高集成电路的性能和 集成密度， 同时尽可能的减小集成电路的功耗。 因此， 制备高性能， 低功耗的超短沟 器件将成为未来半导体制造业的焦点。 当进入到 22纳米技术节点以后， 传统平面场 效应晶体管的泄漏电流不断增加，以及日益严重的短沟道效应，漏致势垒降低（DIBL) 效应， 不能很好的适应半导体制造的发展。 为了克服上述一系列问题， 一大批新结构 半导体器件开始崭露头角，如 Double Gate FET, FinFET, Tri-Gate FET, Gate-all-around (GAA) Nanowire (NW) FET等， 逐渐引起广泛的关注。 通过多栅结构， 能够很好 的加强栅对于沟道的控制能力， 使得电场线难以从漏端直接穿过沟道到达源端，这样 就能大幅度的改善漏致势垒降低效应， 减小泄漏电流， 并且很好的抑制短沟道效应。 正是由于栅结构导致良好的栅控能力，沟道区域不需要像传统平面场效应晶体管一样 进行重掺杂来抑制短沟道效应，轻掺杂沟道区域的优势在于减小了散射带来的迁移率 的下降， 从而使多栅结构器件的迁移率得到大幅度改善。 因此， FinFET 作为一种新 结构器件， 将是一个很有潜力的能够替代传统平面场效应晶体管的选择。
Hasimoto等人在 1998年的 IEDM会议上提出了 "folded-channel MOSFETs"的概念。 1999年， Heang等人在 IEDM会议上公布 50nm以下沟道长度的 FinFET。这是 FinFET 第一次采用传统硅工艺， 被成功的集成在衬底上。
Hu等人的 U.S. Pat. No. 6413802中揭开了 FinFET的结构， 以及制备 FinFET的 工艺。 在 SOI衬底上最容易形成 FinFET, 工艺相对简单， 只需要在 SOI衬底的顶硅 层上光刻刻蚀出 Fin条形状， 然后再经过一系列栅工艺， 源漏工艺以及后端的介质层 和金属互联就可以形成 FinFET。 但是它的缺点是： （1 ) 工艺成本太高， SOI衬底相 当昂贵； （2) 需要进行源漏抬升技术， 否则源漏的扩展电阻过大导致开态电流过小， 器件性能较差； （3 )没有体引出，这样就无法通过衬底偏置效应调节阈值电压。在锗， 三五族体衬底上形成 FinFET, 具有如下优点： （1 ) 工艺成本相对较小， 因为均在体 衬底上完成， 相比 SOI片廉价很多； (2) 由于采用锗、 三五族衬底， 所以器件的迁移 率比较高， 因此可以获得较大的开态电流； （3 ) 在体衬底上制备 FinFET, 可以获得 体引出， 从而可以通过衬底偏置效应调节器件的阈值电压。 发明内容 本发明的目的在于提出了与常规硅基超大规模集成电路制造技术兼容的锗、三五 族半导体材料衬底上制备 FinFET的方法，
本发明通过如下技术方案予以实现： 一种锗、 三五族半导体材料衬底上制备 FinFET的方法， 包括如下步骤：
a) 形成源漏和连接源漏的细条状 （Fin条） 的图形结构
该步骤主要目的是利用电子束光刻在硬掩膜上形成源漏和连接源漏的细条状图 形结构， 利用电子束光刻可以使形成的细条状结构宽度 20~40纳米左右。
i. 在硅衬底上采用离子增强化学气相淀积氧化硅、 氮化硅作为硬掩膜； ii. 通过一次电子束光刻， 刻蚀氮化硅、氧化硅工艺， 在硬掩膜上形成源漏和连接 源漏的 Fin条的图形结构；
iii. 去掉电子束光刻胶；
iv. 各向异性干法刻蚀锗、 三五族衬底， 将硬掩膜上的图形结构转移到衬底材料 上；
b) 形成氧化隔离层
该步骤主要目的是在 Fin条下面和 Fin条两侧衬底表面形成氧化层， 使得这层氧 化隔离层能够起到抑制了衬底平面晶体管的开启，防止电流从源端通过衬底到达漏端 的作用。 从而降低泄露电流， 降低器件的功耗。
方案一：
i. 采用离子增强化学气相淀积一层新的氧化硅， 作为氧化隔离层；
ii. CMP化学机械抛光， 使氧化硅平坦化， 并且停止在 Fin条顶部氮化硅硬掩膜表 面；
iii. 利用湿法腐蚀回刻新淀积的氧化硅直 Fin条露出设计的高度作为沟道区域； 方案二：
i. 淀积一层新的氮化硅；
ii. 利用各项异性干法刻蚀刻蚀新的氮化硅， 在 Fin条两侧形成氮化硅侧墙； iii. 利用各项异性干法刻蚀刻蚀 Fin条两侧裸露出来的锗、 三五族衬底； iv. 利用各项同性干法刻蚀刻蚀 Fin条两侧裸露凹陷下去的锗、 三五族衬底和 Fin 条底部的锗、 三五族半导体材料衬底；
如果完全刻蚀掉 Fin条底部的锗、 三五族半导体材料， 使得 Fin条不再与衬底相 连， 那么可以更好的抑制短沟道效应； 如果部分刻蚀掉 Fin条底部的锗、三五族半导 体材料， 使得 Fin条仍然与衬底相连， 那么可以使器件具有衬底偏置效应， 更容易设 计阈值电压。
i. 采用离子增强化学气相淀积一层新的氧化硅， 作为氧化隔离层；
ii. CMP化学机械抛光， 使氧化硅平坦化， 并且停止在 Fin条顶部氮化硅硬掩膜表 面；
iii. 利用湿法腐蚀回刻新淀积的氧化硅直 Fin条露出设计的高度作为沟道区域； c) 制备栅结构和源漏结构
该步骤主要目的是形成栅结构，其中栅结构需要用电子束光刻来定义，这主要是 因为电子束光刻能容易的将栅线条宽度控制在 22纳米左右， 这是我们需要的沟道长 度。 另外， 如果增加 CMP化学机械抛光使得 Fin条两侧的栅结果分离， 相互独立， 从而得到独立双栅结构的 FinFET。
i. ALD淀积一层栅介质层；
ii. PVD淀积一层栅材料；
iii. 通过电子束光刻， 刻蚀栅材料， 形成栅线条；
iv. 通过离子增强化学汽相淀积以及回刻， 形成氧化硅的侧墙；
v. 进行离子注入和退火， 形成源漏结构；
该步骤中， 如果在光刻栅材料之前先进行一次 CMP使得栅材料平坦化， 并且平 面表面为 Fin条顶部氧化硅硬掩膜表面， 然后再通过光刻刻蚀技术， 在 Fin条两侧形 成两个相互不连接， 独立的栅线条， 从而成为多阈值电压器件。
d) 形成金属接触和金属互联
该步骤主要目的是引出源漏端和栅端， 方便测试和形成大规模电路结构。本发明 具有如下技术效果：
该工艺流程完全与常规硅基超大规模集成电路制造技术兼容， 制备过程具有简 单、 方便、 周期短的特点。 此外， 采用此工艺制备出的 FinFET最小宽度可以控制在 二十纳米左右， 多栅结构可以提供很好的栅控制能力， 非常适合于制备超短沟器件， 进一步缩小器件尺寸。 最后， 此方法制备形成的 FinFET, 具有较低的功耗， 这主要 由两个原因： 一是因为 Fin条下面和 Fin条两侧衬底表面形成氧化层起到隔离作用， 抑制了衬底平面晶体管的开启， 防止电流从源端通过衬底到达漏端； 二是因为独立双 栅结构可以用于制备动态阈值电压场效应晶体管，在保持高性能的同时进一步降低功 耗。 附图说明
图 1-11是本发明提出的锗、 三五族半导体材料衬底上制备 FinFET的工艺流程示 意图。
工艺流程的简要说明如下： 图 1为淀积氧化硅氮化硅薄膜作为硬掩膜以后的结构 示意图； 图 2为进行电子束光刻图形， 并通过各项异性干法刻蚀将图形转移到锗、三 五族半导体材料衬底上之后的结构示意图； 图 3为方案一中淀积氧化硅并进行 CMP 之后的结构示意图； 图 4为方案一中中各向同性湿法腐蚀氧化硅至露出一定高度的 Fin条之后的结构示意图； 图 5为方案二中淀积氮化硅并各向异性干法刻蚀氮化硅， 形成氮化硅侧墙之后的结构示意图； 图 6为方案二中各项异性干法刻蚀锗、三五族半 导体材料衬底之后的结构示意图； 图 7为方案二中各项同性干法刻蚀锗、三五族半导 体材料衬底， 使 Fin条悬空之后的结构示意图； 图 8为方案二中去掉氮化硅层之后的 结构示意图； 图 9为方案二中淀积氧化硅、 进行 CMP、 然后各向同性湿法腐蚀氧化 硅至露出一定高度的 Fin条之后的结构示意图； 图 10为进过栅介质层淀积， 栅材料 淀积以及后续的 CMP工艺之后， 对栅线条进行电子束光刻和各项异性干法刻蚀之后 的结构示意图； 图 11为进行侧墙工艺以及源漏注入、 退火工艺之后的最终器件结构 示意图。
图中： 1一锗、 三五族半导体材料衬底； 2—氧化硅： 3—氮化硅； 4一氮化钛。 具体实施方式 下面结合附图和具体实施例对本发明进行详细说明，具体给出一实现本发明提出 的锗、 三五族半导体材料衬底上制备 FinFET的工艺方案， 但不以任何方式限制本发 明的范围。
根据下列步骤制备 Fin条厚度约为 20纳米， 沟道长度约为 32纳米的 n型锗、三 五族 FinFET的方案一：
1. 在硅衬底上离子增强化学气相沉积氧化硅 300 A;
2. 在氧化硅上离子增强化学气相沉积氮化硅 1000 A， 如图 1所示；
3. 电子束光刻定义源漏和连接源漏的细条状图形结构，其中细条状图形结构的宽 度为 20纳米；
4. 各向异性干法刻蚀 1000A氮化硅；
5. 各向异性干法刻蚀 300A氧化硅；
6. 去掉光刻胶；
7. 各项异性干法刻蚀 1000A锗、 三五族衬底， 将图形转移到硅衬底上， 如图 2 所示；
8. 在硅衬底上离子增强化学气相沉积氧化硅 5000 A;
9. CMP化学机械抛光， 使氧化硅平坦化， 并且停止在 Fin条顶部氮化硅硬掩膜表 面， 如图 3所示；
10. 各向同性湿法腐蚀氧化硅， 直至裸露出 500A高度的 Fin条， 如图 4所示； 11. 用 HF溶液对 Fin条进行表面清洗；
12. ALD淀积 High-k材料， 如 Hf02， 厚度为 5nm;
13. 溅射 ΙΟΟΟΑ氮化钛， 作为栅材料；
14. 电子束光刻定义栅细线条， 栅条的宽度为 32纳米；
15. 各项异性干法刻蚀 1000A氮化钛， 形成栅细线条， 如图 10所示；
16. 离子增强化学汽相沉积氧化硅 200A， 作为侧墙材料；
17. 各向异性干法刻蚀 200A氧化层， 形成侧墙；
18. 源漏离子注入， 注 As， 注入能量为 50keV， 注入剂量为 4el5cm— 2；
19. RTP退火， 1050度， 5秒， 在氮气氛围下， 如图 11所示；
根据下列步骤制备 Fin条厚度约为 30纳米， 沟道长度约为 32纳米的 n型锗、三 五族 FinFET的方案二：
1. 在硅衬底上离子增强化学气相沉积氧化硅 300 A;
2. 在氧化硅上离子增强化学气相沉积氮化硅 1000 A， 如图 1所示；
3. 电子束光刻定义源漏和连接源漏的细条状图形结构，其中细条状图形结构的宽 度为 20纳米；
4. 各向异性干法刻蚀 1000A氮化硅；
5. 各向异性干法刻蚀 300A氧化硅； 6. 去掉光刻胶；
7. 各项异性干法刻蚀 1000A锗、 三五族衬底， 将图形转移到硅衬底上， 如图 2 所示；
8. 在硅衬底上离子增强化学气相沉积氮化硅 500 A;
9. 各向异性干法刻蚀氮化硅 500 A，如图 5所示，在 Fin条两侧形成氮化硅侧墙；
10. 各向异性干法刻蚀 1000A锗、 三五族衬底， 如图 6所示， 刻蚀 Fin条两侧裸 露出来的锗、 三五族衬底；
11. 各向同性干法刻蚀 1000A锗、 三五族衬底， 如图 7所示， 刻蚀 Fin条两侧裸 露凹陷下去的锗、 三五族衬底和 Fin条底部的锗、 三五族半导体材料衬底。 如果完全 刻蚀掉 Fin条底部的锗、 三五族半导体材料， 使得 Fin条不再与衬底相连， 那么可以 更好的抑制短沟道效应； 如果部分刻蚀掉 Fin条底部的锗、 三五族半导体材料， 使得 Fin条仍然与衬底相连， 那么可以使器件具有衬底偏置效应， 更容易设计阈值电压。
12. 各向同性湿法腐蚀去掉 1000A氮化硅， 如图 8所示；
13. 在硅衬底上离子增强化学气相沉积氧化硅 5000 A;
14. CMP化学机械抛光， 使氧化硅平坦化， 并且停止在 Fin条顶部氮化硅硬掩膜 表面；
15. 各向同性湿法腐蚀氧化硅， 直至裸露出 500A高度的 Fin条， 如图 9所示；
16. 用 HF溶液对 Fin条进行表面清洗；
17. ALD淀积 High-k材料， 如 Hf02， 厚度为 5nm;
18. 溅射 ιοοοΑ氮化钛， 作为栅材料；
19. 电子束光刻定义栅细线条， 栅条的宽度为 32纳米；
20. 各项异性干法刻蚀 1000A氮化钛， 形成栅细线条， 如图 10所示；
21. 离子增强化学汽相沉积氧化硅 200A， 作为侧墙材料；
22. 各向异性干法刻蚀 200A氧化层， 形成侧墙；
23. 源漏离子注入， 注 As， 注入能量为 50keV， 注入剂量为 4el5cm— 2；
24. RTP退火， 1050度， 5秒， 在氮气氛围下， 如图 11所示。
最后需要注意的是， 公布实施方式的目的在于帮助进一步理解本发明， 但是本领 域的技术人员可以理解： 在不脱离本发明及所附的权利要求的精神和范围内，各种替 换和修改都是可能的。 因此， 本发明不应局限于实施例所公开的内容， 本发明要求保 护的范围以权利要求书界定的范围为准。

Claims

权 利 要 求
1. 一种锗、 三五族半导体材料衬底上制备 FinFET的方法， 包括如下步骤： a) 形成源漏和连接源漏的细条状的图形结构
i. 在锗、三五族衬底上采用离子增强化学气相淀积氧化硅、氮化硅作为硬掩 膜；
ii. 通过一次电子束光刻， 刻蚀氮化硅、 氧化硅工艺， 在硬掩膜上形成源漏 和连接源漏的 Fin条的图形结构；
iii. 去掉电子束光刻胶；
iv. 各向异性干法刻蚀锗、 三五族衬底， 将硬掩膜上的图形结构转移到衬底 材料上；
b) 形成氧化隔离层的方案
1. 采用离子增强化学气相淀积一层新的氧化硅， 作为氧化隔离层； ii. CMP化学机械抛光， 使氧化硅平坦化， 并且停止在 Fin条顶部氮化硅硬 掩膜表面；
iii. 利用湿法腐蚀回刻新淀积的氧化硅直 Fin条露出设计的高度作为沟道区 域；
c) 形成栅结构和源漏结构
L ALD淀积一层栅介质层；
ii. PVD淀积一层栅材料；
iii. 通过电子束光刻， 刻蚀栅材料， 形成栅线条；
iv. 通过离子增强化学汽相淀积以及回刻；
v. 进行离子注入和退火， 形成源漏结构。
2. 一种锗、 三五族半导体材料衬底上制备 FinFET的方法， 包括如下步骤： a) 形成源漏和连接源漏的细条状的图形结构
i. 在硅衬底上采用离子增强化学气相淀积氧化硅、 氮化硅作为硬掩膜； ii. 通过一次电子束光刻， 刻蚀氮化硅、 氧化硅工艺， 在硬掩膜上形成源漏 和连接源漏的 Fin条的图形结构；
iii. 去掉电子束光刻胶；
iv. 各向异性干法刻蚀锗、 三五族衬底， 将硬掩膜上的图形结构转移到衬底 材料上； b) 形成氧化隔离层的方案
i. 淀积一层新的氮化硅；
ii. 利用各项异性干法刻蚀刻蚀新的氮化硅， 在 Fin条两侧形成氮化硅侧墙； iii. 利用各项异性干法刻蚀刻蚀 Fin条两侧裸露出来的锗、 三五族半导体材 料衬底；
iv. 利用各项同性干法刻蚀刻蚀 Fin条两侧裸露凹陷下去的锗、 三五族半导 体材料衬底， 以及完全刻蚀掉或部分刻蚀掉 Fin条底部的锗、三五族半导体材料 衬底；
v. 采用离子增强化学气相淀积一层新的氧化硅， 作为氧化隔离层； vi. CMP化学机械抛光， 使氧化硅平坦化， 并且停止在 Fin条顶部氮化硅硬 掩膜表面；
vii. 利用湿法腐蚀回刻新淀积的氧化硅直 Fin条露出设计的高度作为沟道区 域；
c) 形成栅结构和源漏结构
i. ALD淀积一层栅介质层；
ii. PVD淀积一层栅材料；
iii. 通过电子束光刻， 刻蚀栅材料， 形成栅线条；
iv. 通过离子增强化学汽相淀积以及回刻；
v. 进行离子注入和退火， 形成源漏结构。
3. 如权利要求 1或 2所述的锗、三五族半导体材料衬底上制备 FinFET的方 法， 其特征在于： 所属步骤 c)中， High-k栅介质和金属栅材料分别由 ALD和 PVD完成。
4. 如权利要求 1或 2所述的锗、三五族半导体材料衬底上制备 FinFET的方 法， 其特征在于： 所属步骤 c)中， 在光刻栅材料之前先进行一次 CMP使得栅材 料平坦化， 并且平面表面为 Fin条顶部氧化硅硬掩膜表面， 然后再通过光刻刻蚀 技术， 在 Fin条两侧形成两个相互不连接， 独立的栅线条。
5. 如权利要求 1或 2所述的锗、三五族半导体材料衬底上制备 FinFET的方 法， 其特征在于： 所述步骤 a)、 c)中， 光刻形成源漏和连接源漏的细条状图形结 构， 采用电子束光刻技术形成细栅图形结构。
6. 如权利要求 1或 2所述的锗、三五族半导体材料衬底上制备 FinFET的方 法， 其特征在于： 所述步骤 a)、 b)中， 淀积工艺采用 PECVD技术。
7. 如权利要求 1或 2所述的锗、三五族半导体材料衬底上制备 FinFET的方 法， 其特征在于： 所述步骤 c)中， 涉及的退火工艺为低温退火， 退火温度范围为 300°C~500°C。
PCT/CN2013/079018 2012-09-05 2013-07-08 锗、三五族半导体材料衬底上制备FinFET的方法 WO2014036855A1 (zh)

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