WO2012159314A1 - 一种空气为侧墙的围栅硅纳米线晶体管的制备方法 - Google Patents

一种空气为侧墙的围栅硅纳米线晶体管的制备方法 Download PDF

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WO2012159314A1
WO2012159314A1 PCT/CN2011/076805 CN2011076805W WO2012159314A1 WO 2012159314 A1 WO2012159314 A1 WO 2012159314A1 CN 2011076805 W CN2011076805 W CN 2011076805W WO 2012159314 A1 WO2012159314 A1 WO 2012159314A1
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drain
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黄如
诸葛菁
樊捷闻
艾玉杰
王润声
黄欣
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北京大学
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Priority to US13/384,215 priority Critical patent/US8563370B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates

Definitions

  • the present invention relates to the field of CMOS Very Large Scale Integrated Circuit (ULSI) manufacturing technology, and in particular to a method for fabricating a gate-side silicon nanowire transistor for an air sidewall.
  • CMOS Very Large Scale Integrated Circuit ULSI
  • ULSI Very Large Scale Integrated Circuit
  • BACKGROUND OF THE INVENTION As device sizes shrink to deep submicron, the gate control capability of conventional planar transistors is weakened, and short channel effects are becoming more and more pronounced, leading to a series of problems such as threshold voltage drift, subthreshold slope increase, subthreshold leakage current. Increase, leakage caused by barrier reduction effects, and so on.
  • a multi-gate structure can be used to increase the gate-to-channel control capability.
  • the extreme structure of the multi-gate structure is the surrounding gate silicon nanowire structure. Due to the excellent gate control capability and one-dimensional quasi-ballistic transport potential of the fence structure, the fenced silicon nanowire transistor can obtain very good subthreshold characteristics and improve the current switching ratio. , enhance current drive capability. In addition, it has good CMOS process compatibility, so the fenced silicon nanowire transistor is considered to be a device that is expected to replace planar transistors in the future.
  • a material with a lower dielectric constant can be used as the sidewall spacer, which can reduce the capacitive coupling effect between the gate and the source and drain, thereby reducing the edge parasitic capacitance.
  • Air has a very low dielectric constant, and a cross-sectional view of the surrounding gate silicon nanowire transistor with air as a side wall along the channel direction is shown in Fig. 2.
  • the transistor was fabricated on a SOI (Si l icon-On-Insulator, silicon on an insulating substrate) substrate.
  • a method for fabricating a gate-wall silicon nanowire transistor with air as a sidewall characterized in that it is prepared on a SOI substrate and comprises the following steps: 1) isolation process;
  • lithography defines a channel region and a large source and drain region
  • the step 1) uses silicon island isolation or local oxidation isolation of silicon (L0C0S).
  • the steps 2), 5), 9), 14), 19) employ a chemical vapor deposition method.
  • the steps 4), 7), 8), 16) are anisotropic dry etching.
  • the step 10) uses an anisotropic dry etching to ensure that SiN remains above the source and drain without being completely etched away.
  • the step 11) employs dry oxygen oxidation or hydrogen oxygen synthesis oxidation.
  • the step 12) uses hydrofluoric acid to remove the oxide layer.
  • the step 13) uses dry oxygen oxidation to form a 310 2 dielectric layer, and other high dielectric constant dielectric layers may also be used.
  • the step 18) uses concentrated phosphoric acid at 170 ° C to remove SiN.
  • Advantageous Effects of Invention provides a method for preparing a silicon nanowire transistor with air as a sidewall, which is compatible with a CMOS process flow, and introduction of an air sidewall can effectively reduce parasitic capacitance of the device and improve transient response of the device.
  • FIG. 1 is a schematic diagram of the edge capacitance of a gated silicon nanowire device
  • Figure 2 is a cross-sectional view of the Si0 2 and air sidewall spacers along the channel direction
  • Embodiment 1 The process flow of the enclosure silicon nanowire device for the air sidewall is as follows:
  • Lithography defines the channel region and large source and drain regions
  • ICP inductively coupled plasma
  • the dry oxygen oxidized SiO 2 is etched away with buffered hydrofluoric acid (BHF) to form suspended nanowires, as shown in FIG.
  • ICP Inductively Coupled Plasma
  • Reactive Si etching is used to etch Si0 2 3000A
  • buffered hydrofluoric acid BHF is used to corrode the remaining silicon oxide in the hole, and the glue is cleaned.
  • Example 2 As in Example 1, the difference is:
  • ICP inductively coupled plasma
  • the buffered hydrofluoric acid (BHF) is used to oxidize the 810 2 of the hydrogen-oxygen synthesis oxidation to form suspended nanowires.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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Abstract

提供了一种空气为侧墙的围栅硅纳米线晶体管的制备方法，包括：隔离并淀积SiN（3）；淀积SiO2（5）定义沟道区和大源漏区；将光刻胶上的图形转移到SiN（3）和SiO2（5）硬掩膜上；淀积与Si有高刻蚀选择比的材料；定义Fin条；形成Fin和大源漏的硬掩膜；形成Si的Fin条和大源漏；淀积SiN（3）；蚀刻SiN（3），形成SiN（3）侧墙；氧化，形成纳米线；去除氧化层，形成悬空纳米线；形成栅氧化层；淀积多晶硅（4）；定义栅线条，将光刻胶上的图形转移到多晶硅（4）上；多晶硅（4）和源漏注入；湿法腐蚀SiN（3）；淀积SiO2（5）形成空气侧墙；退火激活杂质；完成器件制备。与CMOS工艺流程相兼容，空气侧墙的引入能有效减少器件的寄生电容，提高器件瞬态响应特性，适用于高性能逻辑电路应用。

Description

一种空气为侧墙的围栅硅纳米线晶体管的制备方法
技术领域 本发明属于 CMOS超大规模集成电路 (ULSI)制造技术领域， 具体涉及一种空气侧墙的围栅 硅纳米线晶体管的制备方法。 背景技术 随着器件尺寸縮小到深亚微米， 传统平面晶体管的栅控能力减弱， 短沟道效应越来越明 显， 导致一系列问题， 如阈值电压漂移、 亚阈值斜率增加、 亚阈区泄漏电流增加、 漏致势垒 降低效应等等。 为了抑制日益恶化的短沟道效应， 可以采用多栅结构， 增加栅对沟道的控制 能力。 多栅结构的极致为围栅硅纳米线结构， 由于围栅结构优秀的栅控能力和一维准弹道输 运潜力， 围栅硅纳米线晶体管能够获得非常好的亚阈值特性、 提高电流开关比、 增强电流驱 动能力。 另外， 还具有良好的 CMOS工艺兼容能力， 因此围栅硅纳米线晶体管被认为是一种未 来有希望取代平面晶体管的器件。
但是由于其围栅、 纳米级沟道的结构特点， 栅和源漏之间的边缘 (fringing)寄生电容不 可忽略， 如图 1所示， 从而严重影响器件的瞬态响应特性。
为了减小寄生电容， 可以釆用较低介电常数的材料作为侧墙， 能够减小栅和源漏之间的 电容耦合效应， 从而减小边缘寄生电容。 空气具有极低的介电常数， 以空气为侧墙的围栅硅 纳米线晶体管沿着沟道方向的剖面图如图 2所示。
由于纳米线独特的三维结构， 如何形成空气侧墙需要特殊的工艺流程设计， 这方面的研 究目前未见报道。 发明内容 本发明的目的是提供一种以空气为侧墙的围栅硅纳米线晶体管的制备方法。 该晶体管在 SOI (Si l icon-On-Insulator, 绝缘衬底上的硅）衬底上制备。
本发明提供的技术方案如下：
一种空气为侧墙的围栅硅纳米线晶体管的制备方法， 其特征在于， 在 S0I衬底上制备， 包括如下步骤： 1) 隔离工艺；
2) 淀积 Si02、 淀积 SiN;
3) 光刻定义沟道区和大源漏区；
4) 通过刻蚀将光刻胶上的图形转移到 SiN和 Si02硬掩膜上；
5) 淀积与 Si有高刻蚀选择比的材料 A (如 Si02、 SiN等）；
6) 光刻定义 Fin (鰭状细线条)条；
7) 通过刻蚀将光刻胶上的图形转移到材料 A上， 形成 Fin和大源漏的硬掩膜；
8) 以材料 A和 SiN为硬掩膜， 刻蚀 Si， 形成 Si Fin条和大源漏；
9) 淀积 SiN;
10)刻蚀 SiN， 形成 SiN侧墙；
11)氧化， 形成纳米线；
12)湿法去除氧化层， 形成悬空纳米线；
13)形成栅氧化层；
14)淀积多晶硅；
15)光刻定义栅线条；
16)通过刻蚀将光刻胶上的图形转移到多晶硅上；
17)注入多晶硅和源漏；
18)湿法腐蚀 SiN;
19)淀积 Si02， 形成空气侧墙；
20)退火激活杂质；
21)采用常规 CMOS后端工艺完成后续流程， 完成器件制备。
所述歩骤 1 )采用硅岛隔离或者硅的局部氧化隔离 (L0C0S)。
所述歩骤 2)、 5)、 9)、 14)、 19) 采用的是化学气相淀积方法。
所述步骤 4)、 7)、 8)、 16) 采用的是各向异性干法刻蚀。
所述步骤 10)采用的是各项异性干法刻蚀， 要保证源漏上方仍然有 SiN保留而不是全部 被刻蚀掉。
所述步骤 11)采用的是干氧氧化或氢氧合成氧化。
所述步骤 12)采用的是氢氟酸去掉氧化层。
所述步骤 13)采用的是干氧氧化形成 3102介质层，也可以采用其他高介电常数的介质层。 所述歩骤 18)采用的是 170°C浓磷酸去除 SiN。 本发明的有益效果： 本发明提供的以空气为侧墙的硅纳米线晶体管的制备方法， 与 CMOS 工艺流程相兼容， 空气侧墙的引入能有效减小器件的寄生电容， 提高器件瞬态响应特性， 适 用于高性能逻辑电路应用。 附图说明 图 1围栅硅纳米线器件边缘电容示意图
图 2 Si02和空气侧墙的围栅硅纳米线器件沿着沟道方向的截面图
图 3到图 13是实施实例的工艺流程图， 图中各层材料的说明如下：
1-Si 2-埋氧化层
3-SiN 4-多晶硅
5- Si02 6-空气
具体实施方式 下面结合附图和具体实施例对本发明作进一歩阐述。
实施例 1 : 空气侧墙的围栅硅纳米线器件的工艺流程如下：
从 S0I衬底 (埋氧化层上的 Si厚度为 2500 A)出发：
1. 采用硅岛隔离方法
2. 低压化学气相淀积 （LPCVD) Si02300 A
3. 低压化学气相淀积 (LPCVD) S1N1500 A, 如图 3所示
4. 光刻定义沟道区和大源漏区
5. 采用反应离子刻蚀技术 （RIE)刻蚀 SiN1500 A、 Si02300 A， 形成大源漏区的硬掩膜， 并 去胶清洗， 如图 4所示
6. 淀积 SiN300 A, 如图 5所示
7. 光刻定义 Fin条的硬掩模
8.采用反应离子刻蚀技术（RIE)刻蚀 SiN300 A， 将光刻胶上的图形转移到 SiN上， 形成 SiN 的 Fin硬掩模， 并去胶清洗， 如图 6所示
9. 以 SiN为硬掩模， 感应耦合等离子 （ICP)刻蚀 Si2500 A， 形成 Si Fin条和大源漏， 如 图 7所示
10. 低压化学气相淀积 (LPCVD) S皿 500A 11. 采用反应离子刻蚀技术 （RIE) 刻蚀 SiN2500A， 形成 SiN侧墙， 如图 8所示
12. 干氧氧化， 形成硅纳米线
13. 釆用缓冲氢氟酸 （BHF)将干氧氧化的 Si02腐蚀掉， 形成悬空纳米线， 如图 9所示
14. 栅氧氧化， 形成 5纳米栅氧化层
15. 低压化学气相淀积 (LPCVD) 多晶硅 2000A, 如图 10所示
16. 光刻定义栅线条
17. 感应耦合等离子 （ICP)刻蚀多晶硅 2000A, 形成多晶硅栅， 并去胶清洗， 如图 11所示
18. As注入， 能量 50Kev， 剂量 4 X 1015 cm— 2， 如图 12所示
19. 170°C浓磷酸选择腐蚀 SiN, 将源漏上方的 SiN和 SiN侧墙去除干净
20. 低压化学气相淀积 (LPCVD) Si023000A， 形成空气侧墙， 如图 13所示
21. 氮气中 105CTC快速热退火 （RTP) 5秒钟， 激活杂质
22. 光刻金属接触孔
23.采用反应离子刻蚀技术 （RIE)刻蚀 Si023000A， 采用缓冲氢氟酸（BHF)将孔内剩余的氧 化硅腐蚀干净， 去胶清洗
24. 溅射 Ti/Al， 700A /Ι μ ιη
25. 光刻金属引线
26. RIE刻蚀 Al/Ti Ι μ ιιι /70θΑ, 去胶清洗
27. + 中430 下退火 30分钟， 合金化， 器件制备完成 实施例 2: 如实施实例 1， 不同之处在于：
1. 采用 L0C0S隔离方法
6. 淀积 Si02300 A
8. 采用反应离子刻蚀技术 （RIE)刻蚀 Si02300 A， 将光刻胶上的图形转移到 Si02上， 形成 Si02的 Fin硬掩模， 并去胶清洗
9. 以 Si02和 SiN为硬掩模， 感应耦合等离子 （ICP)刻蚀 Si2500 A， 形成 Si Fin条和大源 漏
12. 氢氧合成氧化， 形成硅纳米线
13. 采用缓冲氢氟酸 （BHF)将氢氧合成氧化的 8102腐蚀掉， 形成悬空纳米线，

Claims

权 利 要 求 书
1. 一种以空气为侧墙的围栅硅纳米线晶体管的制备方法， 其特征在于， 在 SOI衬底上制备， 包括如下歩骤：
1) 隔离工艺；
2) 淀积 Si02、 淀积 SiN;
3) 光刻定义沟道区和大源漏区；
4) 通过刻蚀将光刻胶上的图形转移到 SiN和 Si02硬掩膜上；
5) 淀积与 Si有高刻蚀选择比的材料 A;
6) 光刻定义 Fin条；
7) 通过刻蚀将光刻胶上的图形转移到材料 A上， 形成 Fin和大源漏的硬掩膜；
8) 以材料 A和 SiN为硬掩膜， 刻蚀 Si， 形成 Si Fin条和大源漏；
9) 淀积 SiN;
10)刻蚀 SiN， 形成 SiN侧墙；
11)氧化， 形成纳米线；
12)湿法去除氧化层， 形成悬空纳米线；
13)形成栅氧化层；
14)淀积多晶硅；
15)光刻定义栅线条；
16)通过刻蚀将光刻胶上的图形转移到多晶硅上；
17)注入多晶硅和源漏；
18)湿法腐蚀 SiN;
19)淀积 Si02， 形成空气侧墙；
20)退火激活杂质；
21)采用常规 CMOS后端工艺完成后续流程， 完成器件制备。
2. 如权利要求 1所述的制备方法， 其特征在于， 所述步骤 1 )采用硅岛隔离或者硅的局部氧 化隔离。
3. 如权利要求 1所述的制备方法， 其特征在于， 所述步骤 2)、 5)、 9)、 14)、 19)采用的是 化学气相淀积方法。
4. 如权利要求 1所述的制备方法， 其特征在于， 所述步骤 4)、 7)、 8)、 16)采用的是各向 异性干法刻蚀。
5. 如权利要求 1所述的制备方法， 其特征在于， 所述歩骤 10)采用的是各项异性干法刻蚀， 要保证源漏上方仍然有 SiN保留而不是全部被刻蚀掉。
6. 如权利要求 1所述的制备方法， 其特征在于， 所述步骤 11)采用的是干氧氧化或氢氧合成 氧化。
7. 如权利要求 1所述的制备方法， 其特征在于， 所述歩骤 12)采用的是氢氟酸去掉氧化层。
8. 如权利要求 1所述的制备方法， 其特征在于， 所述步骤 13)采用的是干氧氧化形成 Si02 介质层。
9. 如权利要求 1所述的制备方法，其特征在于，所述步骤 18)采用的是 170°C浓磷酸去除 SiN。
PCT/CN2011/076805 2011-05-26 2011-07-04 一种空气为侧墙的围栅硅纳米线晶体管的制备方法 WO2012159314A1 (zh)

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