WO2011147062A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2011147062A1
WO2011147062A1 PCT/CN2010/001489 CN2010001489W WO2011147062A1 WO 2011147062 A1 WO2011147062 A1 WO 2011147062A1 CN 2010001489 W CN2010001489 W CN 2010001489W WO 2011147062 A1 WO2011147062 A1 WO 2011147062A1
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gate
layer
semiconductor layer
semiconductor
forming
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PCT/CN2010/001489
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English (en)
French (fr)
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尹海洲
骆志炯
朱慧珑
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中国科学院微电子研究所
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Priority to CN201090000826.3U priority Critical patent/CN202585421U/zh
Priority to US13/062,911 priority patent/US8399315B2/en
Priority to GB1121727.0A priority patent/GB2483405B/en
Publication of WO2011147062A1 publication Critical patent/WO2011147062A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H01L29/6678—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates on sapphire substrates, e.g. SOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

Definitions

  • the present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to an ultrathin SOI transistor including a channel region formed in a semiconductor substrate and an elevated source/drain region (RSD) over the semiconductor substrate and Its manufacturing method.
  • RSD source/drain region
  • a conventional ultra-thin SOI transistor is formed on a SOI substrate including a bottom substrate 11, a buried oxide layer (BOX) 12, and a top semiconductor layer 13, including a channel region formed in the top semiconductor layer.
  • a gate including a gate dielectric '14 and a gate conductor 15 formed over the channel region, a sidewall 16 formed on the side of the gate, and RSDs 17a, 17b o
  • RSD reduces the source/drain resistance and minimizes the gate-source and gate-drain parasitic capacitance.
  • the RSD provides sufficient Si to participate in silicidation, preventing the Si in the source/drain regions from being completely consumed in silicidation.
  • the formation of the RSD includes pre-cleaning the top semiconductor layer of the ultra-thin SOI substrate and epitaxially growing the silicon layer thereon after forming the gate electrode and forming the spacer on the side of the gate electrode, which complicates the process of manufacturing the transistor. . Also, a portion of the top semiconductor layer of the ultra-thin S0I substrate located under the sidewall has a high resistance, and this portion is a part of the source-drain conductive path, resulting in an excessively high on-resistance of the device. Summary of the invention
  • a semiconductor structure including a semiconductor substrate; an epitaxial semiconductor layer, the epitaxial semiconductor layer is located at two sides above the semiconductor substrate; and a gate, the gate is located above the semiconductor substrate An intermediate position and adjacent to the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer sandwiched between the gate conductor layer and the semiconductor substrate and laterally surrounding the gate conductor; and a sidewall spacer The side walls are located above the epitaxial semiconductor layer and on both sides of the gate.
  • a method of fabricating a semiconductor structure comprising the steps of: a) forming an epitaxial semiconductor layer on top of a semiconductor substrate; b) forming a sacrificial gate on the epitaxial semiconductor layer; c) at the expense Forming a sidewall around the gate; d) removing the sacrificial gate, forming a gate opening to expose the surface of the epitaxial semiconductor layer; e) removing a portion of the epitaxial semiconductor layer exposed from the gate opening; f) forming a gate opening a conformal gate dielectric; and g) forming a gate conductor in the gate opening.
  • an epitaxial semiconductor layer is formed first, and then an RSD is formed in the epitaxial semiconductor layer by using a sacrificial gate. This process does not require pre-cleaning and epitaxial growth after the patterning step, thereby simplifying the manufacturing process and increasing the yield.
  • the RSD extends below the sidewall and directly adjacent to the channel region, thereby reducing the resistance of the portion, thereby reducing the on-resistance and power consumption of the transistor.
  • Fig. 1 schematically shows a cross-sectional view of an ultrathin SOI transistor according to the prior art.
  • various portions of the semiconductor device may be constructed of materials well known to those skilled in the art.
  • the following steps of fabricating an ultrathin SOI transistor are sequentially performed in the order of Figs. 2 through 14.
  • a semiconductor substrate as an initial structure may be a common semiconductor substrate such as a Group IV semiconductor (e.g., silicon or germanium) or a Group III-V compound semiconductor (e.g., gallium arsenide).
  • the semiconductor substrate is a SOI (Silicon On Insulator) wafer including a base substrate 101, a buried oxide layer 102, and a top semiconductor layer 103. More preferably, the substrate is an ultrathin SOI substrate, wherein the thickness of the top semiconductor layer 103 is typically no more than 15 ⁇ , preferably no more than 10 ⁇ .
  • ultra-thin S0I substrates are well known in the art, for example, layer transfer techniques including wafer bonding can be employed. Alternatively, if a conventional S0I substrate is used, the desired thickness can be achieved by thinning the top semiconductor layer of the SOI substrate. '
  • the epitaxial semiconductor layer 104 for forming an RSD in a subsequent step is epitaxially grown on the top semiconductor layer 103 of the ultrathin S0I substrate in accordance with a conventional deposition process such as CVD, as shown in FIG.
  • the thickness of the epitaxial semiconductor layer 104 is typically 10 - 30 nm.
  • the epitaxial semiconductor layer 104 is composed of a material different from the top semiconductor layer 103 of the ultra-thin SOI substrate by an etch rate, thereby producing selectivity in an etching step described below, such as a top semiconductor of an ultra-thin SOI substrate.
  • Layer 103 is composed of silicon
  • epitaxial semiconductor layer 104 is composed of SiGe.
  • a gate electrode including a gate dielectric 105 and a gate conductor 106 is formed on top of the epitaxial semiconductor layer 104 in accordance with a conventional deposition process.
  • the gate acts as a sacrificial gate (also referred to as a "fake gate”) and is not part of the final transistor.
  • a process of forming a sacrificial gate may include sequentially forming a gate dielectric layer and a gate conductor layer by deposition, and then patterning it.
  • the patterning may include the steps of: forming a patterned photoresist mask on the gate conductor layer by a photolithography process including exposure and development; by thousand etching, such as ion milling, plasma etching, reactive ionization Sub-etching, laser ablation, or removing the exposed portions of the gate conductor layer and the gate dielectric layer by wet etching using an etchant solution, the etching step is stopped at the top of the epitaxial semiconductor layer; by dissolving in a solvent or Ashing removes the photoresist mask.
  • a layer of insulating material is deposited over the entire surface of the semiconductor structure. It is patterned to form a nitride spacer 107 (e.g., Si3N4) on the side and top of the gate.
  • a nitride spacer 107 e.g., Si3N4
  • the portion of the nitride spacer layer 107 at the top of the gate provides a cap for the stop layer and the protective layer in the subsequent planarization step.
  • ions are implanted into the exposed portion of the epitaxial semiconductor layer 104 using a sacrificial gate as a hard mask in accordance with a conventional MOS process to provide doped regions, thereby forming source/drain regions 121a, 121b.
  • in-situ doping may also be performed in the step of forming the epitaxial semiconductor layer 104 (see FIG. 3) as described above, whereby the epitaxial semiconductor layers (121a and 121b) remaining in the final transistor, as will be described later, See Figure M) for source/drain regions. '
  • the portion of the top semiconductor layer 103 of the ultra-thin S0I substrate that is below the sacrificial gate will form the channel region 120.
  • an interlayer insulating layer 108 (e.g., SiO 2 ) is formed on the exposed surface of the epitaxial semiconductor layer 104 and the nitride spacer layer 107 in accordance with a conventional deposition process for protecting the epitaxial semiconductor layer 104 in a subsequent step. .
  • a portion of the interlayer insulating layer 108 is removed by, for example, chemical mechanical planarization (CMP) using the cap of the nitride spacer 107 as a stop layer to obtain a flat surface of the semiconductor structure.
  • CMP chemical mechanical planarization
  • the cap of the nitride spacer 107 is removed, for example by additional CMP, to expose the surface of the gate conductor 106. At the same time, a portion of the nitride spacer layer 107 on the side of the gate remains as a spacer for the gate.
  • the cap of the nitride spacer 107 may be selectively removed by reactive ion etching (RIE).
  • RIE reactive ion etching
  • the sacrificial gate is removed by dry etching or selective wet etching to form an opening 109 exposing the surface of the epitaxial semiconductor layer 104 (see Fig. 8).
  • the portion of the epitaxial semiconductor layer 104 exposed from the opening 109 is removed by selective wet etching, which is stopped at the top of the top semiconductor layer 103 of the SOI substrate.
  • a conformal high-k dielectric layer 110 (e.g., HfO 2 ) is formed over the entire surface of the semiconductor structure in accordance with a conventional deposition process.
  • the high K dielectric layer 110 covers the sidewalls of the opening 109 and the ultra-thin SOI substrate
  • the top semiconductor layer 103 is exposed at the bottom of the mouth 109.
  • a gate conductor layer 111 (e.g., TiN) is formed on the entire surface of the semiconductor structure in accordance with a conventional deposition process.
  • the gate conductor layer 111 fills the gate 109 and covers the high-k dielectric layer around the opening 109.
  • the surface of 110 (see Figure 11).
  • the gate conductor layer 111 may be one or more layers. For example, a TiN layer may be deposited first, and then a ruthenium layer may be deposited as needed.
  • the portion of the gate dielectric layer 110 and the gate conductor layer 111 located around the opening 109 is removed, for example, by CMP, leaving only the co-formed gate dielectric layer 110 and the filled gate conductor layer 111 in the opening 109 for use as The gate of the final transistor (also known as the "alternative gate").
  • the interlayer insulating layer 108 is completely removed, for example, by a selective wet etching process, to expose the surface of the epitaxial semiconductor layer 104 to perform a silicidation step as described below.
  • a portion of the silicon exposed on the surface of the source/drain regions 121a, 121b is metal silicided according to a conventional MOS process, and unreacted metal is removed, thereby forming source/drain contact regions 122a, 122b.
  • a channel region 120 is formed in a top semiconductor layer of the ultra-thin SOI substrate, and source/drain regions 121a, 121b are formed in the epitaxial semiconductor layer above the top semiconductor layer.
  • a gate is formed over the channel region 120
  • the dielectric 110 and the gate conductor 111 are separated from the channel region 120 and the source/drain regions 121a, 121b by a gate dielectric 110.
  • the source/drain regions are located above the top semiconductor layer 103 of the SOI substrate, the source/drain regions
  • 121a, 121b are "elevated" relative to channel region 120, i.e., provide RSD in ultra-thin S0I transistors.
  • the source/drain regions 121a, 121b extend below the sidewall spacer 107 and abut the channel region 120, thereby reducing the on-resistance and power consumption of the device.

Description

半导体结构及其制造方法 技术领域
本发明涉及一种半导体结构及其制造方法，具体地涉及包括在半导体衬底中形成 的沟道区和在该半导体衬底上方的抬高的源 /漏区（RSD)的超薄 S0I晶体管及其制造 方法。 背景技术
集成电路的发展趋势是晶体管的尺寸的按比例缩小， 这将导致公知的短沟道效 应。近年来提出了超薄 S0I晶体管， 在超薄 S0I衬底的顶部半导体中形成的沟道区完 全耗尽， 从而实现了对短沟道效应的良好控制。
例如， 在 Cheng等人的文章 "Fully Depleted Extremely Thin SOI Technology Fabricated by a Novel Integration Scheme Featuring Implant-Free, Zero - Silicon- Loss, and Faceted Raised Source/Drain", 2009 Symposium on VLSI Technology Digest of Technical Papers, p212- 213公开了超薄 SOI晶体管的结构。
如图 1所示，常规的超薄 S0I晶体管形成在包含底部衬底 11、掩埋氧化物层 (BOX) 12、 顶部半导体层 13的 S0I衬底上， 包括在顶部半导体层中形成的沟道区， 在沟道 区上方形成的包括栅极电介质' 14和栅极导体 15的栅极， 在栅极侧面形成的侧墙 16、 以及 RSD 17a、 17b o
在上述超薄 S0I晶体管中， RSD减小了源 /漏电阻并使得栅-源和栅-漏寄生电容最 小化。 此外， 在源 /漏区上方形成硅化物时， RSD提供了足够的 Si参与硅化， 避免源 / 漏区的 Si在硅化中完全消耗掉。
然而， RSD的形成包括在形成栅极以及在栅极侧面形成侧墙之后， 对超薄 S0I衬 底的顶部半导体层进行预清洁并在其上外延生长硅层，这导致制造晶体管的工艺复杂 化。 并且， 超薄 S0I衬底的顶部半导体层位于侧墙下方的一部分具有高电阻， 而该部 分是源 -漏导电路径的一部分， 从而导致器件的导通电阻过高。 发明内容
本发明的目的是提供一种容易制造且具有减小的导通电阻的半导体结构及其制 造方法。 根据本发明的一方面， 提供一种半导体结构， 包括半导体衬底； 外延半导体层， 所述外延半导体层位于半导体衬底上方的两侧位置； 栅极， 所述栅极位于半导体衬底 上方的中间位置并且与外延半导体层相邻，所述栅极包括栅极导体层和夹在栅极导体 层和半导体衬底之间并在侧面环绕栅极导体的栅极电介质层； 以及侧墙， 所述侧墙位 于外延半导体层上方以及所述栅极的两侧。
根据本发明的另一方面， 提供一种制造半导体结构的方法， 包括以下步骤： a)在 半导体衬底的顶部形成外延半导体层； b)在外延半导体层上形成牺牲栅极； c)在牺牲 栅极周围形成侧墙； d)去除牺牲栅极， 形成栅极开口， 以暴露外延半导体层的表面； e)去除外延半导体层从栅极幵口暴露的部分； f)在栅极开口中形成共形的栅极电介 质； 以及 g)在栅极开口中形成栅极导体。
在本发明的半导体结构和方法中， 先形成了外延半导体层， 然后利用牺牲栅极在 该外延半导体层中形成 RSD。该工艺不需要在图案化步骤之后执行预清洁和外延生长， 从而简化了制造工艺， 并提高了产率。
而且， 在本发明的半导体结构中， RSD延伸到侧墙下方， 与直接与沟道区相邻， 从而减小了该部分的电阻， 进而减小了晶体管的导通电阻和功耗。 附图说明
图 1示意性地示出了根据现有技术的超薄 S0I晶体管的截面图。
图 2至 14示意性地示出根据本发明的半导体结构的制造方法的各个阶段的截面 图。 具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中， 相同的元件采用类似的附 图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。
应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另一层、 另一个 区域 "上面"或 "上方" 时， 可以指直接位于另一层、 另一个区域上面， 或者在其与 另一层、 另一个区域之间还包含其它的层或区域。 并且， 如果将器件翻转， 该一层、 一个区域将位于另一层、 另一个区域 "下面"或 "下方" 。
如果为了描述直接位于另一层、 另一个区域上面的情形， 本文将釆用 "直接 在……上面"或 "在……上面并与之 ¾接" 的表述方式。 在下文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处理 工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员能够理解的那样， 可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知 的材料构成。
根据本发明的优选实施例， 按照图 2至 14的顺序依次执行制造超薄 S0I晶体管 的以下步骤。
参见图 2所示， 作为初始结构的半导体衬底， 可以为常见的半导体衬底， 例如 IV 族半导体 （如， 硅或锗） 或 III族- V族化合物半导体 （如， 砷化镓）。 优选地， 与图 1所示的现有技术相同， 该半导体衬底为 S0I (绝缘体上硅）晶片， 包括底部衬底 101、 掩埋氧化物层 102和顶部半导体层 103。 更优选地， 衬底为超薄 S0I衬底， 其中， 顶 部半导体层 103的厚度典型地为不大于 15ηηι， 优选不大于 10皿。
超薄 S0I衬底的制备已经是本领域公知的，例如可以采用包括晶片键合的层转移 技术。 可选地， 如果釆用普通的 S0I衬底， 则可以通过对 S0I衬底的顶部半导体层进 行减薄来达到所需的厚度。 '
按照常规的淀积工艺， 如 CVD, 在超薄 S0I衬底的顶部半导体层 103上外延生长 用于在随后的步骤中形成 RSD的外延半导体层 104，如图 3所示。该外延半导体层 104 的厚度典型地为 10- 30nm。
在下文中， 为了简明的目的， 除非指明特定的淀积工艺， 不再详述所釆用的淀积 工艺。
优选地，该外延半导体层 104由与超薄 S0I衬底的顶部半导体层 103由蚀刻速率 不同的材料构成， 从而在下文所述的蚀刻步骤中产生选择性， 例如超薄 S0I衬底的顶 部半导体层 103由硅构成， 外延半导体层 104由 SiGe构成。
' 如图 4所示， 按照常规的淀积工艺， 在外延半导体层 104顶部形成包括栅极电介 质 105和栅极导体 106的栅极。如下文所述，该栅极用作牺牲栅极（也称为"假栅极")， 而不作为最终晶体管的一部分。
例如，形成牺牲栅极的工艺可以包括通过淀积依次形成栅极电介质层和栅极导体 层， 然后对其图案化。
该图案化可以包括以下步骤： 通过包含曝光和显影的光刻工艺， 在栅极导体层上 形成含有图案的光抗蚀剂掩模； 通过千法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离 子蚀刻、 激光烧蚀， 或者通过其中使用蚀刻剂溶液的湿法蚀刻， 去除栅极导体层和栅 极电介质层的暴露部分， 该蚀刻步骤停止在外延半导体层的顶部； 通过在溶剂中溶解 或灰化去除光抗蚀剂掩模。
在下文中， 为了简明的目的， 除非指明特定的图案化工艺， 不再详述所釆用的图 案化工艺。
然后， 在半导体结构的整个表面上， 淀积绝缘材料层。 对其进行图案化， 形成栅 极的侧面及顶部的氮化物隔离层 107 (如 Si3N4)。
氮化物隔离层 107位于栅极的顶部的部分提供了在随后的平面化步骤中作为停止 层和保护层的帽盖。
接着， 可选地， 按照常规的 M0S工艺， 利用牺牲栅极作为硬掩模， 向外延半导体 层 104的暴露部分注入离子， 提供掺杂区域， 从而形成了源 /漏区 121a、 121b。
替代地， 也可以在前面所述形成外延半导体层 104 (参见图 3) 的步骤中， 进行 原位掺杂， 从而， 如后面所述的， 最终晶体管中保留的外延半导体层 （121a和 121b， 参见图 M) 用作源 /漏区。 '
另外，超薄 S0I衬底的顶部半导体层 103的位于牺牲栅极下方的部分将形成沟道 区 120。 '
如图 5所示， 按照常规的淀积工艺， 在外延半导体层 104的暴露表面和氮化物隔 离层 107上形成层间绝缘层 108(如 Si02)，用于在随后的步骤保护外延半导体层 104。
如图 6所示， 例如通过化学机械平面化（CMP), 利用氮化物隔离层 107的帽盖作 为停止层， 去除层间绝缘层 108的一部分， 以获得半导体结构的平整表面。
如图 7所示， 例如通过附加的 CMP, 去除氮化物隔离层 107的帽盖， 以暴露栅极 导体 106的表面。同时，氮化物隔离层 107位于栅极侧面的部分保留作为栅极的侧墙。
替代地， 可以首先通过反应离子蚀刻 （RIE) 选择性地去除氮化物隔离层 107的 帽盖。
然后， 通过干法蚀刻或选择性的湿法蚀刻， 去除牺牲栅极， 形成暴露外延半导体 层 104的表面的开口 109 (参见图 8)。
进一步地， 如图 9所示， 通过选择性的湿法蚀刻， 去除外延半导体层 104从开口 109中暴露的部分， 该蚀刻在 S0I衬底的顶部半导体层 103的顶部停止。
如图 10所示，按照常规的淀积工艺，在半导体结构的整个表面上形成共形的高 K 电介质层 110 (如 Hf02)。 该高 K电介质层 110覆盖开口 109的侧壁和超薄 S0I衬底 的顶部半导体层 103在幵口 109的底部暴露的表面。
接着，按照常规的淀积工艺，在半导体结构的整个表面上形成栅极导体层 111 (如 TiN) c 该栅极导体层 111填充了幵口 109， 并且覆盖了开口 109周围的高 K电介质层 110的表面 （参见图 11 )。 这里， 栅极导体层 111可以为一层或多层。 例如， 根据需 要， 可以先淀积 TiN层， 然后再淀积 ΠΑ1Ν层。
例如通过 CMP, 去除栅极电介质层 110和栅极导体层 111的位于开口 109周围的 部分， 仅在开口 109中留下共形成的栅极电介质层 110和填充的栅极导体层 111， 用 作最终晶体管的栅极 （也称为 "替代栅极")。
可选地， 如图 13所示， 例如通过选择性的湿法蚀刻工艺， 完全去除层间绝缘层 108， 以暴露外延半导体层 104的表面执行如下所述的硅化步骤。
接着， 按照常规的 M0S工艺， 对源 /漏区 121a、 121b表面上露出的一部分硅进行 金属硅化， 并去除未反应的金属， 从而形成源 /漏接触区 122a， 122b。
当然， 本领域技术人员可以理解的是， 也可以不进行去除层间绝缘层 108的操作 步骤， 在后续的步骤， 根据需要直接在层间绝缘层 108上形成开口， 例如接触孔， 然 后如上面所述的， 在接触孔中进行金属硅化以及去除未反应的金属的操作。
最终完成的晶体管如图 14所示。 在超薄 S0I衬底的顶部半导体层中形成了沟道 区 120， 而在该顶部半导体层上方的外延半导体层中形成了源 /漏区 121a、 121b. 在 沟道区 120上方形成了栅极电介质 110和栅极导体 111 , 栅极导体 111与沟道区 120 和源 /漏区 121a、 121b之间由栅极电介质 110隔开。
由于外延半导体层 104位于 S0I 衬底的顶部半导体层 103 上方， 从而源 /漏区
121a, 121b相对于沟道区 120是 "抬高的"， 即提供了超薄 S0I晶体管中的 RSD。
该源 /漏区 121a、 121b延伸到侧墙 107下方， 并与沟道区 120邻接， 从而减小了 器件的导通电阻和功耗。
以上描述只是为了示例说明和描述本发明， 而非意图穷举和限制本发明。 因此， 本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改， 均 在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种半导体结构， 包括
半导体衬底；
外延半导体层， 所述外延半导体层位于半导体衬底上方的两侧位置； 栅极， 所述栅极位于半导体衬底上方的中间位置并且与外延半导体层相邻， 所述 栅极包括栅极导体层和夹在栅极导体层和半导体衬底之间并在侧面环绕栅极导体的 栅极电介质层； 以及
侧墙， 所述侧墙位于外延半导体层上方以及所述栅极的两侧。
2、 根据权利要求 1所述的半导体结构， 其中所述半导体衬底为选自 IV族半导体 衬底、 III族- V族半导体衬底、 S0I衬底构成的组中的一种。
3、 根据权利要求 2所述的半导体结构， 其中 S0I衬底的顶部半导体层与所述外 延半导体层由不同蚀刻速率的材料构成。
4、 根据权利要求 2所述的半导体结构， 其中所述 S0I衬底的顶部半导体层的厚 度不大于 15應。
5、 一种制造半导体结构的方法， 包括以下步骤- a)在半导体衬底的顶部形成外延半导体层；
b)在外延半导体层上形成牺牲栅极；
c)在牺牲栅极周围形成侧墙；
d)去除牺牲栅极， 形成栅极开口， 以暴露外延半导体层的表面；
e)去除外延半导体层从栅极开口暴露的部分；
f)在栅极开口中形成共形的栅极电介质； 以及
g)在栅极开口中形成栅极导体。
6、 根据权利要求 5所述的方法， 其中步骤 b)包括形成用作牺牲栅极的栅极电介 质层和栅极导体层的叠层， 然后对其图案化。
7、根据权利要求 5所述的方法，其中步骤 c)包括在牺牲栅极的侧面和 /或顶部形 成氮化物隔离层。
8、 根据权利要求 7所述的方法， 其中在形成氮化物隔离层之后， 利用氮化物隔 离层作为停止层执行平面化处理， 以及利用附加的平面化处理或反应离子蚀刻， 以去 除氮化物隔离层位于牺牲栅极顶部的部分。
9、 根据权利要求 5所述的方法， 其中步骤 c)还包括形成用于保护外延半导体层 的层间绝缘层。
10、 根据权利要求 5所述的方法， 其中在步骤 c) 和 d) 之间还包括利用牺牲栅 极作为硬掩模， 向外延半导体中注入离子而形成源 /漏区的步骤。
11、根据权利要求 5所述的方法， 其中在步骤 g)之后还包括对源 /漏区表面上露 出的一部分进行金属硅化以形成源 /漏接触区的步骤。
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CN103383914B (zh) * 2012-05-02 2016-03-02 中国科学院微电子研究所 半导体结构及其制造方法
US8847315B2 (en) * 2012-05-07 2014-09-30 Qualcomm Incorporated Complementary metal-oxide-semiconductor (CMOS) device and method
US9252270B2 (en) * 2012-12-13 2016-02-02 Globalfoundries Singapore Pte. Ltd. Floating body cell
US9385044B2 (en) * 2012-12-31 2016-07-05 Texas Instruments Incorporated Replacement gate process
CN104008974A (zh) * 2013-02-26 2014-08-27 中国科学院微电子研究所 半导体器件及其制造方法
CN104008973A (zh) * 2013-02-26 2014-08-27 中国科学院微电子研究所 半导体器件的制造方法
CN106601617A (zh) * 2015-10-16 2017-04-26 中国科学院微电子研究所 半导体器件制造方法
FR3066646B1 (fr) * 2017-05-18 2019-12-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Realisation d'un transistor mos a base d'un materiau semiconducteur bidimensionnel
CN114121677B (zh) * 2022-01-27 2022-05-27 澳芯集成电路技术(广东)有限公司 一种fdsoi器件的沟道制作工艺优化方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1624885A (zh) * 2003-10-22 2005-06-08 国际商业机器公司 制造具有凹入沟道的薄soi cmos的方法及其制造的器件
US7279430B2 (en) * 2004-08-17 2007-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Process for fabricating a strained channel MOSFET device
CN101552293A (zh) * 2008-03-31 2009-10-07 万国半导体股份有限公司 用于使用多晶硅的沟槽dmos器件的源极和本体连接结构

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6063677A (en) * 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate and raised source and drain
US6225173B1 (en) * 1998-11-06 2001-05-01 Advanced Micro Devices, Inc. Recessed channel structure for manufacturing shallow source/drain extensions
US6452229B1 (en) * 2002-02-21 2002-09-17 Advanced Micro Devices, Inc. Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication
US8878292B2 (en) * 2008-03-02 2014-11-04 Alpha And Omega Semiconductor Incorporated Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
US7955909B2 (en) * 2008-03-28 2011-06-07 International Business Machines Corporation Strained ultra-thin SOI transistor formed by replacement gate
JP2010251344A (ja) * 2009-04-10 2010-11-04 Hitachi Ltd 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1624885A (zh) * 2003-10-22 2005-06-08 国际商业机器公司 制造具有凹入沟道的薄soi cmos的方法及其制造的器件
US7279430B2 (en) * 2004-08-17 2007-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Process for fabricating a strained channel MOSFET device
CN101552293A (zh) * 2008-03-31 2009-10-07 万国半导体股份有限公司 用于使用多晶硅的沟槽dmos器件的源极和本体连接结构

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