CN202585421U - 一种半导体结构 - Google Patents

一种半导体结构 Download PDF

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CN202585421U
CN202585421U CN201090000826.3U CN201090000826U CN202585421U CN 202585421 U CN202585421 U CN 202585421U CN 201090000826 U CN201090000826 U CN 201090000826U CN 202585421 U CN202585421 U CN 202585421U
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尹海洲
骆志炯
朱慧珑
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Abstract

提供了一种半导体结构及其制造方法，该半导体结构包括半导体衬底(101)；外延半导体层，外延半导体层位于半导体衬底上方的两侧位置；栅极，所述栅极位于半导体衬底上方的中间位置并且与外延半导体层相邻，和侧墙(107)，所述侧墙位于外延半导体层上方和所述栅极两侧，其中，所述栅极包括栅极导体层(111)和夹在栅极导体层和半导体衬底之间并在侧面环绕栅极导体的栅极电介质层(110)。该半导体结构的制造方法包括利用牺牲栅极在外延半导体层中形成抬高的源/漏区(121a，121b)的步骤。该半导体结构及其制造方法可用于简化超薄SOI晶体管的制造工艺和减小其导通电阻和功耗。

Description

一种半导体结构
技术领域
本发明涉及一种半导体结构及其制造方法，具体地涉及包括在半导体衬底中形成的沟道区和在该半导体衬底上方的抬高的源/漏区(RSD)的超薄SOI晶体管及其制造方法。 
背景技术
集成电路的发展趋势是晶体管的尺寸的按比例缩小，这将导致公知的短沟道效应。近年来提出了超薄SOI晶体管，在超薄SOI衬底的顶部半导体中形成的沟道区完全耗尽，从而实现了对短沟道效应的良好控制。 
例如，在Cheng等人的文章“Fully Depleted Extremely Thin SOI Technology Fabricated by a Novel Integration Scheme Featuring Implant-Free，Zero-Silicon-Loss，and Faceted Raised Source/Drain”，2009 Symposium on VLSI Technology Digest of Technical Papers，p212-213公开了超薄SOI晶体管的结构。 
如图1所示，常规的超薄SOI晶体管形成在包含底部衬底11、掩埋氧化物层(BOX)12、顶部半导体层13的SOI衬底上，包括在顶部半导体层中形成的沟道区，在沟道区上方形成的包括栅极电介质14和栅极导体15的栅极，在栅极侧面形成的侧墙16、以及RSD 17a、17b。 
在上述超薄SOI晶体管中，RSD减小了源/漏电阻并使得栅-源和栅-漏寄生电容最小化。此外，在源/漏区上方形成硅化物时，RSD提供了足够的Si参与硅化，避免源/漏区的Si在硅化中完全消耗掉。 
然而，RSD的形成包括在形成栅极以及在栅极侧面形成侧墙之后，对超薄SOI衬底的顶部半导体层进行预清洁并在其上外延生长硅层，这导致制造晶体管的工艺复杂化。并且，超薄SOI衬底的顶部半导体层位于侧墙下方的一部分具有高电阻，而该部分是源-漏导电路径的一部分，从而导致器件的导通电阻过高。 
发明内容
本发明的目的是提供一种容易制造且具有减小的导通电阻的半导体结构及其制造方法。 
根据本发明的一方面，提供一种半导体结构，包括半导体衬底；外延半导体层，所述外延半导体层位于半导体衬底上方的两侧位置；栅极，所述栅极位于半导体衬底上方的中间位置并且与外延半导体层相邻，所述栅极包括栅极导体层和夹在栅极导体层和半导体衬底之间并在侧面环绕栅极导体的栅极电介质层；以及侧墙，所述侧墙位于外延半导体层上方以及所述栅极的两侧。 
根据本发明的另一方面，提供一种制造半导体结构的方法，包括以下步骤：a)在半导体衬底的顶部形成外延半导体层；b)在外延半导体层上形成牺牲栅极；c)在牺牲栅极周围形成侧墙；d)去除牺牲栅极，形成栅极开口，以暴露外延半导体层的表面；e)去除外延半导体层从栅极开口暴露的部分；f)在栅极开口中形成共形的栅极电介质；以及g)在栅极开口中形成栅极导体。 
在本发明的半导体结构和方法中，先形成了外延半导体层，然后利用牺牲栅极在该外延半导体层中形成RSD。该工艺不需要在图案化步骤之后执行预清洁和外延生长，从而简化了制造工艺，并提高了产率。 
而且，在本发明的半导体结构中，RSD延伸到侧墙下方，与直接与沟道区相邻，从而减小了该部分的电阻，进而减小了晶体管的导通电阻和功耗。 
附图说明
图1示意性地示出了根据现有技术的超薄SOI晶体管的截面图。 
图2至14示意性地示出根据本发明的半导体结构的制造方法的各个阶段的截面图。 
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。 
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。 
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“直接在……上面”或“在……上面并与之邻接”的表述方式。 
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。 
除非在下文中特别指出，半导体器件中的各个部分可以由本领域的技术人员公知的材料构成。 
根据本发明的优选实施例，按照图2至14的顺序依次执行制造超薄SOI晶体管的以下步骤。 
参见图2所示，作为初始结构的半导体衬底，可以为常见的半导体衬底，例如IV族半导体(如，硅或锗)或III族-V族化合物半导体(如，砷化镓)。优选地，与图1所示的现有技术相同，该半导体衬底为SOI(绝缘体上硅)晶片，包括底部衬底101、掩埋氧化物层102和顶部半导体层103。更优选地，衬底为超薄SOI衬底，其中，顶部半导体层103的厚度典型地为不大于15nm，优选不大于10nm。 
超薄SOI衬底的制备已经是本领域公知的，例如可以采用包括晶片键合的层转移技术。可选地，如果采用普通的SOI衬底，则可以通过对SOI衬底的顶部半导体层进行减薄来达到所需的厚度。 
按照常规的淀积工艺，如CVD，在超薄SOI衬底的顶部半导体层103上外延生长用于在随后的步骤中形成RSD的外延半导体层104，如图3所示。该外延半导体层104的厚度典型地为10-30nm。 
在下文中，为了简明的目的，除非指明特定的淀积工艺，不再详述所采用的淀积工艺。 
优选地，该外延半导体层104由与超薄SOI衬底的顶部半导体层103由蚀刻速率不同的材料构成，从而在下文所述的蚀刻步骤中产生选择性，例如超薄SOI衬底的顶部半导体层103由硅构成，外延半导体层104由SiGe构成。 
如图4所示，按照常规的淀积工艺，在外延半导体层104顶部形成包括栅极电介质105和栅极导体106的栅极。如下文所述，该栅极用作牺牲栅极(也称为“假栅极”)，而不作为最终晶体管的一部分。 
例如，形成牺牲栅极的工艺可以包括通过淀积依次形成栅极电介质层和栅极导体层，然后对其图案化。 
该图案化可以包括以下步骤：通过包含曝光和显影的光刻工艺，在栅极导体层上形成含有图案的光抗蚀剂掩模；通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离 子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，去除栅极导体层和栅极电介质层的暴露部分，该蚀刻步骤停止在外延半导体层的顶部；通过在溶剂中溶解或灰化去除光抗蚀剂掩模。 
在下文中，为了简明的目的，除非指明特定的图案化工艺，不再详述所采用的图案化工艺。 
然后，在半导体结构的整个表面上，淀积绝缘材料层。对其进行图案化，形成栅极的侧面及顶部的氮化物隔离层107(如Si3N4)。 
氮化物隔离层107位于栅极的顶部的部分提供了在随后的平面化步骤中作为停止层和保护层的帽盖。 
接着，可选地，按照常规的MOS工艺，利用牺牲栅极作为硬掩模，向外延半导体层104的暴露部分注入离子，提供掺杂区域，从而形成了源/漏区121a、121b。 
替代地，也可以在前面所述形成外延半导体层104(参见图3)的步骤中，进行原位掺杂，从而，如后面所述的，最终晶体管中保留的外延半导体层(121a和121b，参见图14)用作源/漏区。 
另外，超薄SOI衬底的顶部半导体层103的位于牺牲栅极下方的部分将形成沟道区120。 
如图5所示，按照常规的淀积工艺，在外延半导体层104的暴露表面和氮化物隔离层107上形成层间绝缘层108(如SiO2)，用于在随后的步骤保护外延半导体层104。 
如图6所示，例如通过化学机械平面化(CMP)，利用氮化物隔离层107的帽盖作为停止层，去除层间绝缘层108的一部分，以获得半导体结构的平整表面。 
如图7所示，例如通过附加的CMP，去除氮化物隔离层107的帽盖，以暴露栅极导体106的表面。同时，氮化物隔离层107位于栅极侧面的部分保留作为栅极的侧墙。 
替代地，可以首先通过反应离子蚀刻(RIE)选择性地去除氮化物隔离层107的帽盖。 
然后，通过干法蚀刻或选择性的湿法蚀刻，去除牺牲栅极，形成暴露外延半导体层104的表面的开口109(参见图8)。 
进一步地，如图9所示，通过选择性的湿法蚀刻，去除外延半导体层104从开口109中暴露的部分，该蚀刻在SOI衬底的顶部半导体层103的顶部停止。 
如图10所示，按照常规的淀积工艺，在半导体结构的整个表面上形成共形的高K电介质层110(如HfO2)。该高K电介质层110覆盖开口109的侧壁和超薄SOI衬底 的顶部半导体层103在开口109的底部暴露的表面。 
接着，按照常规的淀积工艺，在半导体结构的整个表面上形成栅极导体层111(如TiN)。该栅极导体层111填充了开口109，并且覆盖了开口109周围的高K电介质层110的表面(参见图11)。这里，栅极导体层111可以为一层或多层。例如，根据需要，可以先淀积TiN层，然后再淀积TiAlN层。 
例如通过CMP，去除栅极电介质层110和栅极导体层111的位于开口109周围的部分，仅在开口109中留下共形成的栅极电介质层110和填充的栅极导体层111，用作最终晶体管的栅极(也称为“替代栅极”)。 
可选地，如图13所示，例如通过选择性的湿法蚀刻工艺，完全去除层间绝缘层108，以暴露外延半导体层104的表面执行如下所述的硅化步骤。 
接着，按照常规的MOS工艺，对源/漏区121a、121b表面上露出的一部分硅进行金属硅化，并去除未反应的金属，从而形成源/漏接触区122a，122b。 
当然，本领域技术人员可以理解的是，也可以不进行去除层间绝缘层108的操作步骤，在后续的步骤，根据需要直接在层间绝缘层108上形成开口，例如接触孔，然后如上面所述的，在接触孔中进行金属硅化以及去除未反应的金属的操作。 
最终完成的晶体管如图14所示。在超薄SOI衬底的顶部半导体层中形成了沟道区120，而在该顶部半导体层上方的外延半导体层中形成了源/漏区121a、121b。在沟道区120上方形成了栅极电介质110和栅极导体111，栅极导体111与沟道区120和源/漏区121a、121b之间由栅极电介质110隔开。 
由于外延半导体层104位于SOI衬底的顶部半导体层103上方，从而源/漏区121a、121b相对于沟道区120是“抬高的”，即提供了超薄SOI晶体管中的RSD。 
该源/漏区121a、121b延伸到侧墙107下方，并与沟道区120邻接，从而减小了器件的导通电阻和功耗。 
以上描述只是为了示例说明和描述本发明，而非意图穷举和限制本发明。因此，本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改，均在本发明的保护范围之内。 

Claims (1)

1.一种半导体结构，其特征在于，所述半导体结构包括：
半导体衬底；
外延半导体层，所述外延半导体层位于半导体衬底上方的两侧位置；
栅极，所述栅极位于半导体衬底上方的中间位置并且与外延半导体层相邻，所述栅极包括栅极导体层和夹在栅极导体层和半导体衬底之间并在侧面环绕栅极导体的栅极电介质层；以及
侧墙，所述侧墙位于外延半导体层上方以及所述栅极的两侧，
所述半导体衬底为选自IV族半导体衬底、III族-V族半导体衬底、SOI衬底构成的组中的一种，
其中SOI衬底的顶部半导体层与所述外延半导体层由不同蚀刻速率的材料构成，
其中所述SOI衬底的顶部半导体层的厚度不大于15nm。
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