CN103383914B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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CN103383914B
CN103383914B CN201210135261.5A CN201210135261A CN103383914B CN 103383914 B CN103383914 B CN 103383914B CN 201210135261 A CN201210135261 A CN 201210135261A CN 103383914 B CN103383914 B CN 103383914B
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董立军
陈大鹏
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Institute of Microelectronics of CAS
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Abstract

本发明提供一种半导体结构及其制造方法。通过沟道重建使得源/漏区（110）位于侧墙（240）两侧的部分的顶部高于栅堆叠结构和侧墙（240）的底部，并且所述源/漏区（110）在所述栅堆叠结构和侧墙（240）的底部之下横向扩展超过侧墙（240），达到所述栅堆叠结构的正下方，从而获得抬高源漏MOSFET。本发明大量减少工艺步骤，提高效率并降低成本。

Description

半导体结构及其制造方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及其制造方法。
背景技术
抬高源漏金属氧化物半导体场效应晶体管（MOSFET）可以降低源漏串联电阻，从而获得更好的器件特性。一般抬高源漏技术是分别通过选择性外延方法在n管和p管的源漏扩展区域（SDE）上进行高浓度外延。两次选择性外延大大增加了工艺成本，另外由于外延产生的非平面工艺也给下一步光刻制造了难度。
发明内容
针对之前制造抬高源漏MOSFET方法工艺成本和难度大、效率低的缺点，本发明提出了通过沟道重建来获得抬高源漏MOSFET，不需要SDE注入和侧墙沉积，也不要外延，而且是硅平面工艺，大大降低了成本，提高效率。
根据本发明的一个方面，提供一种半导体结构的制造方法，该方法包括以下步骤：
a)提供衬底；
b)在所述衬底上形成伪栅堆叠以及源/漏区；所述伪栅堆叠至少包括伪栅极；所述源/漏区位于所述伪栅堆叠的两侧并延展至所述伪栅堆叠的正下方；
c)形成覆盖所述衬底、源/漏区以及伪栅堆叠的层间介质层；
d)去除所述层间介质层的一部分以暴露所述伪栅堆叠；
e)去除所述伪栅堆叠，以及位于所述伪栅堆叠正下方的衬底的一部分，以形成开口；所述开口的正下方保留部分源/漏区；
f)形成附着于所述开口内侧壁的侧墙；
g)在开口底部形成栅介质层并填充导电材料，形成栅堆叠结构。
本发明的另一方面还提出一种半导体结构，该半导体结构包括：
衬底；
部分嵌入所述衬底中的栅堆叠结构和侧墙；
形成于所述衬底之中的源/漏区；其中源/漏区位于所述侧墙两侧的部分的顶部高于所述栅堆叠结构和侧墙的底部，并且所述源/漏区在所述栅堆叠结构和侧墙的底部之下横向扩展超过侧墙，达到所述栅堆叠结构的正下方。
本发明提出的方法通过沟道重建来获得抬高源漏MOSFET，大量减少工艺步骤，提高生产效率并降低成本。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为根据本发明的半导体结构制造方法的流程图；
图2至图7为根据本发明的一个优选实施例按照图1所示流程制造半导体结构的各个阶段的剖面示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了各种特定的工艺和材料的例子，但是本领域技术人员可以意识到其他工艺的可应用性和/或其他材料的使用。应当注意，在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
下面，将结合图2至图7对图1中形成半导体结构的方法进行具体地描述。
参考图1和图2，在步骤S101中，提供衬底100。
在本实施例中，衬底100包括硅衬底(例如硅晶片)。根据现有技术公知的设计要求(例如P型衬底或者N型衬底)，衬底100可以包括各种掺杂配置。其他实施例中衬底100还可以包括其他基本半导体，例如锗。或者，衬底100可以包括化合物半导体（如Ⅲ-Ⅴ族材料），例如碳化硅、砷化镓、砷化铟。典型地，衬底100可以具有但不限于约几百微米的厚度，例如可以在400um-800um的厚度范围内。
特别地，可以在衬底100中形成隔离区，例如浅沟槽隔离(STI)结构120，以便电隔离相邻的场效应晶体管器件。
参考图1和图2，在步骤S102中，在所述衬底100上形成伪栅堆叠以及源/漏区110；所述伪栅堆叠至少包括伪栅极210；所述源/漏区110位于所述伪栅堆叠的两侧并延展至所述伪栅堆叠的正下方。
在本实施例中，所述伪栅堆叠包括伪栅极210和覆盖层220,如图2a所示，并没有栅介质层，可以在后续的替代栅工艺中除去伪栅堆叠后形成栅介质层。在形成伪栅堆叠时，在所述衬底100上通过沉积例如Poly-Si、Poly-SiGe、非晶硅，和/或，掺杂或未掺杂的氧化硅及氮化硅、氮氧化硅、碳化硅，甚至金属形成伪栅极210，其厚度可以为10-80nm。然后，在伪栅极210上形成覆盖层220，例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成，用以保护伪栅极210的顶部区域，防止伪栅极210的顶部区域在后续形成接触层的工艺中与沉积的金属层发生反应。在其他实施例中，也可以不形成覆盖层220。通过光刻工艺构图，并利用刻蚀工艺刻蚀上述沉积的多层结构后，形成伪栅堆叠。在另一个实施例中，伪栅堆叠也可以包括伪栅介质层201，如图2b所示，只需要在形成伪栅堆叠时，首先在衬底100上形成伪栅介质层201，然后再重复之前所述步骤即可。所述伪栅介质层201的材料可以是氧化硅、氮化硅及其组合形成，在其他实施例中，也可以是高K介质，例如，HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，其厚度可以为2-10nm；
与现有技术的工艺步骤不同，在形成所述伪栅堆叠后，本发明不在所述伪栅堆叠的侧壁上形成侧墙。
源/漏区110位于伪栅堆叠两侧，可以通过向衬底100中注入P型或N型掺杂物或杂质而形成，例如，对于PMOS来说，源/漏区110可以是P型掺杂；对于NMOS来说，源/漏区110可以是N型掺杂。源/漏区110可以由包括光刻、离子注入、扩散和/或其他合适工艺的方法形成，利用通常的半导体加工工艺和步骤，对所述半导体结构进行退火，以激活源/漏区110中的掺杂，退火可以采用包括快速退火、尖峰退火等其他合适的方法形成。在本实施例中，先形成所述伪栅堆叠，然后进行源/漏注入和退火，使得杂质离子横向扩散，得到延展至所述伪栅堆叠正下方的源漏区，如图2a和图2b所示。在另一个实施例中，先通过光刻加注入形成所述源/漏区，然后形成覆盖源/漏区之间的沟道区并覆盖源漏区的一部分的伪栅堆叠，也可以得到延展至所述伪栅堆叠正下方的源漏区。位于伪栅堆叠结构两侧的源漏区深度可以为50-100nm。源/漏区延展至所述伪栅堆叠的正下方的部分的宽度可以为10-20nm。
参考图1和图3，在步骤S103中，形成覆盖所述衬底100、源/漏区110以及伪栅堆叠的层间介质层300。所述层间介质层300可以通过化学气相沉淀(CVD)、等离子体增强CVD、高密度等离子体CVD、旋涂和/或其他合适的工艺等方法形成。所述层间介质层300的材料可以包括氧化硅(USG)、掺杂的氧化硅(如氟硅玻璃、硼硅玻璃、磷硅玻璃、硼磷硅玻璃)、低k电介质材料(如黑钻石、coral等)中的一种或其组合。所述层间介质层300的厚度范围可以是40nm-150nm，如80nm、100nm或120nm，且可以具有多层结构（相邻两层间，材料可以不同）。
参考图1和图4，在步骤S104中，去除所述层间介质层300的一部分以暴露所述伪栅堆叠。
在本实施例中，执行替代栅工艺。参考图4，对层间介质层300和伪栅堆叠进行平坦化处理以暴露伪栅极210的上表面。例如，可以通过化学机械抛光(CMP)的方法去除层间介质层300，并使伪栅极210和层间介质层300的上表面齐平(本文件内，术语“齐平”意指两者之间的高度差在工艺误差允许的范围内)。
参考图1和图5，在步骤S105中，去除所述伪栅堆叠，以及位于所述伪栅堆叠正下方的衬底的一部分，以形成开口230；所述开口230的正下方保留部分源/漏区。
在本实施例中，先去除伪栅极210。在另一个实施例中，若伪栅堆叠包括伪栅介质层201，则先一并去除伪栅极210和伪栅介质层201。可以使用湿法刻蚀和/或干法刻蚀的方式去除伪栅极210或者伪栅极210和伪栅介质层201。湿法刻蚀工艺包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)或者其他合适刻蚀的溶液；干法刻蚀工艺包括六氟化硫(SF6)、溴化氢(HBr)、碘化氢(HI)、氯、氩、氦、甲烷（及氯代甲烷）、乙炔、乙烯等碳的氢化物及其组合，和/或其他合适的材料。然后去除位于所述伪栅堆叠正下方的衬底的一部分，从而形成开口230。可以使用不同的刻蚀工艺和/或不同的刻蚀剂来刻蚀所述伪栅堆叠正下方的部分衬底。例如，在所需刻蚀的部分衬底较薄的情况下，使用湿法刻蚀；湿法刻蚀工艺包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)或者其他合适刻蚀的溶液。
在本发明的实施例中，如图5所示，需要对刻蚀沟道和部分源/漏区的深度进行控制，以使得所述开口230的正下方保留部分源/漏区。保留源/漏区的多少可以视具体的设计需要确定。具体地，在刻蚀伪栅堆叠正下方的部分衬底时，可以减少或者加大刻蚀时间；减少刻蚀时间使得所述保留的部分源/漏区较多较厚，相应的从后续步骤可以看到延展进入栅堆叠底部的源/漏区较多较厚；减少刻蚀时间使得所述保留的部分源/漏区较少较薄；相应的从后续步骤可以看到延展进入栅堆叠底部的源/漏区较少较薄。所述开口230底部低于两侧源漏区顶部的距离可以为10-50nm。
参考图1和图6，在步骤S106中，形成附着于所述开口230内侧壁的侧墙240。
在本实施例中，形成所述开口230后，在所述开口230的内侧壁上形成侧墙240，用于将后续步骤形成的栅极隔开。侧墙240可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙240可以具有多层结构，且对于相邻的两层，其材料可以不同。侧墙240可以通过包括沉积刻蚀工艺形成，侧墙240的宽度不大于所述开口230正下方保留的部分源/漏区的宽度。
参考图1，图6和图7，在步骤S107中，在开口230底部形成栅介质层250并填充导电材料260，形成栅堆叠结构。
在本实施例中，形成侧墙240后，沉积栅介质层250，覆盖开口230的底部，参考图7。所述栅介质层250的材料可以是高K介质，例如，HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，其厚度可以为2nm-10nm，如5nm或8nm。所述栅介质层250可以通过CVD或者原子层沉积(ALD)的工艺来形成。所述栅介质层250还可以具有多层结构，包括具有上述材料的两个以上的层。
形成所述栅介质层250后，进一步进行退火，以提高半导体结构的性能，退火的温度范围为600℃至800℃。退火后，在所述栅介质层250上通过沉积导电材料的方式形成金属栅极260，从而形成完整的栅堆叠，参考图7。对于NMOS，所述导电材料可以是TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合，对于PMOS，所述导电材料可以是MoNx,TiSiN,TiCN,TaAlC,TiAlN,TaN,PtSix,Ni3Si,Pt,Ru,Ir,Mo,HfRu,RuOx；其厚度可以为10nm-80nm，如30nm或50nm。其中，金属栅极260也可以具有多层结构，包括具有上述材料的两个以上的层。
参考图7，图7为完成图1中所示的步骤后最终形成的半导体结构的剖面图。所述半导体结构包括：衬底100；部分嵌入所述衬底100中的栅堆叠结构和侧墙240；形成于所述衬底100之中的源/漏区110；其中源/漏区位于所述侧墙240两侧的部分的顶部高于所述栅堆叠结构和侧墙240的底部（本说明书中所指的栅堆叠结构的底部意指栅堆叠和侧墙与衬底100的交界面），并且所述源/漏区110在所述栅堆叠结构和侧墙240的底部之下横向扩展超过侧墙240，达到所述栅堆叠结构的正下方。
所述栅堆叠结构的底部低于两侧源漏区顶部的距离可以为10-50nm。
位于栅堆叠结构两侧的源漏区深度可以为50-100nm。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (7)

1.一种半导体结构的制造方法，该方法包括以下步骤：
a)提供衬底(100)；
b)在所述衬底(100)上形成伪栅堆叠以及源/漏区(110)；所述伪栅堆叠至少包括伪栅极(210)；所述源/漏区(110)位于所述伪栅堆叠的两侧并延展至所述伪栅堆叠的正下方；
c)形成覆盖所述衬底、源/漏区以及伪栅堆叠的层间介质层(300)；
d)去除所述层间介质层(300)的一部分以暴露所述伪栅堆叠；
e)去除所述伪栅堆叠，以及位于所述伪栅堆叠正下方的衬底的一部分，以形成开口(230)；所述开口(230)的正下方保留部分源/漏区；
f)形成附着于所述开口(230)内侧壁的侧墙(240)；其中，侧墙(240)的宽度不大于所述开口(230)正下方保留的部分源/漏区的宽度；
g)在开口(230)底部形成栅介质层(250)并填充导电材料(260)，形成栅堆叠结构。
2.根据权利要求1所述的方法，在步骤b)中，通过先形成所述伪栅堆叠，后进行源/漏注入和退火的方式得到延展至所述伪栅堆叠正下方的源漏区。
3.根据权利要求1所述的方法，在步骤b)中，通过先形成所述源/漏区，后形成所述伪栅堆叠的方式得到延展至所述伪栅堆叠正下方的源漏区。
4.根据权利要求1所述的方法，在步骤b)中，源/漏区延展至所述伪栅堆叠的正下方的部分的宽度为10-20nm。
5.根据权利要求1所述的方法，在步骤b)中，位于伪栅堆叠结构两侧的源漏区深度为50-100nm。
6.根据权利要求1所述的方法，在步骤e)中，通过控制蚀刻的时间来控制所述保留的部分源/漏区的大小。
7.根据权利要求1所述的方法，在步骤e)中，所述开口(230)底部低于两侧源漏区顶部10-50nm。
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