WO2013163831A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2013163831A1
WO2013163831A1 PCT/CN2012/075738 CN2012075738W WO2013163831A1 WO 2013163831 A1 WO2013163831 A1 WO 2013163831A1 CN 2012075738 W CN2012075738 W CN 2012075738W WO 2013163831 A1 WO2013163831 A1 WO 2013163831A1
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Prior art keywords
source
gate stack
dummy gate
drain regions
substrate
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PCT/CN2012/075738
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English (en)
French (fr)
Inventor
董立军
陈大鹏
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中国科学院微电子研究所
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Priority to US13/878,655 priority Critical patent/US20140191311A1/en
Publication of WO2013163831A1 publication Critical patent/WO2013163831A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention relates to the field of semiconductor fabrication, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • the source-drain technique is to perform high-concentration epitaxy on the source-drain extension region (SDE) of the n-tube and the p-tube by selective epitaxy.
  • SDE source-drain extension region
  • the two selective epitaxy greatly increases the process cost, and the non-planar process due to the extension also makes the next lithography difficult.
  • the present invention proposes to obtain an elevated source-drain MOSFET by channel reconstruction, which does not require SDE implantation and sidewall deposition, and does not require Epitaxy, and silicon planar process, greatly reduces costs and improves efficiency.
  • a method of fabricating a semiconductor structure comprising the steps of:
  • dummy gate stack including at least dummy gates; the source/drain regions being located on both sides of the dummy gate stack and extending to the dummy Directly below the gate stack;
  • Another aspect of the invention also provides a semiconductor structure, the semiconductor structure comprising: a substrate;
  • a source/drain region formed in the substrate wherein a top of a portion of the source/drain regions on both sides of the spacer is higher than a bottom of the gate stack and the sidewall, and the source/drain regions A lateral extent extends beyond the sidewall of the gate stack structure and the sidewalls directly below the gate stack structure.
  • the method proposed by the present invention obtains an elevated source-drain MOSFET through channel reconstruction, which greatly reduces process steps, improves production efficiency, and reduces cost.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIGS. 2 through 7 are schematic cross-sectional views showing various stages of fabricating a semiconductor structure in accordance with the flow of Fig. 1 in accordance with a preferred embodiment of the present invention.
  • step S101 a substrate 100 is provided.
  • the substrate 100 includes a silicon substrate (e.g., a silicon wafer).
  • the substrate 100 can include various doping configurations in accordance with design requirements known in the art (e.g., a P-type substrate or an N-type substrate).
  • the substrate 100 in other embodiments may also include other basic semiconductors such as germanium.
  • the substrate 100 may comprise a compound semiconductor (e.g., a III-V material) such as silicon carbide, gallium arsenide, or indium arsenide.
  • substrate 100 can have, but is not limited to, a thickness of about a few hundred microns, such as can range from 400 um to 800 um.
  • isolation regions such as shallow trench isolation (STI) structures 120, may be formed in substrate 100 to electrically isolate adjacent field effect transistor devices.
  • STI shallow trench isolation
  • step S102 a dummy gate stack and source/drain regions 110 are formed on the substrate 100; the dummy gate stack includes at least a dummy gate 210;
  • The/drain regions 110 are located on both sides of the dummy gate stack and extend just below the dummy gate stack.
  • the dummy gate stack includes a dummy gate 210 and a capping layer 220. As shown in FIG. 2a, there is no gate dielectric layer, which may be formed after removing the dummy gate stack in a subsequent replacement gate process. Gate dielectric layer.
  • a dummy gate stack is formed, for example, Poly-Si, Poly-SiGe, amorphous silicon, and/or doped or undoped silicon oxide and silicon nitride, silicon oxynitride are deposited on the substrate 100. , silicon carbide, or even metal forms a dummy gate 210, which is thick The degree can be 10-80 nm.
  • a capping layer 220 is formed on the dummy gate 210, for example, by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or a combination thereof to protect the top region of the dummy gate 210, preventing the dummy gate 210 The top region reacts with the deposited metal layer in a subsequent process of forming a contact layer.
  • the cover layer 220 may not be formed.
  • a dummy gate stack is formed.
  • the dummy gate stack may also include a dummy gate dielectric layer 201. As shown in FIG.
  • the material of the dummy gate dielectric layer 201 may be formed by silicon oxide, silicon nitride, or a combination thereof. In other embodiments, it may also be a high-k dielectric, for example, Hf0 2 , HffiiO, HfSiON, HfTaO, HfTiO, HfZrO, One or a combination of A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO, which may have a thickness of 2-10 nm;
  • the present invention does not form sidewalls on the sidewalls of the dummy gate stack after forming the dummy gate stack.
  • the source/drain regions 110 are located on both sides of the dummy gate stack and may be formed by implanting P-type or N-type dopants or impurities into the substrate 100.
  • the source/drain regions 110 may be P-type doping; for NMOS, source/drain regions 110 may be N-type doped.
  • Source/drain regions 110 may be formed by methods including photolithography, ion implantation, diffusion, and/or other suitable processes that anneal the semiconductor structures using conventional semiconductor processing techniques and steps to activate source/drain regions 110.
  • the doping, annealing may be formed by other suitable methods including rapid annealing, spike annealing, and the like.
  • the dummy gate stack is formed first, then source/drain implantation and annealing are performed, so that the impurity ions are laterally diffused, and the source and drain regions extending directly below the dummy gate stack are obtained, as shown in FIG. 2a and FIG. 2b. Shown.
  • the source/drain regions are first formed by photolithography plus implantation, and then a dummy gate stack covering a channel region between the source/drain regions and covering a portion of the source and drain regions is formed, and an extension may be obtained.
  • the source and drain regions located on both sides of the dummy gate stack structure may have a depth of 50-100 nm.
  • the portion of the source/drain region extending to the underside of the dummy gate stack may have a width of 10-20 nm.
  • step S103 forming a substrate 100, source/ The drain region 110 and the interlayer dielectric layer 300 of the dummy gate stack.
  • the interlayer dielectric layer 300 may be formed by chemical vapor deposition (CVD), plasma enhanced CVD, high density plasma CVD, spin coating, and/or other suitable processes.
  • the material of the interlayer dielectric layer 300 may include silicon oxide (USG), doped silicon oxide (such as fluorosilicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass), low-k dielectric material (such as black diamond). , or coral, etc., or a combination thereof.
  • the interlayer dielectric layer 300 may have a thickness ranging from 40 nm to 150 nm, such as 80 nm, 100 nm or 120 nm, and may have a multi-layer structure (the materials may be different between adjacent layers).
  • step S104 a portion of the interlayer dielectric layer 300 is removed to expose the dummy gate stack.
  • a replacement gate process is performed.
  • the interlayer dielectric layer 300 and the dummy gate stack are planarized to expose the upper surface of the dummy gate 210.
  • the interlayer dielectric layer 300 may be removed by a chemical mechanical polishing (CMP) method, and the dummy gate 210 and the upper surface of the interlayer dielectric layer 300 may be flush (in this document, the term "flush" means both The height difference between them is within the range allowed by the process error).
  • CMP chemical mechanical polishing
  • step S105 the dummy gate stack is removed, and a portion of the substrate directly under the dummy gate stack is formed to form an opening 230; the opening 230 is directly under the opening 230. Part of the source/drain area.
  • the dummy gate 210 is removed first. In another embodiment, if the dummy gate stack includes the dummy gate dielectric layer 201, the dummy gate 210 and the dummy gate dielectric layer 201 are removed first. The dummy gate 210 or the dummy gate 210 and the dummy gate dielectric layer 201 may be removed using wet etching and/or dry etching.
  • the wet etching process includes tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) or other suitable etching solution; the dry etching process includes sulfur hexafluoride (SF 6 ), hydrogen bromide (HBr) ), hydrides of hydrogen iodide (HI), chlorine, argon, helium, methane (and methyl chloride), acetylene, ethylene, and the like, and combinations thereof, and/or other suitable materials.
  • TMAH tetramethylammonium hydroxide
  • KOH potassium hydroxide
  • the dry etching process includes sulfur hexafluoride (SF 6 ), hydrogen bromide (HBr) ), hydrides of hydrogen iodide (HI), chlorine, argon, helium, methane (and methyl chloride), acetylene, ethylene, and the like, and combinations thereof, and/or other suitable materials.
  • a portion of the substrate directly under the dummy gate stack
  • wet etching is used; the wet etching process includes tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) or other suitable etching solution.
  • TMAH tetramethylammonium hydroxide
  • KOH potassium hydroxide
  • the depth of the /drain region is controlled such that a portion of the source/drain region remains immediately below the opening 230.
  • the number of reserved source/drain regions can be determined by specific design needs. Specifically, when etching a portion of the substrate directly under the dummy gate stack, the etching time may be reduced or increased; reducing the etching time so that the remaining portion of the source/drain regions is thicker, correspondingly from the subsequent steps. It can be seen that the source/drain regions extending into the bottom of the gate stack are thicker; reducing the etching time makes the remaining source/drain regions less thin; correspondingly, the subsequent steps can be seen as ⁇ 'J extended into the gate The source/drain regions at the bottom of the stack are less thin. The distance from the bottom of the opening 230 to the top of the source and drain regions on both sides may be 10-50 nm.
  • step S106 a side wall 240 attached to the inner side wall of the opening 230 is formed.
  • a sidewall 240 is formed on the inner wall of the opening 230 for separating the gates formed in the subsequent steps.
  • Sidewall 240 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 240 may have a multi-layered structure, and the materials may be different for the adjacent two layers.
  • the sidewall spacer 240 may be formed by a deposition etching process, and the width of the sidewall spacer 240 is not greater than the width of a portion of the source/drain regions remaining directly under the opening 230.
  • a gate dielectric layer 250 is formed at the bottom of the opening 230 and filled with a conductive material 260 to form a gate stack structure.
  • the gate dielectric layer 250 is deposited to cover the bottom of the opening 230, with reference to FIG.
  • the material of the gate dielectric layer 250 may be a high-k dielectric, such as one of Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO or In combination, the thickness may be from 2 nm to 10 nm, such as 5 nm or 8 nm.
  • the gate dielectric layer 250 may be formed by a CVD or atomic layer deposition (ALD) process.
  • the gate dielectric layer 250 may also have a multilayer structure including two or more layers having the above materials.
  • annealing is further performed to improve the performance of the semiconductor structure, and the annealing temperature ranges from 600 ° C to 800 ° C.
  • the gate A metal gate 260 is formed on the layer 250 by depositing a conductive material to form a complete gate stack, see FIG.
  • the conductive material may be one or a combination of TaC TiN TaTbN TaErN TaYbN TaSiN HfSiN MoSiN RuTa x NiTa x
  • the conductive material may be MoN x , TiSiN, TiCN, TaAlC, TiAIN, TaN , PtSi x , Ni 3 Si, Pt, Ru, Ir, Mo, HfRu, RuO x ; may have a thickness of 10 nm to 80 nm, such as 30 nm or 50 nm.
  • the metal gate 260 may also have a multilayer structure including two or more layers having the above materials.
  • Figure 7 is a cross-sectional view of the semiconductor structure ultimately formed after the steps shown in Figure 1 are completed.
  • the semiconductor structure includes: a substrate 100; a gate stack structure partially embedded in the substrate 100; and sidewall spacers 240; source/drain regions 110 formed in the substrate 100; wherein the source/drain regions are located
  • the tops of the portions on both sides of the side wall 240 are higher than the bottom of the gate stack structure and the side wall 240 (the bottom of the gate stack structure referred to in this specification means the interface between the gate stack and the side wall and the substrate 100:
  • the source/drain regions 110 extend laterally beyond the sidewalls 240 below the bottom of the gate stack structure and sidewall spacers 240, directly below the gate stack structure.
  • the bottom of the gate stack structure may be 10-50 below the top of the source and drain regions on both sides.
  • the source and drain regions on both sides of the gate stack structure may have a depth of 50-100 nm.

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Abstract

本发明提供一种半导体结构及其制造方法。通过沟道重建使得源/漏区（110）位于侧墙（240）两侧的部分的顶部高于栅堆叠结构和侧墙（240）的底部，并且所述源/漏区（110）在所述栅堆叠结构和侧墙（240）的底部之下横向扩展超过侧墙（240），达到所述栅堆叠结构的正下方，从而获得抬高源漏MOSFET。本发明大量减少工艺步骤，提高效率并降低成本。

Description

半导体结构及其制造方法
[0001】本申请要求了 2012月 5月 2日提交的、 申请号为 201210135261.5、 发明 名称为 "半导体结构及其制造方法" 的中国专利申请的优先权， 其全部内容 通过引用结合在本申请中。 技术领域
[0002】本发明涉及半导体制造领域， 尤其涉及一种半导体结构及其制 造方法。 背景技术
[0003】抬高源漏金属氧化物半导体场效应晶体管（MOSFET )可以降 低源漏串联电阻， 从而获得更好的器件特性。 一般抬高源漏技术是 分别通过选择性外延方法在 n管和 p管的源漏扩展区域（ SDE )上进 行高浓度外延。 两次选择性外延大大增加了工艺成本， 另外由于外 延产生的非平面工艺也给下一步光刻制造了难度。 发明内容
[0004】针对之前制造抬高源漏 MOSFET方法工艺成本和难度大、 效 率低的缺点， 本发明提出了通过沟道重建来获得抬高源漏 MOSFET， 不需要 SDE注入和侧墙沉积， 也不要外延， 而且是硅平面工艺， 大 大降低了成本， 提高效率。
[0005】根据本发明的一个方面， 提供一种半导体结构的制造方法， 该 方法包括以下步骤：
a)提供衬底；
b)在所述衬底上形成伪栅堆叠以及源 /漏区；所述伪栅堆叠至少包括 伪栅极； 所述源 /漏区位于所述伪栅堆叠的两侧并延展至所述伪栅堆叠 的正下方；
c)形成覆盖所述衬底、 源 /漏区以及伪栅堆叠的层间介质层； d)去除所述层间介质层的一部分以暴露所述伪栅堆叠； e)去除所述伪栅堆叠， 以及位于所述伪栅堆叠正下方的衬底的一部 分， 以形成开口； 所述开口的正下方保留部分源 /漏区；
f)形成附着于所述开口内侧壁的侧墙；
g)在开口底部形成栅介质层并填充导电材料， 形成栅堆叠结构。
[0006]本发明的另一方面还提出一种半导体结构， 该半导体结构包括： 衬底；
部分嵌入所述衬底中的栅堆叠结构和侧墙；
形成于所述衬底之中的源 /漏区； 其中源 /漏区位于所述侧墙两侧的 部分的顶部高于所述栅堆叠结构和侧墙的底部， 并且所述源 /漏区在所 述栅堆叠结构和侧墙的底部之下横向扩展超过侧墙，达到所述栅堆叠结 构的正下方。
[0007】本发明提出的方法通过沟道重建来获得抬高源漏 MOSFET，大量 减少工艺步骤， 提高生产效率并降低成本。 附图说明
[0008]通过阅读参照以下附图所作的对非限制性实施例所作的详细描 述， 本发明的其它特征、 目的和优点将会变得更明显：
[0009】图 1为根据本发明的半导体结构制造方法的流程图；
[0010】图 2至图 7为才艮据本发明的一个优选实施例按照图 1所示流程 制造半导体结构的各个阶段的剖面示意图。
[0011】附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0012】下面详细描述本发明的实施例， 所述实施例的示例在附图中示 出。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发 明， 而不能解释为对本发明的限制。
[ 001 3] 下文的公开提供了许多不同的实施例或例子用来实现本发 明的不同结构。 为了简化本发明的公开， 下文中对特定例子的部件 和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本 发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这 种重复是为了简化和清楚的目的， 其本身不指示所讨论各种实施例 和 /或设置之间的关系。 此外， 本发明提供了各种特定的工艺和材料 的例子， 但是本领域技术人员可以意识到其他工艺的可应用性和 /或 其他材料的使用。 应当注意， 在附图中所图示的部件不一定按比例 绘制。 本发明省略了对公知组件和处理技术及工艺的描述以避免不 必要地限制本发明。
[0014】下面，将结合图 2至图 7对图 1中形成半导体结构的方法进行 具体地描述。
[0015】参考图 1和图 2， 在步骤 S101中， 提供衬底 100。
[0016】在本实施例中， 衬底 100包括硅衬底 (例如硅晶片）。 根据现有 技术公知的设计要求 (例如 P型衬底或者 N型衬底）， 衬底 100可以 包括各种掺杂配置。 其他实施例中衬底 100 还可以包括其他基本半 导体， 例如锗。 或者， 衬底 100可以包括化合物半导体（如 III-V族 材料）， 例如碳化硅、 砷化镓、 砷化铟。 典型地， 衬底 100可以具有 但不限于约几百微米的厚度， 例如可以在 400um-800um的厚度范围 内。
[0017】特别地， 可以在衬底 100中形成隔离区， 例如浅沟槽隔离（STI) 结构 120， 以便电隔离相邻的场效应晶体管器件。
[0018】参考图 1和图 2， 在步骤 S102中， 在所述衬底 100上形成伪 栅堆叠以及源 /漏区 110; 所述伪栅堆叠至少包括伪栅极 210; 所述源
/漏区 110 位于所述伪栅堆叠的两侧并延展至所述伪栅堆叠的正下 方。
[0019】在本实施例中， 所述伪栅堆叠包括伪栅极 210 和覆盖层 220, 如图 2a所示， 并没有栅介质层， 可以在后续的替代栅工艺中除去伪 栅堆叠后形成栅介质层。 在形成伪栅堆叠时， 在所述衬底 100 上通 过沉积例如 Poly-Si、 Poly-SiGe, 非晶硅， 和 /或， 掺杂或未掺杂的氧 化硅及氮化硅、 氮氧化硅、 碳化硅， 甚至金属形成伪栅极 210， 其厚 度可以为 10-80nm。 然后， 在伪栅极 210上形成覆盖层 220， 例如通 过沉积氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合形成， 用以保 护伪栅极 210的顶部区域， 防止伪栅极 210的顶部区域在后续形成 接触层的工艺中与沉积的金属层发生反应。 在其他实施例中， 也可 以不形成覆盖层 220。 通过光刻工艺构图， 并利用刻蚀工艺刻蚀上述 沉积的多层结构后， 形成伪栅堆叠。 在另一个实施例中， 伪栅堆叠 也可以包括伪栅介质层 201， 如图 2b所示， 只需要在形成伪栅堆叠 时， 首先在衬底 100上形成伪栅介质层 201， 然后再重复之前所述步 骤即可。 所述伪栅介质层 201 的材料可以是氧化硅、 氮化硅及其组 合形成， 在其他实施例中， 也可以是高 K介质， 例如， Hf02、 HffiiO、 HfSiON、 HfTaO, HfTiO, HfZrO、 A1203、 La203、 Zr02、 LaAlO 中 的一种或其组合， 其厚度可以为 2-10nm;
[0020】与现有技术的工艺步骤不同， 在形成所述伪栅堆叠后， 本发明 不在所述伪栅堆叠的侧壁上形成侧墙。
[0021】源 /漏区 110位于伪栅堆叠两侧，可以通过向衬底 100中注入 P 型或 N型掺杂物或杂质而形成，例如，对于 PMOS来说，源 /漏区 110 可以是 P型掺杂； 对于 NMOS来说， 源 /漏区 110可以是 N型掺杂。 源 /漏区 110可以由包括光刻、 离子注入、 扩散和 /或其他合适工艺的 方法形成， 利用通常的半导体加工工艺和步骤， 对所述半导体结构 进行退火， 以激活源 /漏区 110中的掺杂， 退火可以采用包括快速退 火、 尖峰退火等其他合适的方法形成。 在本实施例中， 先形成所述 伪栅堆叠， 然后进行源 /漏注入和退火， 使得杂质离子横向扩散， 得 到延展至所述伪栅堆叠正下方的源漏区， 如图 2a和图 2b所示。 在 另一个实施例中， 先通过光刻加注入形成所述源 /漏区， 然后形成覆 盖源 /漏区之间的沟道区并覆盖源漏区的一部分的伪栅堆叠， 也可以 得到延展至所述伪栅堆叠正下方的源漏区。 位于伪栅堆叠结构两侧 的源漏区深度可以为 50-100nm。 源 /漏区延展至所述伪栅堆叠的正下 方的部分的宽度可以为 10-20nm。
[0022】参考图 1和图 3， 在步骤 S103中， 形成覆盖所述衬底 100、 源 / 漏区 110以及伪栅堆叠的层间介质层 300。 所述层间介质层 300可以 通过化学气相沉淀 (CVD)、 等离子体增强 CVD、 高密度等离子体 CVD、 旋涂和 /或其他合适的工艺等方法形成。 所述层间介质层 300 的材料可以包括氧化硅 (USG)、 掺杂的氧化硅 (如氟硅玻璃、 硼硅玻 璃、 磷硅玻璃、 硼磷硅玻璃）、 低 k电介质材料 (如黑钻石、 coral等) 中的一种或其组合。 所述层间介质层 300 的厚度范围可以是 40nm-150nm, 如 80nm、 lOOnm或 120nm， 且可以具有多层结构（相 邻两层间， 材料可以不同）。
[0023】参考图 1和图 4， 在步骤 S104 中， 去除所述层间介质层 300 的一部分以暴露所述伪栅堆叠。
[0024】在本实施例中，执行替代栅工艺。参考图 4，对层间介质层 300 和伪栅堆叠进行平坦化处理以暴露伪栅极 210 的上表面。 例如， 可 以通过化学机械抛光 (CMP)的方法去除层间介质层 300， 并使伪栅极 210和层间介质层 300的上表面齐平 (本文件内， 术语 "齐平" 意指 两者之间的高度差在工艺误差允许的范围内）。
[0025】参考图 1和图 5， 在步骤 S105 中， 去除所述伪栅堆叠， 以及 位于所述伪栅堆叠正下方的衬底的一部分， 以形成开口 230; 所述开 口 230的正下方保留部分源 /漏区。
[0026】在本实施例中， 先去除伪栅极 210。 在另一个实施例中， 若伪 栅堆叠包括伪栅介质层 201，则先一并去除伪栅极 210和伪栅介质层 201。可以使用湿法刻蚀和 /或干法刻蚀的方式去除伪栅极 210或者伪 栅极 210 和伪栅介质层 201。 湿法刻蚀工艺包括四甲基氢氧化铵 (TMAH)、 氢氧化钾 (KOH)或者其他合适刻蚀的溶液； 干法刻蚀工艺 包括六氟化硫 (SF6)、 溴化氢 (HBr)、 碘化氢 (HI)、 氯、 氩、 氦、 甲烷 (及氯代甲烷）、 乙炔、 乙烯等碳的氢化物及其组合， 和 /或其他合适 的材料。 然后去除位于所述伪栅堆叠正下方的衬底的一部分， 从而 形成开口 230。 可以使用不同的刻蚀工艺和 /或不同的刻蚀剂来刻蚀 所述伪栅堆叠正下方的部分衬底。 例如， 在所需刻蚀的部分衬底较 薄的情况下， 使用湿法刻蚀； 湿法刻蚀工艺包括四甲基氢氧化铵 (TMAH)、 氢氧化钾 (KOH)或者其他合适刻蚀的溶液。
[0027】在本发明的实施例中， 如图 5所示， 需要对刻蚀沟道和部分源
/漏区的深度进行控制， 以使得所述开口 230的正下方保留部分源 /漏 区。 保留源 /漏区的多少可以视具体的设计需要确定。 具体地， 在刻 蚀伪栅堆叠正下方的部分衬底时， 可以减少或者加大刻蚀时间； 减 少刻蚀时间使得所述保留的部分源 /漏区较多较厚， 相应的从后续步 骤可以看到延展进入栅堆叠底部的源 /漏区较多较厚； 减少刻蚀时间 使得所述保留的部分源 /漏区较少较薄； 相应的从后续步骤可以看 ^ 'J 延展进入栅堆叠底部的源 /漏区较少较薄。 所述开口 230底部低于两 侧源漏区顶部的距离可以为 10-50nm。
[0028】参考图 1和图 6， 在步骤 S106 中， 形成附着于所述开口 230 内侧壁的侧墙 240。
[0029】在本实施例中， 形成所述开口 230后， 在所述开口 230的内侧 壁上形成侧墙 240， 用于将后续步骤形成的栅极隔开。 侧墙 240可以 由氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的 材料形成。 侧墙 240 可以具有多层结构， 且对于相邻的两层， 其材 料可以不同。 侧墙 240 可以通过包括沉积刻蚀工艺形成， 侧墙 240 的宽度不大于所述开口 230正下方保留的部分源 /漏区的宽度。
[0030】参考图 1， 图 6和图 7， 在步骤 S107中， 在开口 230底部形成 栅介质层 250并填充导电材料 260， 形成栅堆叠结构。
[0031】在本实施例中， 形成侧墙 240后， 沉积栅介质层 250， 覆盖开 口 230的底部， 参考图 7。 所述栅介质层 250的材料可以是高 K介 质， 例 口， Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO、 A1203、 La203、 Zr02、 LaAlO中的一种或其组合， 其厚度可以为 2nm-10nm， 如 5nm或 8nm。 所述栅介质层 250可以通过 CVD或者原子层沉积 (ALD)的工艺来形成。 所述栅介质层 250还可以具有多层结构， 包括 具有上述材料的两个以上的层。
[0032】形成所述栅介质层 250后， 进一步进行退火， 以提高半导体结 构的性能， 退火的温度范围为 600°C至 800°C。 退火后， 在所述栅介 质层 250上通过沉积导电材料的方式形成金属栅极 260，从而形成完 整的栅堆叠，参考图 7。对于 NMOS，所述导电材料可以是 TaC TiN TaTbN TaErN TaYbN TaSiN HfSiN MoSiN RuTax NiTax中的 一种或其组合，对于 PMOS，所述导电材料可以是 MoNx, TiSiN, TiCN, TaAlC, TiAIN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuOx;其厚度可 以为 10nm-80nm， 如 30nm或 50nm。 其中， 金属栅极 260也可以具 有多层结构， 包括具有上述材料的两个以上的层。
[0033】参考图 7， 图 7为完成图 1中所示的步骤后最终形成的半导体 结构的剖面图。 所述半导体结构包括： 衬底 100; 部分嵌入所述衬底 100中的栅堆叠结构和侧墙 240;形成于所述衬底 100之中的源 /漏区 110;其中源 /漏区位于所述侧墙 240两侧的部分的顶部高于所述栅堆 叠结构和侧墙 240 的底部 （本说明书中所指的栅堆叠结构的底部意 指栅堆叠和侧墙与衬底 100的交界面：)，并且所述源 /漏区 110在所述 栅堆叠结构和侧墙 240的底部之下横向扩展超过侧墙 240，达到所述 栅堆叠结构的正下方。
[0034】所述栅堆叠结构的底部低于两侧源漏区顶部的距离可以为 10-50
[0035】位于栅堆叠结构两侧的源漏区深度可以为 50-100nm
[0036】虽然关于示例实施例及其优点已经详细说明，应当理解在不脱 离本发明的精神和所附权利要求限定的保护范围的情况下， 可以对 这些实施例进行各种变化、 替换和修改。 对于其他例子， 本领域的 普通技术人员应当容易理解在保持本发明保护范围内的同时， 工艺 步骤的次序可以变化。
[0037】此外，本发明的应用范围不局限于说明书中描述的特定实施例 的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的 公开内容， 作为本领域的普通技术人员将容易地理解， 对于目前已 存在或者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明描述的对应实施例大体相同的 功能或者获得大体相同的结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、 机构、 制造、 物质组 成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种半导体结构的制造方法， 该方法包括以下步骤：
a) 提供衬底（ 100 ) ；
b) 在所述衬底 ( 100 )上形成伪栅堆叠以及源 /漏区（ 110 )； 所述 伪栅堆叠至少包括伪栅极 ( 210 ) ； 所述源 /漏区 （110 )位于 所述伪栅堆叠的两侧并延展至所述伪栅堆叠的正下方； c) 形成覆盖所述衬底、源 /漏区以及伪栅堆叠的层间介质层（ 300 ); d) 去除所述层间介质层（300 ) 的一部分以暴露所述伪栅堆叠； e) 去除所述伪栅堆叠， 以及位于所述伪栅堆叠正下方的衬底的一 部分， 以形成开口 （230 )； 所述开口 （230 )的正下方保留部 分源 /漏区；
f) 形成附着于所述开口 （230 ) 内侧壁的侧墙（240 ) ；
g) 在开口（ 230 )底部形成栅介质层（ 250 )并填充导电材料（ 260 )， 形成栅堆叠结构。
2、 根据权利要求 1所述的方法， 在步骤 b)中， 通过先形成所述伪 栅堆叠，后进行源 /漏注入和退火的方式得到延展至所述伪栅堆叠正下方 的源漏区。
3、 根据权利要求 1所述的方法， 在步骤 b)中， 通过先形成所述源 /漏区，后形成所述伪栅堆叠的方式得到延展至所述伪栅堆叠正下方的源 漏区。
4、 根据权利要求 1 所述的方法， 在步骤 b)中， 源 /漏区延展至所 述伪栅堆叠的正下方的部分的宽度为 10-20nm。
5、 根据权利要求 1所述的方法， 在步骤 b)中， 位于伪栅堆叠结构 两侧的源漏区深度为 50-100nm。
6、 根据权利要求 1所述的方法， 在步骤 e)中， 通过控制蚀刻的时 间来控制所述保留的部分源 /漏区的大小。
7、 根据权利要求 1所述的方法， 在步骤 e)中， 所述开口 （230 ) 底部低于两侧源漏区顶部 10-50nm。
8、 根据权利要求 1所述的方法， 在步骤 f)中， 侧墙（240) 的宽 度不大于所述开口 （230)正下方保留的部分源 /漏区的宽度。
9、 一种半导体结构， 包括：
衬底（ 100 ) ；
部分嵌入所述衬底（100) 中的栅堆叠结构和侧墙（240) ； 形成于所述衬底（100)之中的源 /漏区 （110) ； 其中源 /漏区位于 所述侧墙（240) 两侧的部分的顶部高于所述栅堆叠结构和侧墙（240) 的底部， 并且所述源 /漏区 （110)在所述栅堆叠结构和侧墙（240)的底 部之下横向扩展超过侧墙（240) ， 达到所述栅堆叠结构的正下方。
10、 根据权利要求 9所述的结构， 其中， 所述栅堆叠结构的底部低 于两侧源漏区顶部 10-50nm。
11、 根据权利要求 9所述的结构， 其中， 位于栅堆叠结构两侧的源 漏区深度为 50-100nm。
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