WO2015018130A1 - 一种mosfet结构及其制造方法 - Google Patents

一种mosfet结构及其制造方法 Download PDF

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Publication number
WO2015018130A1
WO2015018130A1 PCT/CN2013/085556 CN2013085556W WO2015018130A1 WO 2015018130 A1 WO2015018130 A1 WO 2015018130A1 CN 2013085556 W CN2013085556 W CN 2013085556W WO 2015018130 A1 WO2015018130 A1 WO 2015018130A1
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doped well
substrate
gate
manufacturing
vacancy
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PCT/CN2013/085556
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French (fr)
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尹海洲
张珂珂
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中国科学院微电子研究所
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/107—Substrate region of field-effect devices
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates to a MOSFET structure and a method of fabricating the same. More specifically, it relates to a MOSFET structure for forming a steep inverted doped well in a semiconductor substrate under a gate stack and a method of fabricating the same.
  • the present invention provides a MOSFET structure and a method of fabricating the same, the channel region below which is close to the source end portion.
  • the depth of the doped well from the channel surface is 1 to 3 times the depth of the inverted doped well near the drain end portion from the channel surface, and the length of the deep doped portion is 1 to 3 of the length of the shallow doped portion. Times.
  • the present invention effectively suppresses the adverse effects of the short channel effect and improves the device performance.
  • the present invention provides an asymmetric MOSFET structure and a fabrication method thereof, which effectively suppresses the short channel effect of the device and improves device performance.
  • the manufacturing method provided by the present invention includes the following steps:
  • the first doped well is formed by ion implantation of a substrate under the dummy gate vacancy, the direction of the ion implantation being perpendicular to the substrate.
  • the first doped well is located in a substrate at 35 to 45 nm below the dummy gate vacancy.
  • the second doped well is formed by: forming a mask in a dummy gate vacancy near the source end, and performing ion implantation on the substrate not covered by the mask under the dummy gate vacancy, The direction of ion implantation is perpendicular to the bottom of the crucible.
  • the second doped well is formed by: implanting a substrate under the dummy gate vacancy with an incident angle ⁇ by using a sidewall spacer as a mask, wherein the ion implantation region The part below the side wall does not exceed the boundary of the side wall.
  • the height of the sidewall spacer is not less than L/tana, where L is a length difference between the dummy first doped well and the second doped well.
  • the second doped well is located in a substrate 15 to 25 nm below the dummy gate vacancy near the drain region, the length of the second doped well being 1/4 of the length of the first doped well ⁇ 1/2.
  • the present invention provides a MOSFET structure including: a substrate, a sidewall, a source a region and a drain region, a gate dielectric layer, a work function adjusting layer, a gate metal layer, a first doped well, and a second doped well, wherein the doping of the first doped well and the second doped well
  • the type is the same as the substrate.
  • the first doped well is located in a substrate at 35 to 45 nm below the gate, and the second doped well is located in a substrate 15 to 25 nm below the gate of the drain region.
  • the height of the sidewall spacer is not less than L/tana, where L is a length difference between the dummy first doped well and the second doped well.
  • the depth of the inverted doped well near the source end portion below the channel region is from the surface of the channel opposite the doped well of the drain end portion.
  • the depth is 1 to 3 times, and the length of the deep doped portion is 1 to 3 times the length of the shallow doped portion. That is to say, near the source end, the influence of the channel width on the mobility is mainly considered, and the doping depth is large; and in the vicinity of the drain end, since the channel width has little effect on the carrier mobility, In order to reduce the influence of DIBL, the doping depth is small.
  • the present invention effectively suppresses the adverse effects of the short channel effect and improves the device performance.
  • 1 to 7 are schematic cross-sectional views showing the structure of a semiconductor body at various stages of the manufacturing method according to the present invention.
  • the present invention provides an asymmetric MOSFET structure, including: a substrate 100, a sidewall spacer 104, source and drain regions, a gate dielectric layer 201, a work function adjustment layer 202, a gate metal layer 203, The first doped well 200 and the second doped well 300, wherein the first doped well 200 and the second doped well 300 have the same doping type as the substrate.
  • the gate structure includes a gate dielectric layer 201, a work function adjustment layer 202, a gate metal layer 203, And a pair of insulating dielectric spacers 104 on either side of the gate stack.
  • the gate dielectric layer 201 is preferably made of silicon oxynitride or silicon oxide or a high-k material. Its equivalent oxidation thickness is from 0.5 nm to 5 nm.
  • the gate metal layer 203 may be only a metal gate or a metal/polysilicon composite gate, wherein the polysilicon has a silicide on its upper surface.
  • the semiconductor channel region is located on the surface of the substrate 100, and the material thereof is a single crystal silicon or a single crystal germanium alloy film having a thickness of 5 to 20 nm. This region is extremely lightly doped or even undoped. In the case of doping, the doping type is opposite to that of the source and drain regions.
  • the source and drain regions are respectively located on both sides of the gate stack, within the substrate 100.
  • the source region is symmetrical with the drain region, and its doping type is opposite to that of the substrate.
  • the first doped well 200 is located in a substrate at 35 to 45 nm below the gate, and the second doped well 300 is located in a substrate 15 to 25 nm below the gate of the drain region.
  • the length of the second doped well 300 is 1/4 to 1/2 of the length of the first doped well 200.
  • the height of the side wall 104 is not less than L/tana, where L is the difference in length between the dummy first doped well 200 and the second doped well 300.
  • a substrate is first provided and a gate dielectric layer 103 is formed on the substrate.
  • the gate dielectric layer 103 may be a thermal oxide layer, including silicon oxide or silicon oxynitride; or a high-k dielectric such as HfA10N, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, A1 2 0 3
  • the gate dielectric layer 301 may have a thickness of 1 nm to 10 nm, for example, 3 nm, 5 nm or 8 nm, of one or a combination of La 2 O 3 , Zr0 2 , and LaAlO.
  • the gate dielectric layer 103 may be formed by a process such as thermal oxidation, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
  • a dummy gate structure 102 is formed on the gate dielectric layer.
  • the dummy gate structure 102 may be a single layer or a plurality of layers.
  • the dummy gate structure 102 may comprise a polymer material, amorphous silicon, polysilicon or TiN, and may have a thickness of 10 nm to 200 nm.
  • the dummy gate structure includes polysilicon and dioxide.
  • a chemical vapor deposition method is used to fill the gate vacancies with polysilicon, and then a silicon dioxide dielectric layer is formed over the polysilicon.
  • the formation method may be Epitaxial growth, oxidation, CVD, and the like.
  • the deposition of various dielectric materials in the embodiments of the present invention may adopt the same or similar methods for forming the gate dielectric layer as described above, and thus will not be described again.
  • the substrate 100 on both sides of the dummy gate structure is shallowly doped to form a lightly doped source and drain region, and Halo implantation may be performed to form a Halo implant region.
  • the shallow doping impurity type is the same as the device type, and the Halo implanted impurity type is opposite to the device type.
  • sidewall spacers 104 are formed on sidewalls of the gate stack for spacing the gates. Specifically, a 40 nm to 80 nm thick sacrificial sidewall dielectric layer of silicon nitride is deposited by LPCVD, and then a silicon nitride spacer 104 having a width of 35 nm to 75 nm is formed on both sides of the gate electrode by a guest technique.
  • the spacers 104 may also be formed of silicon oxide, silicon oxynitride, silicon carbide, combinations thereof, and/or other suitable materials.
  • the side wall 104 may have a multi-layered structure.
  • the spacers 104 may also be formed by a deposition etch process including a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • a silicon dioxide dielectric layer having a thickness of 10 nm to 35 nm is deposited on the semiconductor structure to form an interlayer dielectric layer 105, and the dielectric layer is used as a buffer layer, and the ion implantation source and drain regions are implanted.
  • the dopant is boron or boron or indium or gallium.
  • the dopant is phosphorus or arsenic or antimony.
  • the doping concentration is 5el0 19 cm_ 3 ⁇ lel0 2 ° cm_ 3 .
  • the semiconductor structure after doping is completed as shown in FIG.
  • the dummy gate structure is removed to form dummy gate vacancies, as shown in FIG.
  • the removal of the dummy gate structure can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
  • a first doped well 200 is formed in the substrate below the dummy gate vacancies. Specifically, vertical ion implantation is performed on the semiconductor structure, and a doped region having a certain concentration distribution is formed in a substrate at 35 to 45 nm below the dummy gate vacancy, and the type of the doped region is the same as the substrate, 4, the short channel effect is well suppressed, and the doped well 200 is formed in the substrate, and the doping concentration formed by the ion implantation is 5e 17 cm" 3 ⁇ le 19 cm" 3 .
  • a second doped well 300 is formed in the substrate below the dummy gate vacancy near the drain region, the second doped well being located at a substrate 15-20 nm below the dummy gate vacancy near the drain region
  • the length of the second doped well is 1/4 ⁇ 1/2 of the length of the first doped well.
  • the method of forming the second doped well 300 may be: A mask 106 is formed in the dummy gate vacancies at the source, and the substrate under the dummy gate vacancies that is not covered by the mask is ion-implanted.
  • the mask 106 may be a photoresist. Specifically, the photoresist is filled in the dummy gate vacancy, and the photoresist near the drain end is removed by a process of exposure, development, and de-glue through a mask. The substrate 100 is exposed and the length of the removed photoresist is equal to the length of the desired second doped well.
  • the direction of the ion implantation is perpendicular to the substrate, and by controlling the dose and energy of the ion implantation, the second doped well 300 can be formed under the semiconductor substrate 100 not covered by the photoresist, as shown in FIG. .
  • the mask 106 is then removed to expose the substrate 100.
  • the method for forming the second doped well 300 may further be: using a sidewall spacer as a mask, and performing an incident angle ⁇ ion on the substrate under the dummy gate vacancy Injecting, wherein the portion of the ion implantation region located below the side wall does not exceed the boundary of the sidewall spacer. That is, the farthest distance of the doping ions implanted into the substrate in the direction parallel to the channel does not exceed the boundary between the sidewall spacer 104 and the interlayer dielectric layer, avoiding the second doped well. 300 is connected to the drain region and has some adverse effects on the device.
  • the tilt angle ⁇ of the ion implantation can be determined according to the ion implantation range on the side close to the drain end. It should be noted that in order to ensure that the length of the second doped well 300 is within the range we need, according to the mathematical relationship, the height of the spacer used as a mask here must be not less than L/tana, where L is pseudo first A difference in length between the doped well and the second doped well.
  • the gate dielectric layer 201, the work function adjusting layer 202, and the gate metal layer 203 are sequentially formed in the gate vacancies.
  • the gate metal layer 203 may be only a metal gate or a metal/polysilicon composite gate, wherein the polysilicon has a silicide on its upper surface.
  • a work function metal layer is deposited on the gate dielectric layer 201, and then a metal conductor layer is formed on the work function metal layer.
  • the work function metal layer can be made of materials such as TiN and TaN, and has a thickness ranging from 3 nm to 15 nm.
  • the metal conductor layer may be in a one-layer or multi-layer structure.
  • the material may be one of TaN, TaC, TiN, TaAlN, TiAlN, ⁇ 1 ⁇ , TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof.
  • the thickness may range, for example, from 10 nm to 40 nm, such as 20 nm or 30 nm.

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Abstract

提供一种MOSFET制造方法，包括：a．提供衬底（100）；b．在衬底（100）上形成伪栅堆叠及其侧墙（104）、源/漏区和层间介质层（105）；c．去除伪栅堆叠以形成伪栅空位；d．在伪栅空位下方的衬底（100）中形成第一掺杂阱（200）；e．在靠近漏区的伪栅空位下方的衬底中形成第二掺杂阱（300）；f．对器件进行退火，以激活掺杂；g．在开口中沉积栅极介质层（201）、功函数调节层（202）和栅极金属层（203）。该方法制造的MOSFET能够有效地抑制短沟道效应的不良影响，提高器件性能。

Description

一种 MOSFET结构及其制造方法
[0001]本申请要求了 2013年 8月 6日提交的、 申请号为 201310339819.6、 发明名称为 "一种 MOSFET结构及其制造方法"的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
[0002]本发明涉及一种 MOSFET结构及其制造方法。 更具体而言， 涉及一 种用于在栅堆叠下方的半导体衬底中形成具有陡峭的倒掺杂阱的 MOSFET 结构及其制造方法。
技术背景
[0003]随着半导体行业的发展， 具有更高性能和更强功能的集成电路要求 更大的元件密度， 而且各个部件、 元件之间或各个元件自身的尺寸、 大小 和空间也需要进一步缩小。 相应地， 为了提高 MOSFET(金属氧化物半导 体场效应晶体管 ） 器件的性能， 需要进一步减少 MOSFET 器件的栅长。 然而随着栅长持续减小， 减少到接近源极和漏极的耗尽层的宽度， 例如小 于 40nm 时，将会产生较严重的短通道效应 （short channel effect或筒写为 SCE), 从而不利地降低器件的性能， 给大规模集成电路的生产造成困难。 如何降低短通道效应以及有效地控制短通道效应， 已经成为集成电路大规 模生产中的一个很关键的问题。
[0004]现有方案一般是基于在沟道中形成陡峭的倒掺杂阱以减小栅极下耗 尽层的厚度， 进而减少短通道效应。 然而随着沟道尺寸的进一步减小， 漏 端感应势垒降低效应 ( Drain Induction Barrier Lower ), 载流子迁移率随着 沟道厚度的减小而降低等因素对器件特性的影响越来越严重。
[0005] 因此， 为了平衡沟道宽度对载流子迁移率和 DIBL效应的影响， 优 化器件性能， 本发明提供了一种 MOSFET结构及其制造方法， 其沟道区下 方靠近源端部分的倒掺杂阱距离沟道表面的深度是靠近漏端部分的倒掺杂 阱距离沟道表面的深度的 1至 3倍， 且其深掺杂部分的长度是浅掺杂部分 的长度的 1至 3倍。 也就是说， 在靠近源端的地方， 主要考虑沟道宽度对 迁移率的影响， 掺杂深度较大； 而在靠近漏端的地方， 由于沟道宽度对载 流子迁移率的影响不大， 因此为了降低 DIBL 的影响， 掺杂深度较小。 与 现有技术相比， 本发明有效地抑制了短沟道效应的不良影响， 提高了器件 性能。
发明内容
[0006]本发明提供了一种非对称 MOSFET结构及其制作方法，有效抑制了 器件的短沟道效应， 提高了器件性能。 具体地， 本发明提供的制造方法包 括以下步骤：
a.提供衬底；
b.在衬底上形成伪栅堆叠及其侧墙、 源 /漏区和层间介质层；
c.去除所述伪栅堆叠以形成伪栅空位；
d.在伪栅空位下方的衬底中形成第一掺杂阱；
e.在靠近漏区的伪栅空位下方的衬底中形成第二掺杂阱；
f.对所述器件进行退火， 以激活掺杂；
g.在所述开口中沉积栅极介质层、 功函数调节层和栅极金属层。
[0007】其中， 所述第一掺杂阱的形成方式是： 对所述伪栅空位下方的衬底 进行离子注入， 所述离子注入的方向与衬底垂直。
[0008]其中， 所述第一掺杂阱位于伪栅空位下方 35~45nm处的衬底中。
[0009】其中， 所述第二掺杂阱的形成方法是： 在靠近源端的伪栅空位中形 成掩膜， 对所述伪栅空位下方未被掩膜覆盖的衬底进行离子注入， 所述离 子注入的方向与 †底垂直。
[0010】其中， 所述第二掺杂阱的形成方法是： 以侧墙为掩膜， 对所述伪栅 空位下方的衬底进行入射角为 α的离子注入， 其中， 所述离子注入区域位 于侧墙下方的部分不超过侧墙的边界。
[0011】其中， 所述侧墙的高度不小于 L/tana, 其中 L为伪第一掺杂阱与第 二掺杂阱之间的长度差。
[0012]其中， 所述第二掺杂阱位于靠近漏区的伪栅空位下方 15~25nm处的 衬底中， 所述第二掺杂阱的长度为第一掺杂阱长度的 1/4~1/2。
[0013】其中， 所述离子注入的类型与衬底相同， 浓度 5el7cm-3~lel9cm-3。
[0014】相应的， 本发明提供了一种 MOSFET结构， 包括： 衬底、 侧墙、 源 区和漏区、 栅极介质层、 功函数调节层、 栅极金属层、 第一掺杂阱和第二 掺杂阱， 其中， 所述第一掺杂阱和第二掺杂阱的掺杂类型与衬底相同。
[0015】其中， 所述第一掺杂阱位于栅极下方 35~45nm处的衬底中， 所述第 二掺杂阱位于靠近漏区的栅极下方 15~25nm处的衬底中。
[0016】其中， 所述侧墙的高度不小于 L/tana, 其中 L为伪第一掺杂阱与第 二掺杂阱之间的长度差。
[0017]其中， 所述第二掺杂阱的长度为第一掺杂阱长度的 1/4~1/2。
[0018]根据本发明提供的 MOSFET结构及其制造方法， 其沟道区下方靠近 源端部分的倒掺杂阱距离沟道表面的深度是靠近漏端部分的倒掺杂阱距离 沟道表面的深度的 1至 3倍， 且其深掺杂部分的长度是浅掺杂部分的长度 的 1至 3倍。 也就是说， 在靠近源端的地方， 主要考虑沟道宽度对迁移率 的影响， 掺杂深度较大； 而在靠近漏端的地方， 由于沟道宽度对载流子迁 移率的影响不大， 因此为了降低 DIBL 的影响， 掺杂深度较小。 与现有技 术相比， 本发明有效地抑制了短沟道效应的不良影响， 提高了器件性能。
附图说明
[0019] 图 1至图 7示意性地示出了形成根据本发明的制造方法各阶段半导 体结构的剖面图。
具体实施方式
[0020】为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对 本发明的实施例作详细描述。
[0021]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似 功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本 发明， 而不能解释为对本发明的限制。
[0022】本发明提供了一种非对称 MOSFET结构， 包括： 包括： 衬底 100、 侧墙 104、 源区和漏区、 栅极介质层 201、 功函数调节层 202、 栅极金属层 203、 第一掺杂阱 200和第二掺杂阱 300, 其中， 所述第一掺杂阱 200和第 二掺杂阱 300的掺杂类型与衬底相同。
[0023】栅结构包括栅极介质层 201、 功函数调节层 202、 栅极金属层 203、 和一对位于该栅极叠层两侧的绝缘介质侧墙 104。栅介质层 201优选材料为 氮氧化硅， 也可为氧化硅或高 K材料。 其等效氧化厚度为 0.5nm~5nm。 栅 极金属层 203可以只为金属栅极， 也可以为金属 /多晶硅复合栅极， 其中多 晶硅上表面上具有硅化物。
[0024]半导体沟道区位于衬底 100的表面，其优选材料为单晶硅或单晶锗合 金薄膜， 其厚度为 5~20nm。 该区域是极轻掺杂甚至未掺杂的。 在掺杂的情 况下， 其掺杂类型与源漏区掺杂相反。
[0025]源区和漏区分别位于栅极叠层两侧，衬底 100内。源区与漏区相对称， 其掺杂类型与衬底相反。
[0026]第一掺杂阱 200位于栅极下方 35~45nm处的衬底中，第二掺杂阱 300 位于靠近漏区的栅极下方 15~25nm处的衬底中。 第二掺杂阱 300的长度为 第一掺杂阱 200长度的 1/4~1/2。
[0027]侧墙 104的高度不小于 L/tana, 其中 L为伪第一掺杂阱 200与第二 掺杂阱 300之间的长度差。
[0028]下面结合附图对本发明的制作方法进行详细说明， 包括以下步骤。 需要说明的是， 本发明各个实施例的附图仅是为了示意的目的， 因此没有 必要按比例绘制。
[0029]首先提供衬底，并在所述衬底上形成栅极介质层 103。所述栅极介质 层 103可以是热氧化层， 包括氧化硅、 氮氧化硅； 也可为高 K介质， 例如 HfA10N、 HfSiAlON, HfTaAlON, HfTiAlON, HfON、 HfSiON、 HfTaON、 HfTiON、 A1203、 La203、 Zr02、 LaAlO中的一种或其组合，栅极介质层 301 的厚度可以为 lnm -10nm, 例如 3nm、 5nm或 8nm。 可以采用热氧化、 化 学气相沉积（CVD )或原子层沉积（ALD )等工艺来形成栅极介质层 103。
[0030]接下来， 在所述栅极介质层上形成伪栅结构 102。 所述伪栅结构 102 可以是单层的， 也可以是多层的。 伪栅结构 102可以包括聚合物材料、 非 晶硅、 多晶硅或 TiN, 厚度可以为 10nm~200nm。 本是实例中， 伪栅结构 包括多晶硅和二氧化， 具体的， 采用化学汽相淀积的方法在栅极空位中填 充多晶硅， 接着在多晶硅上方形成一层二氧化硅介质层， 形成方法可以是 外延生长、 氧化、 CVD等。接着采用常规 CMOS工艺光刻和刻蚀所淀积的 伪栅叠层形成栅电极图形，然后以栅电极图形为掩膜腐蚀掉栅极介质层 103 的棵露部分。 需说明地是， 以下若无特别说明， 本发明实施例中各种介质 材料的淀积均可采用上述所列举的形成栅介质层相同或类似的方法， 故不 再赘述。
[0031】接下来， 对伪栅结构两侧的衬底 100进行浅掺杂， 以形成轻掺杂源 漏区， 还可以进行 Halo注入， 以形成 Halo注入区。 其中浅掺杂的杂质类 型与器件类型一致， Halo注入的杂质类型与器件类型相反。
[0032]可选地， 在栅极堆叠的侧壁上形成侧墙 104, 用于将栅极隔开。 具体 的， 用 LPCVD淀积 40nm~80nm厚的牺牲侧墙介质层氮化硅， 接着用会客 技术再栅电极两侧形成宽度为 35nm~75nm的氮化硅侧墙 104。 侧墙 104还 可以由氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的材料形成。 侧墙 104可以具有多层结构。侧墙 104还可以通过包括沉积刻蚀工艺形成， 其厚度范围可以是 lOnm -lOOnm, 如 30nm、 50nm或 80nm。
[0033]接下来，在所述半导体结构上淀积一层厚度为 10nm~35nm厚的二氧 化硅介质层， 形成层间介质层 105 , 并以该介质层为緩沖层， 离子注入源漏 区。对 P型晶体而言，掺杂剂为硼或弗化硼或铟或镓等。对 N型晶体而言， 掺杂剂为磷或砷或锑等。掺杂浓度为 5el019cm_3~lel02° cm_3。完成掺杂之后 的半导体结构如图 1所示。
[0034】接下来， 去除所述伪栅结构， 形成伪栅空位， 如图 2所示。 去除伪 栅结构可以采用湿刻和 /或干刻除去。在一个实施例中，采用等离子体刻蚀。
[0035]接下来，如图 3所示，在伪栅空位下方的衬底中形成第一掺杂阱 200。 具体的，对所述半导体结构进行垂直的离子注入，在伪栅空位下方 35~45nm 处的衬底中形成具有一定浓度分布的掺杂区域， 所述掺杂区域的类型与衬 底相同， 为了 4艮好地抑制短沟道效应， 在衬底中形成倒掺杂阱 200, 所述离 子注入形成的掺杂浓度最高值为 5e 17cm"3~le 19cm"3。
[0036]接下来， 在靠近漏区的伪栅空位下方的衬底中形成第二掺杂阱 300, 所述第二掺杂阱位于靠近漏区的伪栅空位下方 15~25nm处的衬底中， 所述 第二掺杂阱的长度为第一掺杂阱长度的 1/4~1/2。
[0037】具体的， 如图 4所示， 形成第二掺杂阱 300的方法可以是： 在靠近 源端的伪栅空位中形成掩膜 106,对所述伪栅空位下方未被掩膜覆盖的衬底 进行离子注入。 所述掩膜 106可以是光刻胶， 具体的， 在所述伪栅空位中 填充光刻胶， 通过掩膜板进行曝光、 显影、 去胶的工艺过程去除靠近漏端 一侧的光刻胶，暴露出衬底 100,去除的光刻胶长度等于所需第二掺杂阱的 长度。 其中， 所述离子注入的方向与衬底垂直， 通过控制离子注入的剂量 和能量， 则可在未被光刻胶覆盖的半导体衬底 100下方形成第二掺杂阱 300, 如图 5所示。 之后去除掩膜 106, 露出衬底 100。
[0038】可选的， 如图 6所示， 形成第二掺杂阱 300的方法还可以是： 以侧 墙为掩膜， 对所述伪栅空位下方的衬底进行入射角为 α的离子注入， 其中， 所述离子注入区域位于侧墙下方的部分不超过侧墙的边界。 也就是说， 倾 斜注入衬底中的掺杂离子沿沿与沟道平行的方向进入衬底中的最远距离不 超过侧墙 104与层间介质层相邻的边界， 避免第二掺杂阱 300与漏区相连 而对器件产生的一些不良影响。 同时， 根据靠近漏端一侧的离子注入范围 可确定离子注入的倾斜角度 α。 需要注意的是， 为了确保第二掺杂阱 300 的长度在我们需要的范围之内， 根据数学关系， 在此处作为掩膜的侧墙高 度必须不小于 L/tana,其中 L为伪第一掺杂阱与第二掺杂阱之间的长度差。
[0039]第二掺杂阱 300形成之后， 在栅极空位中依次形成栅极介质层 201、 功函数调节层 202和栅极金属层 203。 栅极金属层 203可以只为金属栅极， 也可以为金属 /多晶硅复合栅极， 其中多晶硅上表面上具有硅化物。 具体的 如图 7所示， 优选的， 在栅极介质层 201上先沉积功函数金属层， 之后再 在功函数金属层之上形成金属导体层。 功函数金属层可以采用 TiN、 TaN 等材料制成， 其厚度范围为 3nm~15nm。 金属导体层可以为一层或者多层 结构。 其材料可以为 TaN、 TaC、 TiN、 TaAlN、 TiAlN、 ΜοΑ1Ν、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax中的一种或其组合。 其厚度范围例如可以为 10nm -40nm, 如 20nm或 30nm。
[0040] 虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离本 发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例 进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当 容易理解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。 [0041]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或者以后即将 开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执 行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要求旨在将这些 工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种 MOSFET制造方法， 包括：
a.提供衬底（100 );
b.在衬底上形成伪栅堆叠及其侧墙（ 104 )、源 /漏区和层间介质层（ 105 ); c.去除所述伪栅堆叠以形成伪栅空位；
d.在伪栅空位下方的衬底中形成第一掺杂阱 (200);
e.在靠近漏区的伪栅空位下方的衬底中形成第二掺杂阱 (300);
f.对所述器件进行退火， 以激活掺杂；
g.在所述开口中沉积栅极介质层（201 )、 功函数调节层（202 )和栅极 金属层（ 203 )。
2、 根据权利要求 1所述的制造方法， 其特征在于， 所述第一掺杂阱 (200) 的形成方式是： 对所述伪栅空位下方的衬底（ 100 )进行离子注入， 所述离 子注入的方向与衬底（100 )垂直。
3、根据权利要求 1和 2所述的制造方法，其特征在于，所述第一掺杂阱（ 200 ) 位于伪栅空位下方 35~45nm处的衬底中。
4、 根据权利要求 1所述的制造方法， 其特征在于， 所述第二掺杂阱（300 ) 的形成方法是： 在靠近源端的伪栅空位中形成掩膜（ 106 ), 对所述伪栅空 位下方未被掩膜（106 )覆盖的衬底（100 )进行离子注入， 所述离子注入 的方向与衬底（ 100 )垂直。
5、 根据权利要求 1所述的制造方法， 其特征在于， 所述第二掺杂阱（300 ) 的形成方法是： 以侧墙（ 104 )为掩膜， 对所述伪栅空位下方的衬底（ 100 ) 进行入射角为 α的离子注入， 其中， 所述离子注入区域位于侧墙（ 104 )下 方的部分不超过侧墙（104 ) 的边界。
6、 根据权利要求 1和 5所述的制造方法， 其特征在于,所述侧墙（ 104 )的 高度不小于 L/tana, 其中 L为伪第一掺杂阱 (200)与第二掺杂阱（ 300 )之间 的长度差。
7、 根据权利要求 1所述的制造方法， 其特征在于， 所述第二掺杂阱（300 ) 位于靠近漏区的伪栅空位下方 15~25nm处的衬底中。
8、 根据权利要求 1、 3和 4所述的制造方法， 其特征在于， 所述第二掺杂 阱（300) 的长度为第一掺杂阱（200)长度的 1/4~1/2。
9、 根据权利要求 1、 2、 3和 4所述的制造方法， 其特征在于， 所述离子注 入的类型与衬底相同， 浓度为 5el7cm_3~lel9cm_3。
10、 一种 MOSFET结构， 包括： 衬底（100)、 侧墙（104)、 源区和漏区、 栅极介质层（201)、 功函数调节层（202)、 栅极金属层（203 )、 第一掺杂 阱（200)和第二掺杂阱（300), 其中， 所述第一掺杂阱（200)和第二掺 杂阱（300) 的掺杂类型与衬底（100)相同。
11、根据权利要求 10所述的制造方法，其特征在于，所述第一掺杂阱（200) 位于栅极下方 35~45nm处的衬底中。
12、根据权利要求 10所述的制造方法，其特征在于，所述第二掺杂阱（300) 位于靠近漏区的栅极下方 15~25nm处的衬底中。
13、 根据权利要求 10所述的制造方法， 其特征在于,所述侧墙（ 104 )的高 度不小于 L/tana, 其中 L为伪第一掺杂阱 (200)与第二掺杂阱（ 300 )之间的 长度差。
14、 根据权利要求 10和 12所述的制造方法， 其特征在于， 所述第二掺杂 阱（300) 的长度为第一掺杂阱（200)长度的 1/4~1/2。
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