WO2014063403A1 - 准纳米线晶体管及其制造方法 - Google Patents

准纳米线晶体管及其制造方法 Download PDF

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WO2014063403A1
WO2014063403A1 PCT/CN2012/085331 CN2012085331W WO2014063403A1 WO 2014063403 A1 WO2014063403 A1 WO 2014063403A1 CN 2012085331 W CN2012085331 W CN 2012085331W WO 2014063403 A1 WO2014063403 A1 WO 2014063403A1
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Prior art keywords
layer
quasi
dielectric layer
source
fin
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PCT/CN2012/085331
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English (en)
French (fr)
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朱慧珑
梁擎擎
尹海洲
骆志炯
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中国科学院微电子研究所
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Priority to US14/437,506 priority Critical patent/US9716175B2/en
Publication of WO2014063403A1 publication Critical patent/WO2014063403A1/zh

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
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    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a quasi-nanowire transistor and a method of fabricating the same. Background technique
  • MOSFETs metal oxide field effect transistors
  • a series of negligible effects in the long channel model of MOSFETs become more pronounced and even become the dominant factor affecting performance.
  • the short channel effect causes the electrical performance of the device to deteriorate, such as causing a drop in the gate threshold voltage, an increase in power consumption, and a decrease in signal-to-noise ratio.
  • the industry's dominant idea is to improve the traditional planar device technology, to reduce the thickness of the channel region, to eliminate the neutral layer at the bottom of the depletion layer in the channel, and to consume the channel.
  • the full layer can fill the entire channel region - this is the so-called Fully Depleted (FD) device, while the traditional planar device is a Partialiy Depleted (PD) device.
  • FD Fully Depleted
  • PD Partialiy Depleted
  • the thickness of the silicon layer at the channel is required to be extremely thin.
  • Traditional manufacturing processes, especially traditional silicon-based manufacturing processes, are difficult to produce to meet the required structure or costly, even for emerging SOI (silicon-on-insulator) processes, the thickness of the trench silicon layer is difficult to control. At a thinner level. Focusing on the overall concept of how to implement a fully depleted device, the focus of research and development is shifting to a three-dimensional device structure.
  • a three-dimensional device structure (also referred to as a vertical device in some materials) refers to a technique in which the source and drain regions of the device and the cross section of the gate are not in the same plane, and the essence is a FinFET (Fin Field Effect). Transistor) structure.
  • FinFET Fin Field Effect
  • the semiconductor device includes: a fin 020, the fin 020 is located on an insulating layer 010; a source/drain region 030, the source/drain region 030 And a second surface 024 of the fin 020 adjacent to the first side 022 A gate dielectric layer and a work function metal layer sandwiched between the gate 040 and the fins 020 are shown.
  • the edge portion of the source/drain region 030 may be expanded to reduce the source-drain region resistance, that is, the width of the source/drain region 030 (in the xx' direction) is greater than the thickness of the fin 020.
  • the three-dimensional semiconductor structure is expected to use the 22nm technology node and below. As the device size is further reduced, the short channel effect of the three-dimensional semiconductor device will also become a major factor affecting device performance.
  • nanowire MOSFETs can control short channel effects with low random doping fluctuations, and are therefore promising for future scale-down MOSFETs.
  • the manufacturing process of nanowire devices is currently very difficult. Summary of the invention
  • high-k gate dielectrics and metal gates can be integrated into quasi-nano-line transistors to improve the performance of semiconductor devices.
  • a method of fabricating a semiconductor structure characterized by comprising the steps of:
  • Step S101 providing an SOI substrate, the SOI substrate comprising a base layer, a BOX layer and an SOI layer;
  • Step S102 forming a fin substrate on the SOI layer, the fin substrate comprising at least one set of silicon/silicon germanium stack;
  • Step S103 forming source and drain regions on both sides of the fin substrate
  • Step S104 forming quasi-nano-wire fins from the fin substrate and the SOI layer therebelow;
  • Step S105 forming a gate stack across the quasi-nanowire fins. Accordingly, the present invention also provides a semiconductor structure including:
  • an SOI substrate including an SOI layer, a BOX layer, and a base layer;
  • a fin formed from a portion of the SOI layer and at least one set of silicon/silicon stacks thereon;
  • a source/drain region extending in a width direction of the fin on both sides of the fin, the fin being located in a recess formed by the extended source/drain region, and a portion of the source/drain region not connected to the fin is formed with a side Wall
  • the source and drain regions are formed first, and then the quasi-nano-wire fins are formed, and the gate length characteristics, such as the gate length and the bottom and the top, can be controlled. Align and so on.
  • the present invention reduces the short channel effect of the device by integrating a high-k gate dielectric and a metal gate into the fin-type quasi-nano-field field effect transistor, thereby contributing to an improvement in the performance of the semiconductor device.
  • the strained source and drain regions depending on the device type can apply different stresses to the quasi-nanowire fins depending on the device type, thereby increasing the mobility of the channel carriers.
  • FIG. 1 is a schematic view of a fin field effect transistor in the prior art
  • FIG. 2 is a flow chart showing an embodiment of a method of fabricating a quasi-nanowire transistor according to the present invention
  • FIG. 3 is a cross-sectional structural view showing a substrate used in a specific embodiment of a method for fabricating a quasi-nanowire transistor of the present invention
  • FIG. 4 is a cross-sectional structural view showing a material layer required for fabricating a quasi-nanowire transistor on a substrate in a specific embodiment of a method for fabricating a quasi-nanowire transistor according to the present invention
  • FIG. 5 is a cross-sectional structural view showing the semiconductor structure shown in FIG. 4 after being etched; [0030] FIG.
  • FIG. 6 is a cross-sectional structural view showing the semiconductor structure shown in FIG. 5 after epitaxial growth and deposition of an oxide;
  • FIG. 7 is a schematic top plan view showing a photoresist pattern formation on the semiconductor structure shown in FIG. 6; [0032] FIG.
  • FIG. 8 is a top plan view showing the semiconductor structure shown in FIG. 7 after etching
  • FIG. 9 is a cross-sectional structural view of the semiconductor structure shown in FIG. 8 taken along line A-A'; [0034] FIG.
  • FIG. 10 is a cross-sectional structural view of the semiconductor structure shown in FIG. 8 taken along the line 1-1"; [0035] FIG.
  • FIG. 11 is a top plan view showing the structure of the semiconductor structure shown in FIG. 8 when forming a sidewall; [0036] FIG.
  • FIG. 12 is a cross-sectional structural view of the semiconductor structure shown in FIG. 11 taken along line A-A'; [0037] FIG.
  • Figure 13 is a cross-sectional structural view of the semiconductor structure shown in Figure 11 taken along the line 1-1";
  • FIG. 14 is a cross-sectional structural view after etching the fins in the semiconductor structure shown in FIG. 12; [0039] FIG.
  • FIG. 15 is a top plan view showing the structure of the semiconductor structure shown in FIG. 14 when a metal layer is formed;
  • FIG. 16 is a cross-sectional structural view of the semiconductor structure shown in FIG. 15 taken along the line A-A'; [0041] FIG.
  • FIG. 17 is a cross-sectional structural view of the semiconductor structure shown in FIG. 15 taken along the line 1-1".
  • first and second features are formed in direct contact
  • additional features are formed between the first and second features such that the first and second features may Not direct contact.
  • the method for fabricating a quasi-nanowire transistor provided by the present invention generally includes:
  • Step S101 providing an SOI substrate, the SOI substrate comprising a base layer, a BOX layer and an SOI layer;
  • Step S102 forming a fin substrate on the SOI layer, the fin substrate comprising at least one set of silicon/silicon germanium stack;
  • Step S103 forming source and drain regions on both sides of the fin substrate
  • Step S104 forming quasi-nano-wire fins from the fin substrate and the SOI layer therebelow;
  • Step S105 forming a gate stack across the quasi-nanowire fins.
  • Step S101 as shown in FIG. 3, an SOI substrate is provided, the SOI substrate having at least a three-layer structure, respectively: a base layer 100 (for example, a bulk silicon layer, only part of which is shown in FIG. The base layer 100), the BOX layer 120 above the base layer 100, and the SOI layer 130 overlying the BOX layer 120.
  • the material of the BOX layer 120 is generally selected from SiO 2 , and the thickness of the BOX layer 120 is generally greater than 100 nm;
  • the material of the SOI layer 130 is a single crystal silicon, germanium or a III-V compound (eg, silicon carbide, gallium arsenide, arsenic).
  • the SOI substrate selected in the embodiment is an SOI substrate having an Ultrathin (ultra-thin) SOI layer 130, and thus the SOI layer 130 has a thickness ranging from 5 nm to 20 nm, for example, 5 nm. 13nm or 20nm.
  • the crystal orientation of the SOI layer is ⁇ 100>.
  • Step S102 is performed to form a fin substrate on the SOI layer, the fin substrate comprising at least one set of silicon/silicon stacks.
  • a fin substrate having a length is formed on the SOI layer, the fin substrate including at least one set of silicon/silicon stacks and covered with a first dielectric layer.
  • At least one set of silicon/silicon stack, third dielectric layer 140, and first dielectric layer 150 are sequentially formed on the SOI substrate.
  • At least one of the silicon/silicon stacks includes, for example, a first set of silicon/silicon stacks (first silicon spacer 310, first silicon layer 320), and a second set of silicon/silicon stacks (second silicon fault) Layer 330, and second silicon layer 340). More or fewer sets of silicon/silicon germanium stacks can be included.
  • At least one set of silicon / The silicon germanium stack, the third dielectric layer 140 and the first dielectric layer 150 may be deposited by chemical vapor deposition (CVD), high density plasma CVD, ALD (atomic layer deposition), plasma enhanced atomic layer deposition.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the first silicon germanium layer 310 and the second silicon dummy layer 330 may each have a thickness ranging from 1 to 3 nm. Among them, the content of niobium is 5% to 10% of the entire silicon germanium material.
  • the first silicon layer 320 and the second silicon layer 340 have a thickness ranging from 5 to 20 nm.
  • the material of the third dielectric layer 140 may be, for example, SiO 2 having a thickness of between 2 nm and 5 nm, for example, 2 nm, 4 nm, and 5 nm.
  • the material of the first dielectric layer 150 may be, for example, Si 3 N 4 having a thickness of between 50 nm and 150 nm, for example, 50 nm, 100 nm, and 150 nm.
  • photoresist patterning is performed on the first dielectric layer 150, and the pattern of the photoresist corresponds to the pattern of the fin substrate, for example, a strip having a certain length extending in the width direction of the semiconductor structure (generally It is considered that the horizontal direction shown in the schematic cross-sectional view is the longitudinal direction, and the direction perpendicular to the cross-sectional view of the cross-sectional view is the width direction corresponding to the fin substrate, the fin structure to be formed, and the channel of the semiconductor device. Longitudinal direction).
  • the patterned first photoresist layer 150, the third dielectric layer 140, and at least one set of silicon/silicon stacks are etched using the patterned photoresist as a mask (eg, including the second silicon layer 340, the second silicon germanium layer 330, The first silicon layer 320 and the first silicon spacer 310) stop at the top of the SOI layer 130 to form a structure with a middle height and a low side, as shown in FIG.
  • etching may also remove a portion of the SOI layer 130 as long as a portion of the SOI layer 130 is left.
  • the bumps of the etched semiconductor material are referred to herein as fin substrates which are covered with a third dielectric layer 140 and a first dielectric layer 150.
  • the fin substrate is used to form fins of a quasi-nanowire transistor in a subsequent step.
  • the etching process such as ion etching.
  • the first dielectric layer 150 and the third dielectric layer 140 may not be formed.
  • Step S103 is performed to form source and drain regions on both sides of the fin substrate.
  • the source and drain regions 110 are formed on both sides in the longitudinal direction of the fin substrate, and the second dielectric layer 160 is covered on the source and drain regions, and the material of the second dielectric layer is different from the first dielectric layer.
  • epitaxial growth is performed on the SOI layer 130 of the SOI substrate to form source and drain regions 110.
  • the height of the source and drain regions 110 is slightly higher than the upper surface of the third dielectric layer 140.
  • the source and drain regions 110 can be source and drain regions of stress materials.
  • the source/drain region 110 material may be a Si ⁇ xGex (value of X)
  • the circumference can be 0.15 - 0.75, which can be flexibly adjusted according to the process requirements, such as 0.15, 0.3, 0.4, 0.5 or 0.75.
  • the values of X are the same, no longer repeat them;
  • the material of the source and drain region 110 may be Si:C (the atomic percentage of C may be 0.5% to 2%, such as 0.5%, 1% or 2%, and the content of C may be flexibly adjusted according to process requirements, this document Unless otherwise specified, the atomic percentage of C is the same, and will not be described again.
  • the source and drain regions 110 may be doped in situ during growth, and/or ion implantation may be performed on the source and drain regions 110 and annealed to activate impurities.
  • B can be used for implantation;
  • NMOS devices As or P can be used for injection.
  • the stressor source and drain regions 110 can further adjust the stress in the fin substrate, thereby adjusting the stress in the fins formed from the fin substrate to improve the migration of carriers in the channel region in the fin. rate.
  • the second dielectric layer 160 can then be formed over the entire semiconductor structure.
  • the material of the second dielectric layer 160 is different from the first dielectric layer 150.
  • the second dielectric layer 160 may be an oxide layer.
  • the second dielectric layer 160 may be formed by chemical vapor deposition, high density plasma CVD, atomic layer deposition, plasma enhanced atomic layer deposition, pulsed laser deposition, or other suitable method.
  • the material of the second dielectric layer 160 may be Si0 2 .
  • a planarization operation is performed, stopping on the first dielectric layer 150. As shown in FIG. 6, a second dielectric layer 160 covering the source and drain regions 110 is formed, the upper surface of which is flush with the upper surface of the first dielectric layer 150.
  • the second dielectric layer 160 may not be formed.
  • Step S104 is performed to form quasi-nanowire fins from the fin substrate and the SOI layer therebelow.
  • the source and drain regions 110 and the recesses formed by the second dielectric layer 160 on both sides in the longitudinal direction of the fin substrate are formed by the fin substrate and the SOI layer therebelow along the length direction.
  • the photoresist 200 is formed on a semiconductor structure, for example, by spin coating or exposure development, and the place where the fins are intended to be formed is protected, as shown in FIG.
  • the material of the photoresist layer may be an ethylenic monomer material, a material containing an azide compound or a polyethylene laurate material.
  • the sidewall spacers 210 are formed on both sides of the source and drain regions 110, as shown in Figs. 11, 12 and 13.
  • the sidewall spacers 210 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 210 may have a multi-layered structure.
  • the spacer 210 may be formed by a deposition etching process, and may have a thickness ranging from 5 nm to 10 nm, for example, 5 nm, 8 nm, and 10 nm.
  • the side wall 210 is at least higher than the source/drain region 110.
  • a sidewall 210 is not formed on the fin structure.
  • the fins may be etched after forming the sidewall spacers 210 such that the cross-section of the sidewalls thereof forms a sawtooth shape.
  • the first silicon layer 320 and the second silicon layer may be controlled by controlling the orientation of the fin substrate and by using tetradecylammonium hydroxide (TMAH) or 011.
  • TMAH tetradecylammonium hydroxide
  • 340 and the SOI layer 130 are wet etched.
  • the structure of the fins is an SOI layer 130, a first silicon germanium layer 310, a first silicon layer 320, a second silicon spacer 330, a second silicon layer 340, and a third dielectric layer 140, which are sequentially arranged.
  • the silicon layer is etched, the silicon dummy layer and the third dielectric layer 140 are not etched. Since the etching is etched along the ⁇ 111 ⁇ crystal plane of each silicon layer, fins having a zigzag cross section are finally formed. The crystal orientation of the surface of the silicon layer at the sidewall of the fin is ⁇ 111>.
  • Fins having a sawtooth shaped cross section have a larger sidewall area than conventional fins, which increases the width of the channel region.
  • Step S105 forming a gate stack across the quasi-nanowire fins.
  • a gate dielectric layer 220 covering the fin structure and a gate metal layer 230 covering the gate dielectric layer 220 are formed in the recess.
  • a gate dielectric layer 220 (eg, a high-k dielectric layer) covering the entire semiconductor structure is formed; then a metal layer (eg, a voltage-regulating metal layer is turned on) is deposited on the gate dielectric layer 220 to form a gate metal layer 230.
  • the planarization is performed such that the upper surface of the metal layer 230 in the recess is flush with the upper surface of the second dielectric layer 160, as shown in FIGS. 15, 16, and 17.
  • the metal layer on other areas than the recessed area is removed.
  • the high-k medium may be, for example, one of HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON or a combination thereof, preferably Hf0 2 .
  • the gate dielectric layer 220 may have a thickness of 2 nm to 4 nm, for example, 2 nm, 3 nm, or 4 nm.
  • the gate dielectric layer 220 may be formed by a process such as thermal oxidation, chemical vapor deposition, atomic layer deposition, or the like.
  • the gate metal layer may be TaN, TaC, TiN, TaAlN, TiAIN, MoAIN, TaTbN, TaErN, TaYbN, TaSiN, One of HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof.
  • Thermally oxidized gate dielectric layers and polysilicon gates may also be formed in other embodiments.
  • the source and drain regions are formed first, and then the quasi-nano-wire fins are formed, and the gate length characteristics, such as the gate length and the bottom and the top, can be controlled. Align and so on.
  • the present invention reduces the short channel effect of the device by integrating a high-k gate dielectric and a metal gate into the fin-type quasi-nano-field field effect transistor, thereby contributing to an improvement in the performance of the semiconductor device.
  • the strained source and drain regions depending on the device type can apply different stresses to the quasi-nanowire fins depending on the device type, thereby increasing the mobility of the channel carriers.
  • a quasi-nanowire transistor comprising:
  • an SOI substrate including an SOI layer 130, a BOX layer 120, and a substrate layer 100;
  • a fin formed from a portion of the SOI layer 130 and at least one set of silicon/silicon stacks thereon;
  • a gate metal layer 230 covers the gate dielectric layer 220.
  • the SOI substrate is a three-layer structure, which is a base layer 100, a BOX layer 120 above the base layer 100, and an SOI layer 130 overlying the BOX layer 120.
  • the material of the BOX layer 120 is generally selected from SiO 2 , and the thickness of the BOX layer 120 is generally greater than 100 nm; the material of the SOI layer 130 is a single crystal silicon, germanium or a III-V compound (eg, silicon carbide, gallium arsenide, arsenic).
  • the SOI substrate selected in the present embodiment is an SOI substrate having an Ultrathin (ultra-thin) SOI layer 130, and thus the SOI layer 130 has a thickness ranging from 5 nm to 20 nm, for example, 5 nm. 13 nm or 20 nm.
  • the source and drain regions 110 are located on the SOI layer 130 with a height slightly higher than the upper surface of the third dielectric layer 140.
  • the source/drain region 110 material may be Si lc Ge x (the value of X may range from 0.15 to 0.75, and may be flexibly adjusted according to process requirements, such as 0.15, 0.3, 0.4, 0.5 or 0.75, in this document
  • the material of the source and drain region 110 may be Si:C (the atomic percentage of C may be 0.5% to 2%, For example, 0.5%, 1% or 2%, the content of C can be flexibly adjusted according to the process requirements. Unless otherwise specified in this document, the atomic percentage of C is the same, and will not be described again.
  • the stress material source and drain region 110 can be further adjusted The stress in the channel region increases the mobility of carriers in the channel region.
  • the second dielectric layer 160 is located on the source and drain regions 110, and the material of the second dielectric layer 160 may be Si0 2 .
  • the sidewall spacers 210 are located on both sides of the source and drain regions 110 for separating the source/drain regions 110 from the gates formed thereafter, and thus have a height at least higher than the height of the source/drain regions 110.
  • the sidewall 210 can be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 210 may have a multi-layered structure. The thickness of the sidewall 210 may range from 5 nm to 10 nm, such as 5 nm, 8 nm, and 10 nm.
  • the fin includes an SOI layer 130 and a first dielectric layer 310, a first silicon layer 320, a second silicon germanium layer 330, a second silicon layer 340, and a third dielectric layer 140 of a thin oxygen layer thereon.
  • the fins have a zigzag cross section, that is, each silicon layer is etched along the ⁇ 111 ⁇ plane.
  • the material of the thin oxygen layer is Si0 2 . Its thickness is between 2 nm and 5 nm, for example 2 nm, 4 nm, 5 nm.
  • the thickness of the first silicon germanium layer 310 and the second silicon dummy layer 330 ranges from 1 to 3 nm. Among them, the content of niobium is 5% to 10% of the entire silicon germanium material.
  • the first silicon layer 320 and the second silicon layer 340 have thicknesses ranging from 5 to 2011111.
  • a gate dielectric layer 220 covers the fins.
  • the high-k medium may be, for example, one of HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON or a combination thereof, preferably Hf0 2 .
  • the gate dielectric layer 220 may have a thickness of 2 nm to 4 nm, for example, 2 nm, 3 nm, or 4 nm.
  • a gate metal layer 230 (eg, a turn-on voltage regulating metal layer) covers the BOX layer 120, sidewalls 210, and fins.
  • the gate metal layer 230 may be one of TaN, TaC, TiN, TaAIN, TiAIN, MoAIN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof.

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Abstract

一种准纳米线晶体管及其制造方法，该方法包括：提供SOI衬底，该SOI衬底包括基底层（100），BOX层（120）和SOI层（130）；在SOI层上形成鳍片基体，鳍片基体包括至少一组硅/硅锗叠层；在鳍片基体的两侧形成源漏区（110）；由鳍片基体以及其下的SOI层形成准纳米线鳍片；横跨准纳米线鳍片形成栅堆叠。该方法可以有效地控制栅长特性。以及由该方法形成的半导体结构。

Description

准纳米线晶体管及其制造方法
[0001】本申请要求了 2012年 10月 23日提交的、 申请号为 201210407807.8、 发 明名称为"准纳米线晶体管及其制造方法"的中国专利申请的优先权， 其全部 内容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体技术领域， 尤其涉及一种准纳米线晶体管及其制造 方法。 背景技术
[0003]随着 MOSFET (金属氧化物场效应晶体管）沟道长度不断缩短， 一系 列在 MOSFET长沟道模型中可以忽略的效应变得愈发显著， 甚至成为影响性 能的主导因素， 这种现象统称为短沟道效应。 短沟道效应导致器件的电学性 能恶化， 如造成栅极阈值电压下降、 功耗增加以及信噪比下降等问题。
[0004]为了改善短沟道效应， 业界的主导思路是改进传统的平面型器件技 术， 想办法减小沟道区的厚度， 消除沟道中耗尽层底部的中性层， 让沟道中 的耗尽层能够填满整个沟道区一这便是所谓的全耗尽型（ Fully Depleted: FD ) 器件， 而传统的平面型器件则属于部分耗尽型 （Partialiy Depleted: PD ) 器 件。
[0005]不过， 要制造出全耗尽型器件， 要求沟道处的硅层厚度极薄。 传统的 制造工艺，特别是传统基于体硅的制造工艺很难造出符合要求的结构或造价 昂贵， 即便对新兴的 SOI (绝缘体上硅） 工艺而言， 沟道硅层的厚度也很难 控制在较薄的水平。 围绕如何实现全耗尽型器件的整体构思， 研发的重心转 向立体型器件结构。
[0006]立体型器件结构（有的材料中也称为垂直型器件）指的是器件的源漏 区和栅极的横截面并不位于同一平面内的技术， 实质属 FinFET (鳍式场效应 晶体管）结构。
[0007】转向立体型器件结构之后， 由于沟道区不再包含在体硅或 SOI中， 而 是从这些结构中独立出来， 因此， 采取蚀刻等方式可能制作出厚度极薄的全 耗尽型沟道。
[0008] 当前， 已提出的立体型半导体器件如图 1所示， 所述半导体器件包括： 鳍片 020, 所述鳍片 020位于绝缘层 010上； 源漏区 030, 所述源漏区 030接于 所述鳍片 020中相对的第一侧面 022;栅极 040,所述栅极 040位于所述鳍片 020 中与所述第一侧面 022相邻的第二侧面 024上（图中未示出所述栅极 040及所 述鳍片 020间夹有的栅介质层和功函数金属层）。 其中， 为减小源漏区电阻， 所述源漏区 030的边缘部分可被扩展， 即， 所述源漏区 030的宽度（沿 xx'方 向） 大于所述鳍片 020的厚度。 立体型半导体结构有望应用 22nm技术节点及 其以下， 随着器件尺寸进一步缩小， 立体型半导体器件的短沟道效应也将成 为影响器件性能的一大因素。
[0009]作为一种立体型器件， 纳米线 MOSFET可以 4艮好地控制短沟道效应， 具有很低的随机掺杂波动， 因此很有希望用于未来的进一步按比例缩小的 MOSFET。 然而， 目前纳米线器件的制造工艺难度 4艮大。 发明内容
[0010]本发明的目的在于提供一种准纳米线（ quasi-nanowire )晶体管及其制 造方法，其可以 ^艮好地控制栅长特性，例如栅极长度和底部与顶部的对准等。 另外， 可以将高 k栅介质和金属栅集成到准纳米线晶体管中， 提升半导体器 件的性能。 另外， 本发明的目的还在于在准纳米线晶体管中提供具有应力的 应变的源漏区。
[0011]根据本发明的一个方面， 提供一种半导体结构的制造方法， 其特征在 于， 包括以下步骤：
[0012]步骤 S101 , 提供 SOI衬底， 该 SOI衬底包括基底层， BOX层和 SOI层；
[0013]步骤 S102, 在 SOI层上形成鳍片基体， 所述鳍片基体包括至少一组硅 / 硅锗叠层；
[0014]步骤 S103 , 在鳍片基体的两侧形成源漏区；
[0015]步骤 S104, 由鳍片基体以及其下的 SOI层形成准纳米线鳍片；
[0016]步骤 S105, 横跨所述准纳米线鳍片形成栅堆叠。 [0017】相应地， 本发明还提供了一种半导体结构， 该半导体结构包括：
[0018] SOI衬底， 包括 SOI层、 BOX层和基底层；
[0019]鳍片， 由 SOI层的一部分以及其上的至少一组硅 /硅错叠层形成；
[0020]位于鳍片两侧在鳍片的宽度方向上延伸的源漏区，所述鳍片位于延伸 的源漏区形成的 陷中， 源漏区未与鳍片相连的部分上形成有侧墙；
[0021】栅介质层， 覆盖所述鳍片；
[0022]栅金属层， 覆盖所述栅介质层。
[0023]本发明提供的准纳米线晶体管及其制造方法中， 先形成源漏区， 后形 成准纳米线鳍片， 可以 ^艮好地控制栅长特性， 例如栅极长度和底部与顶部的 对准等。 另外， 本发明通过将高 k栅介质和金属栅集成到鳍型准纳米线场效 应晶体管中， 减小器件的短沟道效应， 进而有助于提高半导体器件的性能。 另外，取决于器件类型而形成的应变的源漏区根据器件类型可以向准纳米线 鳍片施加不同的应力， 从而增加沟道载流子的迁移率。 附图说明
[0024]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本 发明的其它特征、 目的和优点将会变得更明显。
[0025]下列各剖视图均为沿对应的俯视图中给出的剖线（ AA，或 11" )切割已 形成的结构后获得。
[0026] 图 1所示为现有技术中鳍型场效应晶体管的示意图；
[0027] 图 2为根据本发明的准纳米线晶体管的制造方法的实施方式的流程 图；
[0028] 图 3所示为本发明准纳米线晶体管的制造方法具体实施例中所使用的 衬底的剖视结构示意图；
[0029] 图 4所示为本发明准纳米线晶体管的制造方法具体实施例中在衬底上 形成为制造准纳米线晶体管所需的各材料层后的剖视结构示意图；
[0030] 图 5是对图 4示出的半导体结构进行刻蚀后的剖视结构示意图；
[0031] 图 6是对图 5示出的半导体结构进行外延生长和沉积氧化物之后的剖 视结构示意图； [0032] 图 7是在图 6示出的半导体结构上形成光刻胶构图时的俯视结构示意 图；
[0033] 图 8是对图 7示出的半导体结构进行刻蚀后的俯视结构示意图；
[0034] 图 9是图 8示出的半导体结构沿 A-A'方向的剖视结构示意图；
[0035] 图 10是图 8示出的半导体结构沿 1-1"方向的剖视结构示意图；
[0036] 图 11是图 8示出的半导体结构形成侧墙时的俯视结构示意图；
[0037] 图 12是图 11示出的半导体结构沿 A-A'方向的剖视结构示意图；
[0038] 图 13是图 11示出的半导体结构沿 1-1"方向的剖视结构示意图；
[0039] 图 14是对图 12示出的半导体结构中的鳍片进行刻蚀后的剖视结构示 意图；
[0040] 图 15是图 14示出的半导体结构形成金属层时的俯视结构示意图；
[0041] 图 16是图 15示出的半导体结构沿 A-A'方向的剖视结构示意图；
[0042] 图 17是图 15示出的半导体结构沿 1-1"方向的剖视结构示意图。
[0043]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0044]为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本 发明的实施例作详细描述。
[0045】下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功 能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明， 而不能解释为对本发明的限制。
[0046]下文的公开提供了许多不同的实施例或例子用来实现本发明的不同 结构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在 不同例子中重复参考数字和 /或字母。这种重复是为了筒化和清楚的目的，其 本身不指示所讨论各种实施例和 /或设置之间的关系。此外，本发明提供了的 各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工 艺的可应用于性和 /或其他材料的使用。另外， 以下描述的第一特征在第二特 征之"上"的结构可以包括第一和第二特征形成为直接接触的实施例， 也可以 包括另外的特征形成在第一和第二特征之间的实施例， 这样第一和第二特征 可能不是直接接触。 应当注意， 在附图中所图示的部件不一定按比例绘制。 本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本 发明。
[0047]本发明提供的准纳米线晶体管的制造方法大致包括：
[0048]步骤 S101 , 提供 SOI衬底， 该 SOI衬底包括基底层， BOX层和 SOI层；
[0049]步骤 S102, 在 SOI层上形成鳍片基体， 所述鳍片基体包括至少一组硅 / 硅锗叠层；
[0050]步骤 S103 , 在鳍片基体的两侧形成源漏区；
[0051]步骤 S104, 由鳍片基体以及其下的 SOI层形成准纳米线鳍片；
[0052]步骤 S105 , 横跨所述准纳米线鳍片形成栅堆叠。
[0053]下文中将参照图 2到图 17, 结合本发明提供的半导体结构的制造方法 的一个具体实施例对各步骤进行进一步的阐述。
[0054]步骤 S101 , 如图 3所示， 提供 SOI衬底， 所述 SOI衬底至少具有三层结 构， 分别是：基底层 100 (例如，体硅层， 图 3中只示出部分所述基底层 100 ) 、 基底层 100之上的 BOX层 120, 以及覆盖在 BOX层 120之上的 SOI层 130。其中， 所述 BOX层 120的材料通常选用 Si02, BOX层 120的厚度通常大于 lOOnm; SOI 层 130的材料是单晶硅、 锗或 III- V族化合物 （如碳化硅、 砷化镓、 砷化铟或 磷化铟等） ， 本具体实施方式中选用的 SOI衬底是具有 Ultrathin (超薄） SOI 层 130的 SOI衬底，因此该 SOI层 130的厚度范围为 5nm~20nm,例如 5nm, 13nm 或 20nm。 优选地， 该 SOI层的晶向为 <100>。
[0055】执行步骤 S102 , 在 SOI层上形成鳍片基体， 所述鳍片基体包括至少一 组硅 /硅错叠层。本具体实施例中，在 SOI层上形成具有一定长度的鳍片基体， 所述鳍片基体包括至少一组硅 /硅错叠层， 并覆盖有第一介质层。
[0056】如图 4所示， 在 SOI衬底上依次形成至少一组硅 /硅错叠层、 第三介质 层 140和第一介质层 150。 其中至少一组硅 /硅错叠层例如包括第一组硅 /硅错 叠层（第一硅错层 310、第一硅层 320 )、第二组硅 /硅错叠层（第二硅错层 330、 和第二硅层 340 ) 。 可以包括更多或者更少组的硅 /硅锗叠层。 至少一组硅 / 硅锗叠层、 第三介质层 140和第一介质层 150可以通过化学气相沉积 ( Chemical vapor deposition, CVD ) 、 高密度等离子体 CVD、 ALD (原子层 淀积） 、 等离子体增强原子层淀积（PEALD ) 、 脉沖激光沉积（PLD )或其 他合适的方法依次形成在 SOI层 130上。第一硅锗层 310和第二硅错层 330的厚 度范围均可以为 l~3nm。 其中， 锗的含量为整个硅锗材料的 5%~10%。 第一 硅层 320和第二硅层 340的厚度范围均为 5~20nm。 第三介质层 140的材料例如 可以是 Si02, 其厚度在 2nm~5nm之间， 例如 2nm, 4nm, 5nm。 第一介质层 150的材料例如可以是 Si3N4,其厚度在 50nm ~150nm之间，例如 50nm, lOOnm, 150nm。
[0057】例如， 在第一介质层 150上进行光刻胶构图， 光刻胶的图案与鳍片基 体的图案对应，例如具有一定长度的在半导体结构的宽度方向上延伸的条形 (文中一般认为各剖视结构示意图中所示的水平方向为长度方向， 与剖视结 构示意图纸面垂直的方向为宽度方向， 该长度方向对应鳍片基体、 将要形成 的鳍片结构以及半导体器件沟道的长度方向）。 因此以构图后的光刻胶为掩 模刻蚀第一介质层 150、 第三介质层 140、 至少一组硅 /硅错叠层（例如包括第 二硅层 340、 第二硅锗层 330、 第一硅层 320、 第一硅错层 310 ) , 停止于 SOI 层 130的顶部， 形成中间高、 两边低的结构， 如图 5所示。 在其他实施例中， 刻蚀也可以去除 SOI层 130的一部分， 只要留下一部分 SOI层 130即可。文中将 该刻蚀形成的半导体材料（包括硅错层和硅层）的凸起称为鳍片基体， 其覆 盖有第三介质层 140和第一介质层 150。 如下文所述， 该鳍片基体用于在后续 步骤中形成准纳米线晶体管的鳍片。 刻蚀工艺有多种选择， 例如可以采用离 子体刻蚀等。
[0058]在其他实施例中， 也可以不形成第一介质层 150和第三介质层 140。
[0059】执行步骤 S 103 , 在鳍片基体的两侧形成源漏区。 在本具体实施例中， 在鳍片基体的长度方向上的两侧形成源漏区 110, 并在源漏区上覆盖第二介 质层 160, 第二介质层的材料不同于第一介质层。 在上述刻蚀步骤后， 在所 述 SOI衬底的 SOI层 130上进行外延生长， 形成源漏区 110。 所述源漏区 110的 高度略高于第三介质层 140的上表面。 例如， 源漏区 110可以是应力材料源漏 区。 例如， 对于 PMOS器件， 所述源漏区 110材料可为 Si^xGex ( X的取值范 围可为 0.15 - 0.75 ,可以根据工艺需要灵活调节，如 0.15、 0.3、 0.4、 0.5或 0.75 , 本文件内未作特殊说明处， X的取值均与此相同， 不再赘述） ； 对于 NMOS 器件， 所述源漏区 110材料可为 Si:C ( C的原子数百分比可以为 0.5% ~ 2% , 如 0.5%、 1%或 2%, C的含量可以根据工艺需要灵活调节， 本文件内未作特 殊说明处， C的原子数百分比均与此相同， 不再赘述）。 源漏区 110可以在生 长的过程中进行原位掺杂， 和 /或可以对源漏区 110进行离子注入， 并退火， 以激活杂质。 对于 PMOS器件， 可以采用 B进行注入； 对于 NMOS器件， 可以 采用 As或 P进行注入。所述应力材料源漏区 110可进一步调节鳍片基体内的应 力， 从而可以调节后续将从鳍片基体形成的鳍片内的应力， 以提高鳍片内的 沟道区中载流子的迁移率。
[0060]之后可以在整个半导体结构上形成第二介质层 160。第二介质层 160的 材料不同于第一介质层 150。例如当第一介质层 150材料为是 Si3N4时， 第二介 质层 160可以是氧化物层。 可以通过化学气相沉积、 高密度等离子体 CVD、 原子层淀积、 等离子体增强原子层淀积、 脉沖激光沉积或其他合适的方法形 成第二介质层 160。 第二介质层 160的材料可以是 Si02。 形成第二介质层 160 之后执行平坦化操作， 停止于第一介质层 150上。 如图 6所示， 形成覆盖源漏 区 110的第二介质层 160, 其上表面与第一介质层 150上表面齐平。
[0061]在其他实施例中， 也可以不形成第二介质层 160。
[0062】执行步骤 S104, 由鳍片基体以及其下的 SOI层形成准纳米线鳍片。 在 本具体实施例中， 由鳍片基体以及其下的 SOI层形成位于鳍片基体的长度方 向上的两侧的源漏区 110以及第二介质层 160构成的凹陷中的沿所述长度方 向延伸的准纳米线鳍片。 例如， 在半导体结构上形成光刻胶 200, 例如可以 采用旋涂、 曝光显影的方式进行构图， 将意图形成鳍片的地方保护起来， 如 图 7所示。 光刻胶层的材料可是烯类单体材料、 含有叠氮醌类化合物的材料 或聚乙烯月桂酸酯材料等。
[0063]以构图的光刻胶 200为掩模刻蚀第一介质层 150、 第三介质层 140、 第 二硅层 340、 第二硅锗层 330、 第一硅层 320、 第一硅错层 310以及 SOI层 130, 停止于 BOX层 120的上表面。之后去除光刻胶 200, 并去除其下的第一介质层 150, 停止于第三介质层 140的上表面， 如图 8、 图 9、 图 10所示。 这样形成了 位于两侧的源漏区 110以及第二介质层 160构成的凹陷中的沿所述长度方向 延伸的鳍结构准纳米线晶体管的鳍片。
[0064]在本具体实施例中， 还需要在凹陷中暴露的 SOI层 130和源漏区 110的 侧壁上形成侧墙 210。 在源漏区 110两侧形成侧墙 210, 如图 11、 12和 13所示。 侧墙 210可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合 适的材料形成。 侧墙 210可以具有多层结构。 侧墙 210可以通过包括沉积刻蚀 工艺形成， 其厚度范围可以是 5nm~10nm, 例如 5nm, 8nm, 10nm。 侧墙 210 至少高于源 /漏区 110。 在鳍结构上并未形成侧墙 210。
[0065】可选地， 可以在形成侧墙 210后对所述鳍片进行刻蚀， 使其侧壁的截 面形成锯齿形状。 例如， 在 SOI层的晶向为 <100>的情况下， 可以通过控制鳍 片基体的取向，并通过采用四曱基氢氧化铵（ TMAH )或 011对第一硅层 320、 第二硅层 340以及 SOI层 130进行湿法刻蚀。 由于所述鳍片的结构为依次排列 的 SOI层 130、 第一硅锗层 310、 第一硅层 320、 第二硅错层 330、 第二硅层 340 和第三介质层 140。因此对硅层进行刻蚀时，不刻蚀硅错层和第三介质层 140。 由于刻蚀沿着各硅层的 { 111 }晶面进行刻蚀， 因此最后会形成截面为锯齿形 状的鳍片。 鳍片的侧壁处硅层表面的晶向为 <111>。
[0066]具有锯齿形状的截面的鳍片比普通的鳍片有更大的侧壁面积，会使沟 道区的宽度增加。
[0067]步骤 S105 , 横跨所述准纳米线鳍片形成栅堆叠。 在本具体实施例中， 在凹陷中形成覆盖鳍结构的栅介质层 220以及覆盖栅介质层 220的栅金属层 230。 形成覆盖整个半导体结构的栅介质层 220 (例如高 k介质层） ； 之后在 栅介质层 220上沉积金属层（例如开启电压调节金属层），形成栅金属层 230。 并进行平坦化，使所述凹陷中的金属层 230的上表面与第二介质层 160的上表 面齐平， 如图 15、 图 16、 图 17所示。 凹陷区域以外的其他区域上的金属层被 去除。所述高 k介质例如可以是： HfAlON、 HfSiAlON、 HfTaAlON、 HfTiAlON、 HfON、 HfSiON、 HfTaON、 HfTiON中的一种或其组合， 优选为 Hf02。 栅介 质层 220的厚度可以为 2nm~4nm, 例如 2nm、 3nm或 4nm。 可以采用热氧化、 化学气相沉积、原子层沉积等工艺来形成栅介质层 220。栅金属层可以是 TaN、 TaC、 TiN、 TaAlN、 TiAIN 、 MoAIN 、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax中的一种或其组合。
[0068]在其他实施例中也可以形成热氧化的栅介质层和多晶硅栅极。
[0069]本发明提供的准纳米线晶体管及其制造方法中， 先形成源漏区， 后形 成准纳米线鳍片， 可以 ^艮好地控制栅长特性， 例如栅极长度和底部与顶部的 对准等。 另外， 本发明通过将高 k栅介质和金属栅集成到鳍型准纳米线场效 应晶体管中， 减小器件的短沟道效应， 进而有助于提高半导体器件的性能。 另外，取决于器件类型而形成的应变的源漏区根据器件类型可以向准纳米线 鳍片施加不同的应力， 从而增加沟道载流子的迁移率。
[0070]下面对本发明提供的半导体结构的优选结构进行概述。
[0071] 一种准纳米线晶体管， 包括：
[0072] SOI衬底， 包括 SOI层 130、 BOX层 120和基底层 100;
[0073]鳍片， 由 SOI层 130的一部分以及其上的至少一组硅 /硅错叠层形成；
[0074]位于鳍片两侧在鳍片的宽度方向上延伸的源漏区 110, 所述鳍片位于 延伸的源漏区形成的凹陷中， 源漏区未与鳍片相连的部分上形成有侧墙 210;
[0075】栅介质层 220, 覆盖所述鳍片；
[0076]栅金属层 230, 覆盖所述栅介质层 220。
[0077]此所述 SOI衬底为三层结构， 分别是： 基底层 100、 基底层 100之上的 BOX层 120, 以及覆盖在 BOX层 120之上的 SOI层 130。 其中， 所述 BOX层 120 的材料通常选用 Si02, BOX层 120的厚度通常大于 lOOnm; SOI层 130的材料 是单晶硅、 锗或 III- V族化合物 （如碳化硅、 砷化镓、 砷化铟或磷化铟等） ， 本具体实施方式中选用的 SOI衬底是具有 Ultrathin (超薄 ) SOI层 130的 SOI衬 底， 因此该 SOI层 130的厚度范围为 5nm~20nm, 例如 5nm, 13nm或 20nm。
[0078]源漏区 110位于 SOI层 130上， 其高度略高于第三介质层 140的上表面。 对于 PMOS器件， 所述源漏区 110材料可为 Sil cGex ( X的取值范围可为 0.15 ~ 0.75 , 可以根据工艺需要灵活调节， 如 0.15、 0.3、 0.4、 0.5或 0.75 , 本文件内 未作特殊说明处， X的取值均与此相同， 不再赘述） ； 对于 NMOS器件， 所 述源漏区 110材料可为 Si:C ( C的原子数百分比可以为 0.5% ~ 2%, 如 0.5%、 1%或 2%, C的含量可以根据工艺需要灵活调节， 本文件内未作特殊说明处， C的原子数百分比均与此相同， 不再赘述）。 应力材料源漏区 110可进一步调 节沟道区内的应力， 以提高沟道区内载流子的迁移率。
[0079]第二介质层 160位于源漏区 110上， 第二介质层 160的材料可以是 Si02。
[0080]侧墙 210位于源漏区 110两侧， 用于将源 /漏区 110于之后形成的栅极隔 离开， 因此其高度至少高于源 /漏区 110的高度。 侧墙 210可以由氮化硅、 氧化 硅、 氮氧化硅、 碳化硅及其组合， 和 /或其他合适的材料形成。 侧墙 210可以 具有多层结构。侧墙 210的厚度范围可以是 5nm~10nm,例如 5nm, 8nm, 10nm。
[0081】鳍片包括 SOI层 130和位于其上方的第一硅错层 310、 第一硅层 320、 第 二硅锗层 330、 第二硅层 340和薄氧层的第三介质层 140, 所述鳍片截面为锯 齿形状， 即各硅层被沿着 {111 }面刻蚀。 薄氧层的材料是 Si02。 其厚度在 2nm~5nm之间, 例如 2nm, 4nm, 5nm。
[0082】第一硅锗层 310和第二硅错层 330的厚度范围均为 l~3nm。 其中， 锗的 含量为整个硅锗材料的 5%~10%。 第一硅层 320和第二硅层 340的厚度范围均 为5~2011111。
[0083]栅介质层 220 (例如高 k介质层）覆盖所述鳍片。 所述高 k介质例如可 以是： HfAlON、 HfSiAlON、 HfTaAlON、 HfTiAlON、 HfON、 HfSiON、 HfTaON、 HfTiON中的一种或其组合， 优选为 Hf02。 栅介质层 220的厚度可以为 2nm~4nm, 例如 2nm、 3nm或 4nm。
[0084]栅金属层 230 (例如开启电压调节金属层）覆盖 BOX层 120、 侧墙 210 和鳍片。栅金属层 230可以 TaN、 TaC、 TiN、 TaAIN、 TiAIN 、 MoAIN 、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax中的一种或其组合。
[0085] 虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0086】此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作 为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发 出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本 发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发 明可以对它们进行应用。 因此，本发明所附权利要求旨在将这些工艺、机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种准纳米线晶体管的制造方法， 包括：
a)提供 SOI衬底， 该 SOI衬底包括基底层（100) , BOX层（ 120)和 SOI 层（ 130) ；
b)在 SOI层上形成鳍片基体， 所述鳍片基体包括至少一组硅 /硅锗叠层； c)在鳍片基体的两侧形成源漏区 （110) ；
d) 由鳍片基体以及其下的 SOI层形成准纳米线鳍片；
e)横跨所述准纳米线鳍片形成栅堆叠。
2、 根据权利要求 1所述的方法， 其中， 源漏区 （110) 为应力材料源漏 区。
3、 根据权利要求 1所述的方法， 其中， 步骤 b) 中通过沉积和刻蚀在 SOI 层上形成鳍片基体， 并且在步骤 c) 中通过外延生长形成源漏区 （110) 。
4、 根据权利要求 3所述的方法， 其中， 步骤 b) 中的刻蚀在鳍片基体两 侧的 SOI层上停止或者去除鳍片基体两侧的一部分 SOI层。
5、根据权利要求 3所述的方法， 其中当鳍型场效应晶体管为 PMOS器件， 源漏区 （110) 的材料为 SiGe, Ge元素的比例在 15%-75%的范围内。
6、根据权利要求 3所述的方法，其中当鳍型场效应晶体管为 NMOS器件， 源漏区 （110) 的材料为 SiC, C元素的比例在 0.5%-2%的范围内。
7、 根据权利要求 1所述的方法， 其中，
步骤 b) 中鳍片基体上覆盖有第一介质层（150) ；
步骤 c)在鳍片基体的长度方向上的两侧形成源漏区 （110) , 并在源漏 区上覆盖第二介质层（160) , 第二介质层的材料不同于第一介质层；
步骤 d )中由鳍片基体以及其下的 SOI层形成位于鳍片基体的长度方向上 的两侧的源漏区 （110)以及第二介质层（160)构成的凹陷中的沿所述长度 方向延伸的准纳米线鳍片； 并且在步骤 e)之前包括
步骤 f)在凹陷中暴露的 SOI层（ 130)和源漏区 （ 110) 的侧壁上形成侧 墙（210) ； 并且
步骤 e) 包括在凹陷中形成覆盖准纳米线鳍片的栅介质层（220)以及覆 盖栅介质层的栅金属层（230) 。
8、 根据权利要求 7所述的方法， 其中， 鳍片基体和第一介质层（ 150) 之间还存在第三介质层（140) 。
9、 根据权利要求 7所述的方法， 其中， 步骤 d) 包括，
在宽度方向上的特定位置覆盖沿长度方向延伸的具有一定宽度的掩模； 去除鳍片基体未被掩模覆盖的部分以及其下的 SOI层直至露出 BOX层 ( 120) ；
去除掩模， 以及掩模之下的第一介质层（150) 。
10、 根据权利要求 1所述的方法， 其中， 栅堆叠中的栅介质层（220)为 高 k介质层， 栅金属层（230) 包括开启电压调节金属。
11、 根据权利要求 7所述的方法， 其中， 步骤 e) 包括，
沉积覆盖整个半导体结构的栅介质层（220) ；
沉积覆盖栅介质层（220) 的栅金属层（230) ；
执行平坦化操作去除凹陷以外的其他区域覆盖的栅金属层（230) 。
12、 根据权利要求 7所述的方法， 其中， 步骤 f)和步骤 e)之间还包括， 对鳍片的侧壁进行刻蚀， 形成截面为锯齿形的侧壁。
13、 根据权利要求 12所述的方法， 其中， SOI层的晶向为 <100>, 其中通 过控制鳍片基体的取向， 并利用湿法刻蚀对鳍片的侧壁进行刻蚀， 形成截面 为锯齿形的侧壁。
14、 一种准纳米线晶体管， 包括：
SOI衬底， 包括 SOI层（130) 、 BOX层（120)和基底层（100) ； 鳍片， 由 SOI层（130) 的一部分以及其上的至少一组硅 /硅锗叠层形成； 位于鳍片两侧在鳍片的宽度方向上延伸的源漏区 （110) , 所述鳍片位 于延伸的源漏区形成的凹陷中， 源漏区 （110) 未与鳍片相连的部分上形成 有侧墙（210) ；
栅介质层（220) , 覆盖所述鳍片；
栅金属层（230) , 覆盖所述栅介质层（220) 。
15、 根据权利要求 14所述的准纳米线晶体管， 其中， 所述鳍片顶部覆盖 有第三介质层（140) 。
16、 根据权利要求 14所述的准纳米线晶体管， 其中， 所述源 /漏区（110 ) 覆盖有第二介质层（160 ) 。
17、 根据权利要求 12所述的准纳米线晶体管， 其中， 源漏区 （110 ) 为 应力材料源漏区。
18、 根据权利要求 17所述的准纳米线晶体管， 其中当准纳米线晶体管为 PMOS器件，应力材料源漏区（ 110 )的材料为 SiGe, Ge元素的比例在 15%-75% 的范围内。
19、 根据权利要求 14所述的准纳米线晶体管， 其中当准纳米线晶体管为 NMOS器件， 应力材料源漏区（110 )的材料为 SiC, C元素的比例在 0.5%-2% 的范围内。
20、 根据权利要求 14所述的准纳米线晶体管， 其中栅介质层（220 ) 为 高 k介质层， 栅金属层（230 ) 包括开启电压调节金属。
21、 根据权利要求 14所述的准纳米线晶体管， 其中， 所述源漏区 （110 ) 高于所述鳍片。
22、 根据权利要求 14所述的准纳米线晶体管， 其中， 鳍片的侧壁处硅层 表面的晶向为 <111>。
PCT/CN2012/085331 2012-10-23 2012-11-27 准纳米线晶体管及其制造方法 WO2014063403A1 (zh)

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