WO2014067200A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2014067200A1
WO2014067200A1 PCT/CN2012/085359 CN2012085359W WO2014067200A1 WO 2014067200 A1 WO2014067200 A1 WO 2014067200A1 CN 2012085359 W CN2012085359 W CN 2012085359W WO 2014067200 A1 WO2014067200 A1 WO 2014067200A1
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Prior art keywords
substrate
semiconductor layer
device stack
stack
region
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PCT/CN2012/085359
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English (en)
French (fr)
Inventor
朱慧珑
骆志炯
尹海洲
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中国科学院微电子研究所
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Priority to US14/439,179 priority Critical patent/US9691899B2/en
Publication of WO2014067200A1 publication Critical patent/WO2014067200A1/zh

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Definitions

  • the present invention relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • Strained silicon technology can effectively control the short channel effect.
  • MOS transistors using strained silicon as a substrate have been used, which utilize silicon germanium lattice constants different from single crystal silicon to cause the silicon germanium epitaxial layer to have a structure. Strain on the strain to form strained silicon. Since the lattice constant of the silicon germanium layer is larger than that of silicon, this Mechanical stress is generated in the channel region, causing carrier mobility to change.
  • the tensile stress can increase the electron mobility, reduce the hole mobility, and can advantageously improve the performance of the NMOS; and the compressive stress can increase the hole mobility, lower the electron mobility, and can advantageously improve the performance of the PMOS.
  • the present invention provides a semiconductor structure and a method of fabricating the same, which are advantageous in providing a good stress effect to a channel and enhancing the steepness of a source/drain region to suppress a short channel effect.
  • a method of fabricating a semiconductor structure comprising the steps of:
  • a semiconductor structure including a substrate, a support structure, a substrate region, a gate stack, a sidewall spacer, and source/drain regions, wherein:
  • the gate stack is located above the substrate region, and the substrate region is supported on the substrate by a support structure;
  • the side wall of the support structure has a cross-section
  • isolation structure below the two side edges of the substrate region, wherein a portion of the isolation structure is connected to the substrate;
  • Source/drain regions are present at least on both sides of the substrate region and the isolation structure.
  • the technical solution provided by the present invention has the following advantages: Since there is a cavity under the channel, the stress of the stress material layer on both sides of the channel can be more concentrated on the channel. , thereby effectively improving the influence of stress on the carrier mobility of the channel and enhancing the control of the channel performance; in addition, the presence of the cavity below the channel is also beneficial to enhance the steepness of the source/drain region, thereby The short channel effect is suppressed and the performance of the semiconductor device is improved.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2 is a schematic cross-sectional view of a substrate
  • FIG. 3 is a schematic cross-sectional view showing a gate stack after forming
  • FIG. 4 is a schematic cross-sectional view showing a device after stacking
  • FIG. 5 is a schematic cross-sectional view showing an etch stop layer and a second spacer after forming a side of the device stack;
  • FIG. 6 is a schematic cross-sectional view showing a groove formed on both sides of a device stack
  • FIG. 2 is a cross-sectional view of the Sigma-shaped recess in which the sidewall is apex-exposed to the device stack directly after etching; 8 is a schematic cross-sectional view showing a filling recess forming a semiconductor layer;
  • FIG. 9 is a schematic cross-sectional view showing a portion of a semiconductor layer after etching
  • FIG. 11 is a top plan view of a semiconductor layer after etching to expose a portion of the substrate and removing the photolithographic mask;
  • FIG. 11a and Fig. 1 ib are schematic cross-sectional views of the structure shown in Fig. 11 taken along line AA' and along line BB';
  • FIG. 12 is a schematic plan view of the semiconductor layer after lateral selective etching
  • 12a and 12b are cross-sectional views of the structure shown in FIG. 12 taken along line AA' and along line BB', respectively;
  • FIG. 13 is a top plan view showing the isolation structure
  • FIG. 13a and 13b are cross-sectional views of the structure of Fig. 13 taken along line AA' and along line BB', respectively;
  • FIG. 14 is a top plan view of the semiconductor layer removed after forming a cavity under the gate stack
  • 14a and 14b are respectively a cross-sectional view of the structure shown in FIG. 14 taken along line AA and along line BB';
  • FIG. 15 is a top plan view of the stressor material after being filled on both sides of the gate stack
  • 15a and 15b are schematic cross-sectional views of the structure shown in Fig. 15 taken along line AA and along line BB, respectively. detailed description
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • a semiconductor structure is provided. Please refer to FIG. 15, FIG. 15a and FIG. 15b, wherein FIG. 15 is a schematic top view of the semiconductor structure, and FIGS. 15a and 15b are respectively FIG. A cross-sectional view along the line AA and along the line BB.
  • the semiconductor structure includes a substrate 130, a support structure 131, a substrate region 100, a gate stack, sidewall spacers 240, and source/drain regions 1 13 , wherein the gate stack is over the substrate region 100
  • the base region 100 is supported on the substrate 130 by the support structure 131; the sidewall of the support structure 131 has a Sigma shape; and an isolation structure 123 exists below the two edges of the base region 100. a portion of the isolation structure 123 is coupled to the substrate 130; a cavity 112 is present between the isolation structure 123 and the support structure 131; and at least the base region 100 and the isolation structure 123 Source/drain regions 1 13 exist on both sides.
  • the material of the substrate 130 is a single crystal Si. In other embodiments, the material of the substrate 130 may also be other single crystal semiconductor materials.
  • the thickness of the substrate 130 ranges from 0.1 nm to 2 mm. In the present embodiment, the crystal orientation of the substrate 130 is ⁇ 100>.
  • the base region 100 is supported by the support structure 131 above the substrate 130.
  • a channel of the semiconductor structure is formed in the base region 100.
  • the material of the base region 100 is monocrystalline silicon. In other embodiments, the material of the base region 100 may also be other suitable semiconductor materials.
  • the thickness of the base region 100 ranges from 10 nm to 30 nm. As can be seen from Figures 15a and 15b, the base region 100 and the support structure 131 protrude from the substrate 130 and are integral with the substrate 130, which is formed by etching the substrate 130.
  • a portion of the isolation structure 123 is connected to the substrate 130, that is, there is a portion of the isolation structure 123 and the substrate 130 having a certain distance, which is not in direct contact. Due to support
  • the side wall of the structure 131 has a Sigma ( ⁇ ) shape, and the isolation structure 123 and the support structure 131 between the base region 100 and the substrate 130 enclose a cavity 112.
  • the material of the isolation structure 123 is the same as that of the substrate 130 and the substrate region 100, and is a single crystal Si. In other embodiments, the material of the isolation structure 123 may also be Other suitable semiconductor materials.
  • the gate stack includes a gate dielectric layer 102, a gate 200, and a cap layer 220.
  • the gate dielectric layer 102 is located above the substrate region 100
  • the gate electrode 200 is located above the gate dielectric layer 102
  • the cap layer 220 is located above the gate electrode 200 for protecting the gate electrode 200. Not damaged in subsequent steps.
  • the material of the gate electrode 200 may be selected from the group consisting of Poly-Si, Ti, Co, Ni, Al, W, alloy, metal silicide, and combinations thereof.
  • the gate dielectric layer 102 may be a thermal oxide layer, including silicon oxide, silicon oxynitride, or a high-k dielectric such as Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO or a combination thereof, the gate dielectric layer 102 may have a thickness of 2 nm to 10 nm, for example, 5 nm or 8 nm.
  • the cap layer 220 may be selected from silicon nitride and has a thickness ranging from 10 nm to 40 nm, such as 10 nm or 20 nm.
  • Sidewalls 240 surround the sidewalls of the gate dielectric layer 102, the gate 200, and the cap layer 220.
  • the material of the first side wall 240 includes one of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the first side wall 240 may have a single layer structure or a multilayer structure.
  • the thickness of the first sidewall 240 ranges from 10 nm to 100 nm, such as 30 ⁇ , 50 ⁇ or 80 ⁇ .
  • the source/drain regions 113 are located on both sides of the gate stack with the sidewall spacers 240, the substrate region 100, and the isolation structure 123.
  • the upper surface of the source/drain regions 113 is preferably higher than the bottom of the gate stack or flush with the bottom of the gate stack.
  • the material of the source/drain region 113 is boron - doped Si 1-x Ge x , and the value of X ranges from 0.1 to 0.7, such as 0.2, 0.3, 0.4, 0.5 or 0.6;
  • the material of the source/drain region 1 13 is Si:C doped with phosphorus or arsenic, and the atomic percentage of C ranges from 0.2% to 2%, such as 0.5%, 1% or 1.5%.
  • the presence of the stress material silicon germanium or silicon carbon facilitates further adjustment of stress in the channel region to increase carrier mobility in the channel region.
  • the PFET device has an N-type ultra-steep recessed well structure, and for the NFET device, it has a P-type ultra-steep back-off well structure.
  • the semiconductor structure provided by the present invention further includes a source/drain extension region 150 located in a portion of the substrate region 100 adjacent to the source/drain regions.
  • the semiconductor structure provided by the present invention has the following advantages: Since there is a cavity under the channel, the stress of silicon germanium or silicon carbon on both sides of the channel can be more concentrated on the channel, thereby effectively improving the efficiency.
  • the effect of stress on the carrier mobility of the channel enhances the control of the channel performance; in addition, the presence of the cavity below the channel is also beneficial to enhance the steepness of the source/drain region, thereby suppressing the short channel effect. Improve the performance of semiconductor devices.
  • a method of fabricating a semiconductor structure is also provided.
  • a method of forming a semiconductor structure of Fig. 1 will be specifically described by way of an embodiment of the present invention with reference to Figs. 2 to 15b.
  • the manufacturing method provided by the present invention comprises the following steps:
  • step S101 a substrate 130 is provided on which a gate stack and a first spacer 240 surrounding the gate stack are formed.
  • a substrate 130 is provided.
  • the material of the substrate 130 is a single crystal Si.
  • the material of the substrate 130 may also be other single crystal semiconductor materials.
  • the crystal orientation of the substrate 130 is ⁇ 100>. This will facilitate anisotropic etching as described below.
  • the substrate 130 has a thickness ranging from 0.1 nm to 2 mm.
  • an isolation region such as a shallow trench isolation (STI) structure 120, is formed in the substrate 130 to electrically isolate the continuous semiconductor device.
  • STI shallow trench isolation
  • a gate stack composed of a gate dielectric layer 102, a gate electrode 200, and a cap layer 220 is formed over the substrate 130.
  • the gate dielectric layer 102 is located on the substrate 130, the gate electrode 200 is located above the gate dielectric layer 102, and the cap layer 220 is located above the gate electrode 200 for protecting the gate electrode 200.
  • the subsequent steps are not destroyed.
  • the material of the gate electrode 200 may be selected from the group consisting of Poly-Si, Ti, Co, Ni, Al, W, alloy, metal silicide, and combinations thereof.
  • the gate dielectric layer 102 may be a thermal oxide layer, including silicon oxide, silicon oxynitride, or a high-k dielectric such as Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO or a combination thereof, the gate dielectric layer 102 may have a thickness of 2 nm to 10 nm, for example, 5 nm or 8 nm.
  • the cap layer 220 may be a nitride of shigui, and has a thickness ranging from 10 nm to 40 nm, such as lOnm or 20 nm.
  • the surface of the substrate 130 on either side of the gate stack is lightly doped to form source/drain extension regions 150.
  • a P-type impurity such as boron and indium is doped into the substrate 130
  • an N-type impurity such as arsenic and phosphorus is doped into the substrate 130.
  • the material of the first side wall 240 includes one of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the first side wall 240 may have a single layer structure or a multilayer structure.
  • the thickness of the first side wall 240 ranges from 10 nm to 100 nm, such as 30 ⁇ , 50 ⁇ or 80 ⁇ .
  • step S102 portions of the substrate 130 on both sides of the gate stack are removed to form a device stack.
  • a portion of the substrate 130 on both sides of the gate stack is etched by using a gate stack with a first spacer 240 as a mask, and a base region 100 is formed under the gate stack.
  • the substrate region 100 and the gate stack thereon and the first spacer 240 are the same as the device stack.
  • the etching depth ranges from 10 nm to 30 nm.
  • the etching is preferably dry etching, and the dry etching method includes plasma etching, ion milling, reverse sputtering, reactive ion etching, and in the present embodiment, reactive ion etching is employed.
  • step S103 a second spacer 260 is formed on the sidewall of the device stack.
  • a first insulating layer (not shown) is deposited over the entire semiconductor structure, and then a second insulating layer (not shown) is deposited on the first insulating layer.
  • the second insulating layer and the first insulating layer are etched to form an etch stop layer 250 surrounding the device stack, and a sidewall spacer 260 surrounding the etch stop layer 250 (hereinafter referred to as the second spacer 260) ).
  • the material of the second spacer 260 includes one of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials, and the thickness ranges from 5 nm to 10 nm.
  • the material of the etch stop layer 250 is preferably an insulating material different from the first sidewall 240 and the second spacer 260.
  • the material of the first sidewall 240 and the second spacer 260 is silicon nitride.
  • the material of the etch stop layer 250 is silicon oxide.
  • the etch stop layer 250 has a thickness ranging from 1 nm to 3 nm.
  • step S104 the substrate 130 on both sides of the device stack is etched using the device stack with the second spacer 260 as a mask to form trenches 160 on both sides of the device stack and
  • the device structure is stacked under the support structure 131, wherein the sidewall of the trench 160 is doped in a meander shape by controlled etching, and the apex of the dome protrudes directly below the device stack.
  • a portion of the substrate 130 on both sides of the device stack is anisotropically applied by using a device stack with a second spacer 260 as a mask.
  • Etching is performed to form recesses 160 on either side of the device stack, and support structures 131 below the substrate region 100.
  • the etching method is preferably dry etching RIE.
  • the bottom surface of the groove 160 and the sidewalls of the groove 160 and the support structure 131 are etched by anisotropic wet etching selective to the crystal orientation, so that The sidewall of the recess 160 has a cross-section that is convex, and the apex of the dome protrudes directly below the device stack.
  • the crystal orientation of the substrate 130 is ⁇ 100>
  • the etching solution of the wet etching may be potassium hydroxide (KOH), tetradecyl ammonium hydroxide (TMAH) or ethylenediamine-neighbor.
  • KOH potassium hydroxide
  • TMAH tetradecyl ammonium hydroxide
  • the concentration of the etching solution is 5 to 40% by mass, and the reaction temperature is 40 to 90 ° C.
  • the etching liquid such as KOH and TMAH has anisotropy against single crystal Si corrosion
  • the ratio of the corrosion rate of the ⁇ 111 ⁇ crystal plane to the etching rate of other crystal planes is about 1:100, so the basic plane of ⁇ 1 11 ⁇ is basically Not corrosive.
  • the sidewalls of the groove 160 are all etch stop surfaces, and the crystal faces are ⁇ 1 11 ⁇ . Therefore, by anisotropic etching, the side wall of the groove is formed in a meander shape, and the apex of the meander shape protrudes directly below the device stack, and correspondingly, the side wall of the support structure 131 has a concave Sigma shape.
  • the wet etching causes the groove 160 to become deep.
  • step S105 a first semiconductor layer 110 filling the recess is formed.
  • the grooves on both sides of the device stack with the second spacer 260 are filled by selective epitaxial growth to form a semiconductor layer 1 10 (hereinafter referred to as first The semiconductor layer 110 is shown).
  • the material of the first semiconductor layer 110 is SiGe, wherein the Ge element ratio is between 10% and 20%.
  • the upper surface of the first semiconductor layer 110 is not lower than the lower surface of the etch stop layer 250.
  • the sidewall of the recess 160 has a dome shape, the apex of the dome protrudes directly below the device stack, and the selectively epitaxially grown first semiconductor layer 10 protrudes to the device stack. Below. [0060]
  • steps S106 portions of the first semiconductor layer 110 on both sides of the device stack are removed, and a first semiconductor layer 110 of a certain thickness is retained.
  • the first semiconductor on both sides of the second spacer 260 is used, for example, by dry etching, by using a device stack with a second spacer 260 as a mask.
  • Layer 110 is etched.
  • the first semiconductor layer 110 is not completely removed, but a certain thickness of the first semiconductor layer 110 remains on both sides of the second spacer 260.
  • the etching selected is substantially anisotropic (substantially only in the vertical direction), the portion of the first semiconductor layer 10 projecting directly below the device stack is retained.
  • step S107 in a partial region in the width direction of the device stack, the first semiconductor layer 110 on both sides of the device stack is removed to expose the substrate 130.
  • the above width is defined on the basis of the channel on which the semiconductor device is to be formed.
  • the direction of the current in the channel is the longitudinal direction, and the direction perpendicular thereto is the width direction. That is, in Fig. 10, the left and right directions are the longitudinal directions, and the direction perpendicular to the paper surface is the width direction.
  • a photolithography mask 300 is formed on the semiconductor structure to cover the intermediate portion to expose the end region in the width direction of the semiconductor structure, so that in the subsequent step, The first semiconductor layer 110 under the photolithography mask 300 is not etched away.
  • the material of the photolithography mask 300 may be a photoresist, an organic polymer, silicon oxide, silicon nitride, borosilicate glass, borophosphosilicate glass, and combinations thereof.
  • the method of forming the photolithography mask 300 is a process familiar to those skilled in the art. For the sake of clarity, we will not repeat them here.
  • the function of the photolithography mask 300 is to protect a portion of the first semiconductor layer 110 on both sides of the gate stack in the intermediate portion in the width direction of the semiconductor structure. That is, after etching the first semiconductor layer 110 which is not covered by the photomask 300 in the subsequent step, a portion of the first semiconductor layer 110 is present on both sides of the gate stack which is located at the intermediate portion in the width direction of the semiconductor structure.
  • the position of the photolithography mask 300 in the present invention is not limited to the position shown in FIG. 10, and any of the portions on the device stack may be covered in a partial region in the width direction of the semiconductor structure.
  • the lithographic mask 300 of the first semiconductor layer 110 is suitable for use in the fabrication method provided by the present invention, and is not described here.
  • the photolithographic mask 300 and the device stack with the second spacer 260 are used as a mask, and the substrate 130 is used as an etch stop layer for the width direction of the device stack.
  • the first semiconductor layer outside the gate stack and the second spacer 260 1 10 is etched until the substrate 130 is exposed.
  • the photolithography mask 300 is removed. Please refer to FIG. 1 1 , FIG. 11a and FIG. 1 ib , wherein FIG. 11 is a top plan view after etching the first semiconductor layer 110 to expose a portion of the substrate and removing the photolithography mask 300, FIG. 11a and FIG.
  • FIG. 11a In the intermediate portion in the width direction of the semiconductor structure, the first semiconductor layer 110 on both sides of the second spacer 260 and covered by the photolithography mask 300 is retained, and in the semiconductor Of the two end regions in the width direction of the structure, the first semiconductor layer 110 on both sides of the second spacer 260 and not covered by the photolithography mask 300 is removed, and the lining underneath is exposed
  • the bottom 130 is as shown in Figure l ib. Since the etching selected is substantially anisotropic (substantially only in the vertical direction), the portion of the first semiconductor layer 110 that protrudes directly below the device stack is retained.
  • step S108 in the partial region in the width direction of the device stack, an isolation structure 123 connecting the substrates is formed under the second spacer 260 and both side edges of the device stack.
  • FIG. 12 is a schematic top view of the first semiconductor layer 110 after lateral selective etching
  • FIG. 12a and FIG. 12b are respectively FIG. A cross-sectional view along the line AA, and along the line BB.
  • the first semiconductor layer 110 under the gate stack and the second spacer 260 is etched back, and the lateral etching depth is slightly larger than the second spacer 260 and the etch stop layer 250 by controlling the etching time. The sum of the thicknesses.
  • FIG. 13 is a schematic plan view showing the isolation structure
  • FIG. 13a and FIG. 13b are respectively along the line AA' and along the line of FIG. BB, a schematic cross-sectional view.
  • a second semiconductor layer (not shown) is formed on the upper surface of the exposed substrate 130 and the upper surface and sidewalls of the first semiconductor layer 110 by, for example, epitaxial growth, and through anisotropy
  • the etching method (for example, RIE, which is substantially only etched in the vertical direction) removes the upper surface of the exposed substrate 130 and the second semiconductor layer on the upper surface of the first semiconductor layer 110, while retaining the second side Wall 260 under device stack
  • a second semiconductor layer (mainly below the second spacer 260) is formed to form the isolation structure 123. In the lateral direction, the isolation structure 123 is located substantially below the second sidewall spacer 260 and the side edges of the device stack.
  • the material of the isolation structure 123 is monocrystalline silicon.
  • the material of the isolation structure 123 may be other semiconductor materials different from the first semiconductor layer 110.
  • the first semiconductor layer 110 is not completely etched under the protection of the photolithography mask 300 (please refer to FIG. 10) due to the intermediate portion in the width direction of the semiconductor structure.
  • the isolation structure 123 is formed on the sidewall of the first semiconductor layer 110 previously covered by the photolithography mask 300, the isolation structure 123 is formed over the first semiconductor layer 110, that is, The first semiconductor layer 110 is present between the isolation structure 123 and the substrate 130; and as shown in FIG.
  • the isolation structure 123 is formed by the two end regions in the width direction of the semiconductor structure as an example in the present embodiment, those skilled in the art should understand that the specific position of the isolation structure 123 is not limited thereto. For example, those skilled in the art can understand that the isolation structure 123 can be located at any position in the width direction of the semiconductor structure as long as it is connected to the substrate and can be subsequently formed to form a cavity. Let me repeat. As shown, there is a portion between the isolation structure 123 and the support structure 131 that is not etched away, and the first semiconductor layer 110 protrudes directly below the device stack.
  • step S109 the remaining first semiconductor layer 110 is removed, and a cavity 112 is formed between the support structure 131 and the isolation structure 123.
  • FIG. 14 is a top plan view of the first semiconductor layer 110 after the cavity 112 is formed under the gate stack
  • FIGS. 14a and 14b are respectively a view.
  • the remaining first semiconductor layer 110 is selectively removed by wet etching, and formed between the support structure 131 and the isolation structure 123 under the gate stack.
  • the cavity 112 is originally filled with a portion of the first semiconductor layer 110 that protrudes directly below the device stack.
  • the material of the first semiconductor layer 110 is different from the substrate 130 and the support structure 131, the material of the base region 100 and the isolation structure 123, so by selecting the corresponding etching solution, only the remaining first semiconductor layer 1 10 can be removed.
  • the etching solution first etches the first semiconductor layer 110 outside the isolation structure 123, and then removes the first semiconductor layer 110 between the isolation structure 123 located at the intermediate portion in the width direction of the semiconductor structure and the substrate 130, which In the middle portion of the width direction of the semiconductor structure, in the isolation structure
  • a gap is formed between the 123 and the substrate 130, through which the etching solution continues to etch the first semiconductor layer 110 under the gate stack until all of the first semiconductor layer 110 is completely removed, thereby supporting under the gate stack
  • a cavity 112 is formed between the structure 131 and the isolation structure 123.
  • the isolation structure 123 and the substrate A gap is formed between 130, and as shown in FIG. 14b, the isolation structure 123 and the substrate 130 are connected to a region where the first semiconductor layer 110 is not present between the isolation structure 123 and the substrate 130.
  • step S110 the second spacer 260 is removed and source/drain regions are formed on both sides of the device stack.
  • FIG. 15 is a top plan view after the stress material is filled on both sides of the gate stack
  • FIG. 15a and FIG. 15b are respectively the cross-section of FIG. A cross-sectional view of line AA, and along line BB.
  • the etch stop layer 250 is used as an etch stop layer
  • the second sidewall spacer 260 is removed by dry etching
  • the first sidewall spacer 240 is used as an etch stop layer
  • the dry layer is continuously used.
  • the upper surface of 13 is preferably higher than the bottom of the gate stack or flush with the bottom of the gate stack. Due to the presence of the isolation structure 123, the stress material is substantially present outside of the isolation structure 123, thereby ensuring that the cavity 12 is not filled. As shown in FIG. 15a, in the region where the isolation structure 123 does not directly contact the substrate 130, since there is a certain gap between the isolation structure 123 and the substrate 130, a small amount of stress material enters from the gap.
  • the method of forming the source/drain regions 113 is preferably epitaxial growth.
  • the material of the source/drain region 113 is boron doped Silc Ge x , and the value of X ranges from 0.1 to 0.7, such as 0.2, 0.3, 0.4, 0.5 or 0.6;
  • the The material of the source/drain region 113 is Si:C doped with phosphorus or arsenic, and the atomic percentage of C ranges from 0.2% to 2%, such as 0.5%, 1% or 1.5%.
  • the presence of the stress material silicon germanium or silicon carbon facilitates further adjustment of stress in the channel region to increase carrier mobility in the channel region.
  • an N-type ultra-steep back-off well is formed after filling the doped stress material; for the NFET device, a P-type ultra-steep back-off well is formed after filling the doped stress material.
  • the present invention has the following advantages: Since there is a cavity under the channel, the stress of the stress material layer on both sides of the channel can be more concentrated on the channel, thereby effectively lifting The influence of stress on the carrier mobility of the channel enhances the control of the channel performance. In addition, the presence of the cavity below the channel is also beneficial to enhance the steepness of the source/drain region, thereby suppressing the short channel effect. , improve the performance of semiconductor devices.

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Abstract

提供了一种半导体结构，包括衬底（130）、支撑结构（131）、基底区（100）、栅堆叠、侧墙（240）以及源/漏区，其中，所述栅堆叠位于所述基底区（100）之上，所述基底区（100）由支撑结构（131）支撑于所述衬底（130）之上，其中：所述支撑结构（131）的侧壁截面为∑形；在所述基底区（100）两侧边缘下方存在隔离结构（123），其中，部分所述隔离结构（123）与所述衬底（130）相连接；在所述隔离结构（123）和所述支撑结构（131）之间存在空腔（112）；以及至少在所述基底区（100）和隔离结构（123）的两侧存在源/漏区。相应地，还提供了该半导体结构的制造方法。

Description

半导体结构及其制造方法
[0001]本申请要求了 2012年 11月 2日提交的、申请号为 201210432008.6、 发明名称为"半导体结构及其制造方法"的中国专利申请的优先权，其全部 内容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体技术领域，尤其涉及一种半导体结构及其制造方 法。 背景技术
[0003】工业需求要求 IC电路具有更高的密度并由此减小 MOS 晶体管的 尺寸。 然而， MOS晶体管的缩小导致了两个众所周知的寄生效应的出现， 即， 随着栅极长度的减小而出现的短沟道效应和漏致势垒降低效应， 易 于恶化器件的电学性能， 如造成栅极阈值电压下降、 功耗增加以及信噪 比下降等问题。 从物理上， 上述效应可以解释为： 当晶体管关断时 (栅极 电压为零）， 非常小的器件中的源 /漏区的静电影响或在沟道区上向漏极施 加的电压降低了沟道中电子或空穴的能量势垒， 并且导致较高的关断电 流。
[0004】为了控制短沟道效应，人们不得不向沟道中掺杂更多的磷、硼等杂 质元素， 但此举易导致器件沟道中载流子迁移率下降； 而且用来向沟道 中掺杂杂质的分布也存在很难控制陡度的问题， 容易造成严重的短沟道 效应； 栅极氧化物介质的厚度方面也将出现发展瓶颈问题， 栅极氧化物 厚度减薄的速度已经很难再跟上栅极宽度缩小的步伐， 栅介质漏电越来 越大； 关键尺寸不断缩小， 易于导致源漏区电阻的不断增大和器件的功 耗越来越大。
[0005]应变硅技术可以有效地控制短沟道效应，已有使用应变硅作为衬底 的 MOS晶体管， 其利用硅锗的晶格常数与单晶硅不同的特性， 使硅锗外 延层产生结构上应变而形成应变硅。 由于硅锗层的晶格常数比硅大， 这 使得沟道区中产生机械应力， 而造成载流子移动性改变。 在 FET中， 拉 应力能够提高电子迁移率， 降低空穴迁移率， 可以有利地提高 NMOS的 性能； 而压应力可以提高空穴迁移率， 降低电子迁移率， 可以有利地提 高 PMOS的性能。
[0006】但是，传统的硅锗应变硅技术也开始面临瓶颈，很难再为沟道提供 更强的应变， 无法有效提升半导体器件的工作性能。 发明内容
[0007】为了解决上述问题， 本发明提供了一种半导体结构及其制造方法， 利于向沟道提供良好的应力效果， 以及利于增强源 /漏区的陡直性以此抑 制短沟道效应。
[0008】根据本发明的一个方面，提供了一种半导体结构的制造方法， 该制 造方法包括以下步骤：
a) 提供衬底， 在该衬底之上形成栅堆叠以及围绕该栅堆叠的第一侧墙； b) 去除位于所述栅堆叠两侧的部分所述衬底， 形成器件堆叠；
c) 在所述器件堆叠的侧壁上形成第二侧墙；
d) 以带有第二侧墙的器件堆叠为掩模刻蚀位于所述器件堆叠两侧的衬 底， 形成位于器件堆叠两侧的 槽以及在所述器件堆叠下方的支撑结构， 其中通过控制刻蚀使得所述 槽的侧壁截面为∑形， 该∑形的顶点凸出至 器件堆叠正下方；
e) 形成填充所述 槽的第一半导体层；
f) 去除位于所述器件堆叠两侧的部分所述第一半导体层， 保留一定厚度 的第一半导体层；
g) 在所述器件堆叠的宽度方向上的部分区域中， 去除位于所述器件堆叠 两侧的所述第一半导体层， 以暴露所述衬底；
h) 在所述器件堆叠的宽度方向上的所述部分区域中， 在第二侧墙以及器 件堆叠的两侧边缘下方形成连接衬底的隔离结构；
i) 去除剩余的所述第一半导体层， 在所述支撑结构和所述隔离结构之间 形成空腔； j) 去除第二侧墙， 并在所述器件堆叠的两侧形成源 /漏区。
[0009】根据本发明的另一个方面， 还提供了一种半导体结构， 包括衬底、 支撑结构、 基底区、 栅堆叠、 侧墙以及源 /漏区， 其中：
[0010]所述栅堆叠位于所述基底区之上，所述基底区由支撑结构支撑于所 述衬底之上；
[0011】所述支撑结构的侧壁截面为∑形；
[0012】在所述基底区两侧边缘下方存在隔离结构， 其中， 部分所述隔离结 构与所述衬底相连接；
[0013]在所述隔离结构和所述支撑结构之间存在空腔； 以及
[0014]至少在所述基底区和隔离结构的两侧存在源 /漏区。
[0015】与现有技术相比， 采用本发明提供的技术方案具有如下优点： 由于 沟道下方存在空腔， 所以位于沟道两侧的应力材料层的应力可以更为集 中地作用于沟道， 从而有效地提升了应力对沟道载流子迁移率的影响， 增强对沟道性能的控制作用； 此外， 沟道下方空腔的存在还有利于增强 源 /漏区的陡直性， 从而抑制短沟道效应， 提高半导体器件的性能。 附图说明
[0016]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本发明的其它特征、 目的和优点将会变得更明显。
[0017]图 1为根据本发明的半导体结构制造方法的流程图；
[0018]图 2为衬底的剖面示意图；
[0019]图 3为形成栅堆叠后的剖面示意图；
[0020]图 4为形成器件堆叠后的剖面示意图；
[0021】图 5 为在器件堆叠的侧面形成刻蚀停止层以及第二侧墙后的剖面 示意图；
[0022]图 6为在器件堆叠的两侧形成 槽后的剖面示意图；
[0023】图 Ί 为继续刻蚀形成侧壁为顶点凸出至器件堆叠正下方的 Sigma 形凹槽后的剖面示意图； [0024]图 8为填充凹槽形成半导体层后的剖面示意图；
[0025]图 9为刻蚀部分半导体层后的剖面示意图；
[0026]图 10为覆盖光刻掩模后的俯视示意图；
[0027]图 1 1为刻蚀半导体层以暴露部分衬底并去除光刻掩模后的俯视示 意图；
[0028】图 11a和图 l ib分别为图 11所示结构沿剖线 AA'和沿剖线 BB'的 剖视示意图；
[0029]图 12为对半导体层进行横向选择性腐蚀后的俯视示意图；
[0030]图 12a和图 12b分别为图 12所示结构沿剖线 AA'和沿剖线 BB'的 剖视示意图；
[0031]图 13为形成隔离结构后的俯视示意图；
[0032】图 13a和图 13b分别为图 13所示结构沿剖线 AA'和沿剖线 BB'的 剖视示意图；
[0033】图 14 为去除半导体层在所述栅堆叠下方形成空腔后的俯视示意 图；
[0034]图 14a和图 14b分别为图 14所示结构沿剖线 AA，和沿剖线 BB'的 剖视示意图；
[0035】图 15为在栅堆叠的两侧填充应力材料后的俯视示意图； 以及
[0036】图 15a和图 15b分别为图 15所示结构沿剖线 AA，和沿剖线 BB，的 剖视示意图。 具体实施方式
[0037]下面详细描述本发明的实施例。
[0038]所述实施例的示例在附图中示出，其中自始至终相同或类似的标号 表示相同或类似的元件或具有相同或类似功能的元件。 下面通过参考附 图描述的实施例是示例性的， 仅用于解释本发明， 而不能解释为对本发 明的限制。 下文的公开提供了许多不同的实施例或例子用来实现本发明 的不同结构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置 进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了筒化 和清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此外， 本发明提供了的各种特定的工艺和材料的例子， 但是本领域普通 技术人员可以意识到其他工艺的可应用于性和 /或其他材料的使用。另外， 以下描述的第一特征在第二特征之 "上"的结构可以包括第一和第二特征 形成为直接接触的实施例， 也可以包括另外的特征形成在第一和第二特 征之间的实施例， 这样第一和第二特征可能不是直接接触。
[0039】根据本发明的一个方面， 提供了一种半导体结构， 请参考图 15、 图 15a和图 15b, 其中， 图 15为该半导体结构的俯视示意图， 图 15a和 图 15b分别为图 15的沿剖线 AA，和沿剖线 BB，的剖视示意图。如图所示， 所述半导体结构包括衬底 130、 支撑结构 131、 基底区 100、 栅堆叠、 侧 墙 240以及源 /漏区 1 13 , 其中， 所述栅堆叠位于所述基底区 100之上， 所述基底区 100由支撑结构 131支撑于所述衬底 130之上； 所述支撑结 构 131的侧壁截面为 Sigma (∑)形状； 在所述基底区 100两侧边缘下方存 在隔离结构 123 , 其中， 部分所述隔离结构 123与所述衬底 130相连接； 在所述隔离结构 123和所述支撑结构 131之间存在空腔 112; 以及至少在 所述基底区 100和隔离结构 123的两侧存在源 /漏区 1 13。
[0040】具体地， 在本实施例中， 所述衬底 130 的材料为单晶 Si, 在其他 实施例中， 所述衬底 130 的材料还可以是其他单晶半导体材料。 所述衬 底 130 的厚度范围为 0.1nm-2mm。 在本实施例中， 衬底 130 的晶向为 <100>。
[0041】基底区 100由支撑结构 131支撑于衬底 130上方。半导体结构的沟 道形成于所述基底区 100 中。 在本实施例中， 所述基底区 100的材料为 单晶硅， 在其他实施例中， 所述基底区 100 的材料还可以是其他合适半 导体材料。 所述基底区 100的厚度范围为 10nm-30nm。 从图 15a和图 15b 可以看出， 基底区 100和支撑结构 131 突出于所述衬底 130上并与衬底 130是一体的， 是通过刻蚀所述衬底 130形成的。
[0042】部分隔离结构 123与所述衬底 130连接， 即，存在部分所述隔离结 构 123和所述衬底 130之间具有一定的距离， 并非直接接触。 由于支撑 结构 131的侧壁截面为 Sigma (∑)形状， 隔离结构 123与位于基底区 100 和衬底 130之间的支撑结构 131围成空腔 112。 在本实施例中， 所述隔离 结构 123的材料与所述衬底 130和所述基底区 100的材料相同， 为单晶 Si, 在其他实施例中， 所述隔离结构 123的材料还可以是其他合适半导体 材料。
[0043】所述栅堆叠包括栅介质层 102、 栅极 200、 以及帽层 220。 其中， 所述栅介质层 102位于基底区 100之上， 所述栅极 200位于所述栅介质 层 102之上， 所述帽层 220位于所述栅极 200的上方， 用以保护栅极 200 在后续的步骤中不受到破坏。 所述栅极 200的材料可以选用 Poly-Si、 Ti、 Co、 Ni、 Al、 W、 合金、 金属硅化物及其组合。 所述栅介质层 102 其可 以是热氧化层， 包括氧化硅、 氮氧化硅， 也可为高 K介质， 例如 Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO , A1203、 La203、 Zr02、 LaAlO 中的一种或其组合，栅介质层 102的厚度可以为 2nm-10nm, 例如 5nm或 8nm。 所述帽层 220可以选用硅的氮化物， 厚度范围为 10nm-40nm, 例如 10nm或 20nm。 侧墙 240 (文中也称为"第一侧墙" )环绕在所述栅介质层 102、 栅极 200和帽层 220的侧壁上。 第一侧墙 240的材料包括氮化硅、 氧化硅、 氮氧化硅、 碳化硅中的一种及其组合， 和 /或其他合适的材料形 成。 第一侧墙 240 可以是单层结构， 也可以具有多层结构。 所述第一侧 墙 240的厚度范围为 lOnm-lOOnm, 如 30匪、 50匪或 80匪。
[0044]源 /漏区 113位于带有侧墙 240的栅堆叠、 基底区 100和隔离结构 123 的两侧。 源 /漏区 113 的上表面优选高于所述栅堆叠的底部或者与所 述栅堆叠的底部齐平。 其中， 对于 PFET器件， 所述源 /漏区 113的材料 为掺杂硼的 Si1-xGex, X的取值范围为 0.1 - 0.7, 如 0.2、 0.3、 0.4、 0.5 或 0.6; 对于 NFET器件， 所述源 /漏区 1 13的材料为掺杂磷或砷的 Si:C, C的原子数百分比的取值范围为 0.2% ~ 2%, 如 0.5%、 1%或 1.5%。 应力 材料硅锗或硅碳的存在利于进一步调节沟道区内的应力， 以提高沟道区 内载流子的迁移率。 此外， 由于应力材料硅锗或硅碳的存在， 所以， 对 于 PFET器件来说， 使其具有 N型超陡后退阱结构， 对于 NFET器件来 说， 使其具有 P型超陡后退阱结构。 [0045】优选地， 本发明所提供的半导体结构还包括源 /漏延伸区 150 ,位于 所述基底区 100中靠近所述源 /漏区的部分。
[0046]本发明提供的半导体结构具有以下优点： 由于沟道下方存在空腔， 所以位于沟道两侧的硅锗或硅碳的应力可以更为集中地作用于沟道， 从 而有效地提升了应力对沟道载流子迁移率的影响， 增强对沟道性能的控 制作用； 此外， 沟道下方空腔的存在还有利于增强源 /漏区的陡直性， 从 而抑制短沟道效应， 提高半导体器件的性能。
[0047】根据本发明的另一个方面， 还提供了一种半导体结构的制造方法。 下面， 将结合图 2至图 15b通过本发明的一个实施例对图 1形成半导体 结构的方法进行具体描述。 如图 1 所示， 本发明所提供的制造方法包括 以下步骤：
[0048】在步骤 S 101 中， 提供衬底 130, 在该衬底 130上形成栅堆叠以及 围绕该栅堆叠的第一侧墙 240。
[0049】具体地， 如图 2所示， 首先， 提供衬底 130, 在本实施例中， 所述 衬底 130的材料为单晶 Si。 在其他实施例中， 所述衬底 130的材料还可 以是其他单晶半导体材料。 在本实施例中， 衬底 130的晶向为<100>。 如 下文所述， 这将便于对其进行各向异性刻蚀。 所述衬底 130 的厚度范围 为 0.1nm-2mm。 典型地， 在所述衬底 130中形成隔离区， 例如浅沟槽隔 离（STI)结构 120, 以便电隔离连续的半导体器件。
[0050】接着， 如图 3所示， 在所述衬底 130之上形成由栅介质层 102、 栅 极 200 以及帽层 220所构成的栅堆叠。 其中， 所述栅介质层 102位于衬 底 130上， 所述栅极 200位于所述栅介质层 102之上， 所述帽层 220位 于所述栅极 200的上方， 用以保护栅极 200在后续的步骤中不受到破坏。 其中， 所述栅极 200的材料可以选用 Poly-Si、 Ti、 Co、 Ni、 Al、 W、 合 金、 金属硅化物及其组合。 所述栅介质层 102 其可以是热氧化层， 包括 氧化硅、氮氧化硅，也可为高 K介质，例如 Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO, A1203、 La203、 Zr02、 LaAlO 中的一种或其组合， 栅介 质层 102的厚度可以为 2nm-10nm, 例如 5nm或 8nm。所述帽层 220可以 选用石圭的氮化物， 厚度范围为 10nm-40nm, 例如 lOnm或 20nm。 形成栅 堆叠后， 对位于栅堆叠两侧的所述衬底 130 的表面进行轻掺杂， 用以形 成源 /漏延伸区 150。 对于 PFET器件， 向所述衬底 130中掺杂 P型杂质， 例如硼和铟， 对于 NFET器件， 向所述衬底 130中掺杂 N型杂质， 例如 砷和磷。 源 /漏延伸区 150形成后， 形成环绕在所述栅介质层 102、 栅极 200和帽层 220的侧壁上的第一侧墙 240。 第一侧墙 240的材料包括氮化 硅、 氧化硅、 氮氧化硅、 碳化硅中的一种及其组合， 和 /或其他合适的材 料形成。 第一侧墙 240 可以是单层结构， 也可以具有多层结构。 第一侧 墙 240的厚度范围为 lOnm-lOOnm, 如 30匪、 50匪或 80匪。
[0051】在步骤 S 102 中， 去除位于所述栅堆叠两侧的部分所述衬底 130, 形成器件堆叠。
[0052】具体地， 如图 4所示， 以带有第一侧墙 240的栅堆叠为掩模刻蚀去 除所述栅堆叠两侧的部分衬底 130 , 在栅堆叠下方形成基底区 100。 基底 区 100和其上的栅堆叠以及第一侧墙 240—同构成器件堆叠。 在本实施 例中， 刻蚀深度的范围为 10nm-30nm。 刻蚀优选为干法刻蚀， 所述干法 刻蚀的方法包括等离子体刻蚀、 离子铣、 反溅射、 反应离子刻蚀， 在本 实施例中， 采用反应离子刻蚀。
[0053】在步骤 S103中， 在所述器件堆叠的侧壁上形成第二侧墙 260。
[0054】具体地， 如图 5所示， 首先， 在整个半导体结构上沉积第一绝缘层 (未示出）， 然后在所述第一绝缘层上沉积第二绝缘层 (未示出）。 接着， 对 第二绝缘层和第一绝缘层进行刻蚀， 以形成环绕器件堆叠的刻蚀停止层 250、以及环绕该刻蚀停止层 250的侧墙 260(下文中以第二侧墙 260表示）。 其中， 所述第二侧墙 260 的材料包括氮化硅、 氧化硅、 氮氧化硅、 碳化 硅中的一种及其组合， 和 /或其他合适的材料， 其厚度范围在 5nm-10nm, 所述刻蚀停止层 250的材料优选为不同于所述第一侧墙 240和第二侧墙 260的绝缘材料， 例如， 所述第一侧墙 240和第二侧墙 260的材料为氮化 硅， 而所述刻蚀停止层 250的材料为氧化硅。 所述刻蚀停止层 250的厚 度范围为 lnm-3nm。
[0055]在步骤 S 104中， 以带有第二侧墙 260的器件堆叠为掩模刻蚀位于 所述器件堆叠两侧的衬底 130,形成位于器件堆叠两侧的 槽 160以及在 所述器件堆叠下方的支撑结构 131 ,其中通过控制刻蚀使得 槽 160的侧 壁截面为∑形， 该∑形的顶点凸出至器件堆叠正下方。
[0056】具体地， 首先， 如图 6所示， 以带有第二侧墙 260的器件堆叠为掩 模， 利用各向异性的方式对位于所述器件堆叠两侧的部分所述衬底 130 进行刻蚀， 形成位于器件堆叠两侧的凹槽 160 , 以及在基底区 100下方的 支撑结构 131。 在本实施例中， 刻蚀方式优选为干法刻蚀 RIE, 通过调整 和控制 RIE设备的气体流量、 组分、 功耗等， 可以获得具有近乎陡直侧 壁的 槽 160和支撑结构 131。
[0057】接着， 如图 7所示， 利用对晶向具有选择性的各向异性湿法刻蚀， 继续对凹槽 160的底面以及凹槽 160和支撑结构 131 的侧壁进行刻蚀， 使得凹槽 160的侧壁截面为∑形， 该∑形的顶点凸出至器件堆叠正下方。 在本实施例中， 所述衬底 130的晶向为<100>, 湿法刻蚀的腐蚀溶液可以 是氢氧化钾（ KOH )、四曱基氢氧化铵（ TMAH )或乙二胺-邻苯二酚（ EDP ) 等， 或其组合， 腐蚀液的浓度为 5~40%质量百分比， 反应温度为 40°C~90°C。 由于 KOH、 TMAH等腐蚀液对单晶 Si腐蚀具有各向异性， 对 { 111 }晶面的腐蚀速率与其他晶面的腐蚀速率之比约为 1 : 100 , 因此对 { 1 11 }晶面基本不腐蚀。 如图 7所示， 所述凹槽 160的侧壁皆为腐蚀停止 面， 晶面为 { 1 11 }。 因此， 利用各向异性腐蚀， 使得 槽的侧壁截面为∑ 形， 该∑形的顶点凸出至器件堆叠正下方， 相应地， 所述支撑结构 131的 侧壁截面为内凹的 Sigma形。 另外， 由于凹槽的底面晶向为<100>, 湿法 刻蚀会使得凹槽 160变深。
[0058】在步骤 S105中， 形成填充所述凹槽的第一半导体层 110。
[0059】具体地， 如图 8所示， 通过选择性外延生长的方式对位于带有第二 侧墙 260的器件堆叠两侧的 槽进行填充， 以形成半导体层 1 10 (下文中 以第一半导体层 110表示） 。 在本实施例中， 第一半导体层 1 10的材料 为 SiGe, 其中， Ge元素比例在 10%-20%之间。 需要说明的是， 第一半导 体层 110的上表面不低于刻蚀停止层 250的下表面。 另外， 如图 8所示， 由于凹槽 160的侧壁截面为∑形， 该∑形的顶点凸出至器件堆叠正下方， 选择性外延生长的第一半导体层 1 10凸出至器件堆叠正下方。 [0060】在步骤 S106中， 去除位于所述器件堆叠两侧的部分所述第一半导 体层 110 , 保留一定厚度的第一半导体层 1 10。
[0061】具体地， 如图 9所示， 以带有第二侧墙 260的器件堆叠为掩模， 采 用例如干法刻蚀等方式对位于所述第二侧墙 260两侧的第一半导体层 110 进行刻蚀。 在刻蚀过程中， 并不完全去除所述第一半导体层 1 10, 而是在 所述第二侧墙 260的两侧仍保留了一定厚度的第一半导体层 1 10。 另外， 由于所选用的刻蚀基本是各向异性的 （基本只在垂直方向刻蚀） ， 第一 半导体层 1 10凸出至器件堆叠正下方的部分得以保留。
[0062】在步骤 S 107中， 在所述器件堆叠的宽度方向上的部分区域中， 去 除位于所述器件堆叠两侧的所述第一半导体层 110,以暴露所述衬底 130。 上述的宽度， 是以将要形成半导体器件的沟道为基准进行定义的， 沟道 中电流方向为长度方向， 与之垂直的方向为宽度方向。 即： 图 10中左右 方向为长度方向， 纸面上与之垂直的方向为宽度方向。
[0063】具体地， 在本实施例中， 如图 10所示， 在半导体结构上形成光刻 掩模 300 , 覆盖中间部分而露出半导体结构宽度方向上的末端区域， 使得 在后续步骤中， 位于所述光刻掩模 300下的第一半导体层 110不被刻蚀 掉。 所述光刻掩模 300 的材料可以是光刻胶、 有机聚合物、 氧化硅、 氮 化硅、 硼硅玻璃、 硼磷硅玻璃及其组合。 其中， 形成光刻掩模 300 的方 法为本领域技术人员所熟悉的工艺。 为了筒明起见， 在此不再赘述。 光 刻掩模 300 的作用是对在半导体结构的宽度方向上位于中间部分的， 栅 堆叠两侧的部分第一半导体层 110 进行保护。 即， 在后续步骤中刻蚀光 刻掩模 300未覆盖的第一半导体层 110之后， 使在半导体结构的宽度方 向上位于中间部分的栅堆叠两侧还存在部分第一半导体层 110。如下面将 说明的， 本发明中的光刻掩模 300的位置不仅限于图 10中所示的位置， 凡是可以在半导体结构宽度方向上的部分区域中覆盖位于所述器件堆叠 两侧的所述第一半导体层 110的光刻掩模 300均适用于本发明所提供的 制造方法， 在此不再——列举说明。
[0064】接着， 以光刻掩模 300和带有第二侧墙 260的器件堆叠为掩模， 以 及以所述衬底 130 为刻蚀停止层， 对在所述器件堆叠的宽度方向上的两 个末端区域中（在其他实施例中， 为在所述器件堆叠的宽度方向上未被光 刻掩模 300所覆盖的区域中）， 位于栅堆叠和第二侧墙 260以外的第一半 导体层 1 10进行刻蚀， 直至暴露衬底 130。 然后， 去除所述光刻掩模 300。 请参考图 1 1、 图 1 1a和图 l ib , 其中， 图 1 1为刻蚀第一半导体层 110以 暴露部分衬底并去除光刻掩模 300后的俯视示意图，图 11a和图 l ib分别 为图 11的沿剖线 AA，和沿剖线 BB，的剖视示意图。 如图 1 1a所示， 在半 导体结构的宽度方向上的中间部分， 位于第二侧墙 260 两侧的、 且被光 刻掩模 300所覆盖的第一半导体层 1 10得以保留， 而在半导体结构的宽 度方向上的两个末端区域中， 位于第二侧墙 260 两侧的、 且未被光刻掩 模 300所覆盖的第一半导体层 1 10被去除， 并暴露出位于其下方的衬底 130, 如图 l ib所示。 由于所选用的刻蚀基本是各向异性的 （基本只在垂 直方向刻蚀） ， 第一半导体层 110 凸出至器件堆叠正下方的部分得以保 留。
[0065]在步骤 S108中，在所述器件堆叠的宽度方向上的所述部分区域中， 在第二侧墙 260 以及器件堆叠的两侧边缘下方形成连接衬底的隔离结构 123。
[0066】具体地， 请参考图 12、 图 12a和图 12b所示， 其中， 图 12为对第 一半导体层 1 10进行横向选择性腐蚀后的俯视示意图， 图 12a和图 12b 分别为图 12的沿剖线 AA，和沿剖线 BB，的剖视示意图。 如图所示， 对位 于栅堆叠和第二侧墙 260下方的第一半导体层 110进行回刻蚀， 通过控 制刻蚀时间使横向腐蚀深度略大于第二侧墙 260和刻蚀停止层 250的厚 度之和。
[0067】接着， 请参考图 13、 图 13a和图 13b所示， 其中， 图 13为形成隔 离结构后的俯视示意图， 图 13a和图 13b分别为图 13的沿剖线 AA'和沿 剖线 BB，的剖视示意图。如图所示， 利用例如外延生长的方法在暴露的衬 底 130的上表面以及的第一半导体层 110的上表面和侧壁上形成第二半 导体层 (未示出）， 并通过各向异性的刻蚀方式（例如 RIE, 基本上仅在垂 直方向上刻蚀）去除位于暴露的衬底 130 的上表面以及位于第一半导体 层 110上表面上第二半导体层， 而保留带有第二侧墙 260的器件堆叠下 方 （主要在第二侧墙 260下方） 的第二半导体层， 以形成隔离结构 123。 在横向上隔离结构 123 大致位于第二侧墙 260 以及器件堆叠的两侧边缘 下方。 在本实施例中， 所述隔离结构 123 的材料为单晶硅， 在其他实施 例中， 所述隔离结构 123 的材料还可以是其他不同于所述第一半导体层 110的半导体材料。 如图 13a所示， 由于在半导体结构的宽度方向上的中 间部分， 所述第一半导体层 110在所述光刻掩模 300(请参考图 10)的保护 下没有刻蚀完全， 所以， 在先前被所述光刻掩模 300 所覆盖的第一半导 体层 110的侧壁上形成隔离结构 123的时候， 该隔离结构 123是形成在 所述第一半导体层 1 10之上的， 即， 所述隔离结构 123与衬底 130之间 存在第一半导体层 110; 而如图 13b所示， 在没有所述光刻掩模 300保护 的在半导体结构的宽度方向上的两个末端区域中， 刻蚀停止在所述衬底 130的表面， 所以在形成所述隔离结构 123时， 其下方没有第一半导体层 110, 即， 所述隔离结构 123直接形成在所述衬底 130之上， 与所述衬底 130相连接。尽管本实施例中以在半导体结构的宽度方向上的两个末端区 域形成隔离结构 123 为例进行了说明， 但是本领域的技术人员应该可以 理解， 所述隔离结构 123 的具体位置不限于此。 例如， 本领域技术人员 可以理解， 只要是与衬底相连接、 且后续可以达到形成空腔的目的， 隔 离结构 123可以位于半导体结构的宽度方向上的任何位置， 为筒明起见， 在此不再赘述。 如图所示， 隔离结构 123和支撑结构 131之间存在未被 刻蚀掉的、 第一半导体层 110凸出至器件堆叠正下方的部分。
[0068】在步骤 S 109 中， 去除剩余的所述第一半导体层 110, 在所述支撑 结构 131和所述隔离结构 123之间形成空腔 112。
[0069】具体地， 如图 14、 图 14a和图 14b, 其中， 图 14为去除第一半导 体层 110在所述栅堆叠下方形成空腔 112后的俯视示意图， 图 14a和图 14b分别为图 14的沿剖线 AA，和沿剖线 BB，的剖视示意图。 如图所示， 利用湿法刻蚀的方式， 选择性去除剩余的所述第一半导体层 1 10, 在所述 栅堆叠的下方形成在所述支撑结构 131和所述隔离结构 123之间的空腔 112 , 该空腔 112中原来填充了第一半导体层 1 10凸出至器件堆叠正下方 的部分。 由于所述第一半导体层 110 的材料不同于衬底 130、 支撑结构 131、基底区 100和隔离结构 123的材料，所以通过选择相应的腐蚀溶液， 可以仅仅将剩余的第一半导体层 1 10 去除。 腐蚀溶液首先对位于隔离结 构 123之外的第一半导体层 110进行腐蚀， 然后将位于半导体结构的宽 度方向上的中间部分的隔离结构 123和衬底 130之间的第一半导体层 110 去除， 这时， 在半导体结构的宽度方向上的中间部分， 在所述隔离结构
123和衬底 130之间形成间隙，腐蚀溶液通过该间隙对位于栅堆叠下方的 第一半导体层 110继续进行腐蚀， 直至将所有第一半导体层 1 10完全被 去除， 从而在栅堆叠下方的支撑结构 131和隔离结构 123之间形成空腔 112。 此时， 如图 14a所示， 对于之前隔离结构 123和衬底 130之间存在 第一半导体层 110的区域， 在所述第一半导体层 1 10被去除后， 所述隔 离结构 123和衬底 130之间形成间隙， 而如图 14b所示， 对于之前隔离 结构 123和衬底 130之间不存在第一半导体层 110的区域， 所述隔离结 构 123和衬底 130相连接。
[0070】在步骤 S 110中， 去除第二侧墙 260, 并在所述器件堆叠的两侧形 成源 /漏区。
[0071】具体地， 请参考图 15、 图 15a和图 15b所示， 其中， 图 15为在栅 堆叠的两侧填充应力材料后的俯视示意图， 图 15a和图 15b分别为图 15 的沿剖线 AA，和沿剖线 BB，的剖视示意图。 如图所示， 首先， 以刻蚀停止 层 250为刻蚀停止层， 利用干法刻蚀的方式去除第二侧墙 260; 接着， 以 第一侧墙 240 为刻蚀停止层， 继续利用干法刻蚀的方式去除所述刻蚀停 止层 250 , 暴露出器件堆叠； 然后， 向所述器件堆叠两侧充应力材料， 以 形成源 /漏区 1 13 , 其中， 所述源 /漏区 1 13的上表面优选高于所述栅堆叠 的底部或者与所述栅堆叠的底部齐平。 由于隔离结构 123 的存在， 所以 应力材料基本存在于隔离结构 123之外， 进而保证空腔 1 12不被填充。 如图 15a所示，在所述隔离结构 123没有直接接触衬底 130的区域， 由于 所述隔离结构 123和衬底 130之间存在一定的间隙， 所以会有少量应力 材料从该间隙内进入所述空腔 112 ,但该少量应力材料进入缝隙后堆积形 成屏障， 致使只有该部分应力材料进入了所述空腔 112 , 而大部分应力材 料被隔离在外； 如图 15b所示， 在所述隔离结构 123和衬底 130相连接 的区域， 所述应力材料完全被所述隔离结构 123 阻挡在所述空腔 112之 外。
[0072】形成所述源 /漏区 113 的方法优选为外延生长。 对于 PFET器件， 所述源 /漏区 113的材料为掺杂硼的 Sil cGex, X的取值范围为 0.1 ~ 0.7 , 如 0.2、 0.3、 0.4、 0.5或 0.6; 对于 NFET器件， 所述源 /漏区 113的材料 为掺杂磷或砷的 Si:C , C 的原子数百分比的取值范围为 0.2% ~ 2% , 如 0.5%、 1%或 1.5%。 应力材料硅锗或硅碳的存在利于进一步调节沟道区内 的应力， 以提高沟道区内载流子的迁移率。 对于 PFET器件来说， 填充含 掺杂的应力材料后， 形成了 N型超陡后退阱； 对于 NFET器件来说， 填 充含掺杂的应力材料后， 形成了 P型超陡后退阱。
[0073】与现有技术相比， 本发明具有以下优点： 由于沟道下方存在空腔， 所以位于沟道两侧的应力材料层的应力可以更为集中地作用于沟道， 从 而有效地提升了应力对沟道载流子迁移率的影响， 增强对沟道性能的控 制作用； 此外， 沟道下方空腔的存在还有利于增强源 /漏区的陡直性， 从 而抑制短沟道效应， 提高半导体器件的性能。
[0074]虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本 发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施 例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员 应当容易理解在保持本发明保护范围内的同时， 工艺步骤的次序可以变 化。
[0075】此外，本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或者以后即 将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它 们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的 结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要求旨 在将这些工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含在其保 护范围内。

Claims

权 利 要 求
1. 一种半导体结构的制造方法， 该方法包括以下步骤：
a) 提供衬底（130) , 在该衬底（130)之上形成栅堆叠以及围绕该栅堆叠 的第一侧墙 (240);
b) 去除位于所述栅堆叠两侧的部分所述衬底（130) , 形成器件堆叠； c) 在所述器件堆叠的侧壁上形成第二侧墙 (260)；
d) 以带有第二侧墙 ( 260 )的器件堆叠为掩模刻蚀位于所述器件堆叠 两侧的衬底（130) , 形成位于器件堆叠两侧的 槽（160)以及在所述器件堆 叠下方的支撑结构（131) , 其中通过控制刻蚀使得所述 槽（160)的侧壁截 面为∑形， 该∑形的顶点凸出至器件堆叠正下方；
e) 形成填充所述 槽的第一半导体层（1 10);
f) 去除位于所述器件堆叠两侧的部分所述第一半导体层（110) , 保留 一定厚度的第一半导体层 (110);
g) 在所述器件堆叠的宽度方向上的部分区域中， 去除位于所述器件 堆叠两侧的所述第一半导体层（1 10), 以暴露所述衬底（130);
h) 在所述器件堆叠的宽度方向上的所述部分区域中， 在第二侧墙 (260)以及器件堆叠的两侧边缘下方形成连接衬底的隔离结构（123);
i) 去除剩余的所述第一半导体层（110) , 在所述支撑结构（131)和所述 隔离结构（123)之间形成空腔（1 12);
j) 去除第二侧墙 (260) , 并在所述器件堆叠的两侧形成源 /漏区。
2. 根据权利要求 1所述的方法， 其中所述源 /漏区包含应力材料。
3. 根据权利要求 1所述的制造方法， 其中， 通过外延生长的方式形 成源 /漏区。
4. 根据权利要求 1所述的方法， 其中所述器件堆叠的宽度方向上的 所述部分区域为所述器件堆叠的宽度方向上的两个末端区域。
5. 根据权利要求 1所述的制造方法， 其中：
6. 根据权利要求 1所述的制造方法， 其中， 所述步骤 b)包括： 以所述栅堆叠为掩模对所述衬底（130)进行刻蚀， 在所述栅堆叠下方 形成基底区（ 100) , 该基底区（ 100)与所述栅堆叠构成器件堆叠。
7. 根据权利要求 6所述的制造方法， 其中， 所述步骤 d)包括： 刻蚀位于所述器件堆叠两侧的部分所述衬底（130), 在所述器件堆叠 两侧形成凹槽（160);
对所述 槽（160)的侧壁进行刻蚀， 在所述器件堆叠下方形成侧壁截 面呈∑形状的支撑结构（131)。
8. 根据权利要求 7所述的制造方法， 其中， 所述步骤 g)包括： 在所述半导体结构上形成光刻掩模 (300) , 覆盖所述器件堆叠的宽度 方向上的部分区域；
以所述光刻掩模 (300)和带有所述第二侧墙 (260)的器件堆叠为掩模， 刻蚀部分所述第一半导体层（110); 以及
去除所述光刻掩模 (300)。
9. 根据权利要求 8所述的制造方法， 其中， 所述步骤 h)包括： 对位于所述栅堆叠下方的第一半导体层（ 110)进行回刻蚀；
通过外延生长在暴露的衬底 （ 130 ) 的上表面以及所述第一半导体层 (110)的上表面和侧壁上形成第二半导体层； 以及
利用各向异性的刻蚀方式去除位于暴露的衬底（ 130 ) 的上表面以及 所述第一半导体层（110)上表面上的第二半导体层， 形成隔离结构（123)。
10. 根据权利要求 1所述的制造方法， 其中：
所述源 /漏区的上表面高于所述栅堆叠的底部或者与所述栅堆叠的底 部齐平。
11. 根据权利要求 1 所述的制造方法， 其中所述衬底（130)的材料包 括硅， 所述第一半导体层的材料包括硅锗， 所述第二半导体层的材料包 括硅， 所述源 /漏区的材料包括硅锗或硅碳。
12. 一种半导体结构， 包括衬底（130)、支撑结构（131) 、基底区（100)、 栅堆叠、 侧墙 (240)以及源 /漏区， 其中， 所述栅堆叠位于所述基底区（100) 之上， 所述基底区（100) 由支撑结构（131)支撑于所述衬底（130)之上， 其 中： 所述支撑结构（131)的侧壁截面为∑形；
在所述基底区（100)两侧边缘下方存在隔离结构（123) , 其中， 部分所 述隔离结构（123)与所述衬底（130)相连接；
在所述隔离结构（123)和所述支撑结构（131)之间存在空腔（112); 以及 至少在所述基底区（100)和隔离结构（123)的两侧存在源 /漏区。
13. 根据权利要求 12所述的半导体结构， 其中， 进一步包括源 /漏延 伸区， 位于所述基底区中。
14. 根据权利要求 12所述的半导体结构， 其中， 所述隔离结构（123) 的材料包括硅。
15. 根据权利要求 12所述的半导体结构， 其中， 所述隔离结构（123) 除了与所述衬底（130)直接接触的部分， 其他部分与衬底（130)之间夹有硅 锗或硅碳。
16. 根据权利要求 12所述的半导体结构， 其中， 所述衬底（130)的材 料包括硅。
17. 根据权利要求 12所述的半导体结构， 其中， 所述源 /漏区的材料 包括硅锗或硅碳。
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