CN106611780A - 量子阱器件及其形成方法 - Google Patents

量子阱器件及其形成方法 Download PDF

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CN106611780A
CN106611780A CN201510707751.1A CN201510707751A CN106611780A CN 106611780 A CN106611780 A CN 106611780A CN 201510707751 A CN201510707751 A CN 201510707751A CN 106611780 A CN106611780 A CN 106611780A
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quantum well
forming method
layer
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肖德元
张汝京
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Zing Semiconductor Corp
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Priority to US15/067,196 priority patent/US9634133B1/en
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Abstract

本发明提出了一种量子阱器件及其形成方法，能够形成具有高迁移率的量子阱器件，并且形成的量子阱器件具有较高的击穿电压，从而获得具有较好的性能及可靠性的量子阱器件。

Description

量子阱器件及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种量子阱器件及其形成方法。
背景技术
高电子迁移率晶体管(HEMT)的基本结构由一个调制掺杂异质结及其源漏结构组成。存在于调制掺杂异质结中的二维电子气(2-DEG)，由于不受电离杂质离子散射的影响，其迁移率非常高。HEMT是电压控制器件，栅极电压Vg可控制异质结势阱的深度，从而控制势阱中2-DEG的面密度，进而控制器件的工作电流。对于GaAs体系的HEMT，通常其中的n-AlxGa1-xAs控制层应该是耗尽的。若n-AlxGa1-xAs层厚度较大、掺杂浓度又高，则在Vg＝0时就存在有2-DEG，为耗尽型器件，反之则为增强型器件(Vg＝0时，肖特基耗尽层即延伸到本征GaAs层内部)；对于HEMT，主要是要控制好宽禁带半导体层(控制层)的掺杂浓度和厚度，特别是厚度。在考虑HEMT中的2-DEG面密度Ns时，通常只需要考虑异质结势阱中的两个二维子能带(i＝0和1)即可。2-DEG面电荷密度Ns将受到栅极电压Vg的控制。
发明内容
本发明的目的在于提供一种量子阱器件及其形成方法，能够获得具有高迁移率的量子阱器件。
为了实现上述目的，本发明提出了一种量子阱器件的形成方法，包括步骤：
提供图形化的衬底；
在图形化的所述衬底表面形成缓冲层；
对所述缓冲层进行刻蚀处理，形成鱼鳍状结构；
在所述缓冲层及鱼鳍状结构表面上依次沉积量子阱层、阻挡层、覆盖层及介质层；
在所述介质层表面形成金属层；
对所述金属层和介质层进行刻蚀，形成金属栅极和栅介质层；
在所述金属栅极和栅介质层的两侧形成侧墙；
依次刻蚀所述覆盖层、阻挡层及量子阱层形成源漏凹陷区，所述凹陷区暴露出所述缓冲层并延伸至所述侧墙的下方；
在所述源漏凹陷区中形成掺杂的源漏区。
进一步的，在所述的量子阱器件的形成方法中，所述图形化的衬底为设有Σ型凹槽的衬底。
进一步的，在所述的量子阱器件的形成方法中，所述Σ型凹槽的衬底的形成步骤包括：
提供衬底；
在所述衬底上形成图案化的掩模层，所述图案化的掩模层暴露出部分衬底；
采用干法刻蚀刻蚀暴露出的衬底，形成圆弧状凹槽；
采用湿法刻蚀对所述圆弧状凹槽进行刻蚀，形成Σ型凹槽；
去除所述图案化的掩模层。
进一步的，在所述的量子阱器件的形成方法中，所述湿法刻蚀采用KOH溶液或者TMAH溶液。
进一步的，在所述的量子阱器件的形成方法中，所述衬底材质为硅、蓝宝石或者SiC。
进一步的，在所述的量子阱器件的形成方法中，所述缓冲层材质为AlN或AlGaN，其厚度范围是1μm～10μm。
进一步的，在所述的量子阱器件的形成方法中，所述缓冲层采用MOCVD、ALD或者MBE工艺形成。
进一步的，在所述的量子阱器件的形成方法中，采用BCl3对所述缓冲层进行刻蚀处理，形成鱼鳍状结构。
进一步的，在所述的量子阱器件的形成方法中，所述量子阱层材质为GaN、InGaN、AlGaN、锗、III-V或者II-VI族元素，其厚度范围是10nm～100nm。
进一步的，在所述的量子阱器件的形成方法中，所述阻挡层材质为AlN、InGaN、AlGaN、III-V或者II-VI族元素，其厚度范围是10nm～100nm。
进一步的，在所述的量子阱器件的形成方法中，所述覆盖层为GaN，其厚度范围为10nm～50nm。
进一步的，在所述的量子阱器件的形成方法中，所述介质层的材质为二氧化硅、氧化铝、氧化锆或氧化铪，其厚度范围是1nm～5nm。
进一步的，在所述的量子阱器件的形成方法中，量子阱层、阻挡层、覆盖层及介质层采用MOCVD、ALD或MBE工艺形成。
进一步的，在所述的量子阱器件的形成方法中，所述金属层的材质为NiAu或CrAu。
进一步的，在所述的量子阱器件的形成方法中，所述金属层采用PVD、MOCVD、ALD或MBE工艺形成。
进一步的，在所述的量子阱器件的形成方法中，所述侧墙的材质为氮化硅。
进一步的，在所述的量子阱器件的形成方法中，所述源漏凹陷区的形成步骤包括：
采用干法刻蚀依次去除位于所述侧墙两侧暴露出的覆盖层、阻挡层及量子阱层，暴露出所述缓冲层；
采用湿法刻蚀去除位于所述侧墙下方的覆盖层、阻挡层及量子阱层，形成源漏凹陷区，所述源漏凹陷区与所述金属栅极和栅介质层不存在重叠部分。
进一步的，在所述的量子阱器件的形成方法中，所述干法刻蚀采用的气体为BCl3。
进一步的，在所述的量子阱器件的形成方法中，所述湿法刻蚀采用质量分数为30％～50％的NaOH溶液刻蚀去除所述量子阱层和覆盖层。
进一步的，在所述的量子阱器件的形成方法中，所述湿法刻蚀采用HF溶液刻蚀去除所述阻挡层。
进一步的，在所述的量子阱器件的形成方法中，所述源漏区材质为掺杂硅的GaN。
进一步的，在所述的量子阱器件的形成方法中，所述源漏区采用MOCVD、ALD或者MBE工艺形成。
进一步的，在所述的量子阱器件的形成方法中，在形成源漏区后，在所述源漏区上形成源漏区电极。
本发明提出了一种量子阱器件，采用如上文所述的量子阱器件的形成方法形成，包括：图形化的衬底、设有鱼鳍状结构的缓冲层、量子阱层、阻挡层、覆盖层、金属栅极、栅介质层、侧墙及源漏区，其中，所述设有鱼鳍状结构的缓冲层形成在所述图形化的衬底上，所述量子阱层、阻挡层、覆盖层、金属栅极及栅介质层依次形成在所述设有鱼鳍状结构的缓冲层上，所述侧墙形成在所述金属栅极及栅介质层的两侧，所述源漏区形成在所述缓冲层上，位于所述金属栅极及栅介质层的两侧，并延伸一部分至所述侧墙的下方。
进一步的，在所述的量子阱器件中，还包括源漏区电极，所述源漏区电极形成在所述源漏区上。
与现有技术相比，本发明的有益效果主要体现在：提出了一种量子阱器件的形成方法，能够形成具有高迁移率的量子阱器件，并且形成的量子阱器件具有较高的击穿电压，从而获得具有较好的性能及可靠性的量子阱器件。
附图说明
图1为本发明一实施例中量子阱器件的形成方法的流程图；
图2a至图2c为本发明一实施例中图形化衬底的形成方法；
图3为本发明一实施例中形成缓冲层后的剖面示意图；
图4a至图13a为本发明一实施例中形成量子阱器件过程中沿着与沟道垂直方向的剖面示意图；
图4b至图13b为本发明一实施例中形成量子阱器件过程中沿着沟道方向的剖面示意图。
具体实施方式
下面将结合示意图对本发明的量子阱器件及其形成方法进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
为了清楚，不描述实际实施例的全部特征。在下列描述中，不详细描述公知的功能和结构，因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中，必须做出大量实施细节以实现开发者的特定目标，例如按照有关系统或有关商业的限制，由一个实施例改变为另一个实施例。另外，应当认为这种开发工作可能是复杂和耗费时间的，但是对于本领域技术人员来说仅仅是常规工作。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图1，在本发明中，提出了一种量子阱器件的形成方法，包括步骤：
S100：提供图形化的衬底；
S200：在图形化的所述衬底表面形成缓冲层；
S300：对所述缓冲层进行刻蚀处理，形成鱼鳍状结构；
S400：在所述缓冲层及鱼鳍状结构表面上依次沉积量子阱层、阻挡层、覆盖层及介质层；
S500：在所述介质层表面形成金属层；
S600：对所述金属层和介质层进行刻蚀，形成金属栅极和栅介质层；
S700：在所述金属栅极和栅介质层的两侧形成侧墙；
S800：依次刻蚀所述覆盖层、阻挡层及量子阱层形成源漏凹陷区，所述凹陷区暴露出所述缓冲层并延伸至所述侧墙的下方；
S900：在所述源漏凹陷区中形成掺杂的源漏区。
具体的，请参考图2a至图2c，在步骤S100中，所述图形化的衬底100为设有Σ型凹槽的衬底。所述Σ型凹槽的衬底100的形成步骤包括：
提供衬底100，其中，所述衬底100可以为硅衬底、蓝宝石衬底或者SiC衬底；
在所述衬底100上形成图案化的掩模层200，所述图案化的掩模层200暴露出部分衬底100，所述掩模层200可以为氮化硅等材质；
采用干法刻蚀刻蚀暴露出的衬底100，形成圆弧状凹槽110；
采用湿法刻蚀对所述圆弧状凹槽110进行刻蚀，形成Σ型凹槽120；其中，所述湿法刻蚀采用KOH溶液或者TMAH溶液(羟化四甲铵，tetramethylazaniumhydroxide)；
去除所述图案化的掩模层200。
请参考图3，在步骤S200中，在图形化的所述衬底100表面形成缓冲层300；所述缓冲层300材质为AlN或AlGaN，其厚度范围是1μm～10μm，例如是5μm。所述缓冲层300可以采用MOCVD(Metal-organic Chemical VaporDeposition，金属有机化合物化学气相沉淀)、ALD(Atomic layer deposition，原子层沉积)或者MBE(Molecular Beam Epitaxy，分子束外延)工艺形成。
接着，请参考图4a和图4b，采用BCl3对所述缓冲层300进行刻蚀处理，形成鱼鳍状结构(Fin)310。
请参考图5a、图5b、图6a和图6b，在所述缓冲层300及鱼鳍状结构310表面上依次沉积量子阱层410、阻挡层420、覆盖层430及介质层440；其中，所述量子阱层410材质为GaN、InGaN、AlGaN、锗、III-V或者II-VI族元素，在本实施例中，例如是GaN，其厚度范围是10nm～100nm，例如是50nm。所述阻挡层420材质为AlN、InGaN、AlGaN、III-V或者II-VI族元素，在本实施例中，例如是AlN，其厚度范围是10nm～100nm，例如是50nm。其中，阻挡层材质可以与量子阱层材质相同，但组分不同，阻挡层材质的禁带宽度必须大于量子阱层材质的禁带宽度所述覆盖层430为GaN，其厚度范围为10nm～50nm，例如是20nm。所述介质层440的材质为二氧化硅、氧化铝、氧化锆或氧化铪，其厚度范围是1nm～5nm，例如是3nm。其中，所述量子阱层410、阻挡层420、覆盖层430及介质层440均可以采用MOCVD、ALD或MBE工艺形成。形成的量子阱层410、阻挡层420、覆盖层430结构，调制掺杂异质结中的量子阱层410可以形成二维电子气(2-DEG，如图中虚线所示)，由于不受电离杂质离子散射的影响，其迁移率非常高。从而可以使形成的量子阱器件具有较高的迁移率。
请参考图7a和图7b，在所述介质层440表面形成金属层500；所述金属层500的材质为NiAu或CrAu，其可以采用PVD(Physical Vapor Deposition，物理气相沉积)、MOCVD、ALD或MBE工艺形成。
请参考图8a和图8b，对所述金属层500和介质层440进行刻蚀，形成金属栅极510和栅介质层441。
接着，请参考图9a和图9b，在所述金属栅极510和栅介质层441的两侧形成侧墙600；所述侧墙600的材质为氮化硅。
接着，依次刻蚀所述覆盖层430、阻挡层420及量子阱层410形成源漏凹陷区，所述凹陷区暴露出所述缓冲层300并延伸至所述侧墙600的下方，但与所述金属栅极510及栅介质层441之间无重叠；
具体的，所述源漏凹陷区的形成步骤包括：
采用干法刻蚀依次去除位于所述侧墙600两侧暴露出的覆盖层430、阻挡层420及量子阱层410，暴露出所述缓冲层300，如图10a和图10b所示；其中，干法刻蚀采用的气体为BCl3；
采用湿法刻蚀去除位于所述侧墙600下方的覆盖层430、阻挡层420及量子阱层410，形成源漏凹陷区，所述源漏凹陷区与所述金属栅极510和栅介质层441不存在重叠部分，如图11a和图11b所示，其中，所述湿法刻蚀采用质量分数为30％～50％的NaOH溶液刻蚀去除所述量子阱层410和覆盖层430，其中，量子阱层410和覆盖层430的材质在本实施例中均为GaN；所述湿法刻蚀采用HF溶液刻蚀去除所述阻挡层420，其中，在本实施例中所述阻挡层420的材质为AlN。
接着，请参考图12a和图12b，在所述源漏凹陷区中形成掺杂的源漏区700，其中，所述源漏区700的材质为掺杂硅的GaN。所述源漏区采用MOCVD、ALD或者MBE工艺形成。
接着，请参考图13a和图13b，在形成源漏区700后，在所述源漏区700上形成源漏区电极800。
在本实施例的另一方面，还提出了一种量子阱器件，采用如上文所述的量子阱器件的形成方法形成，包括：图形化的衬底100、设有鱼鳍状结构310的缓冲层300、量子阱层410、阻挡层420、覆盖层430、金属栅极510、栅介质层441、侧墙600及源漏区700，其中，所述设有鱼鳍状结构310的缓冲层300形成在所述图形化的衬底100上，所述量子阱层410、阻挡层420、覆盖层430、金属栅极510及栅介质层441依次形成在所述设有鱼鳍状结构310的缓冲层300上，所述侧墙600形成在所述金属栅极510及栅介质层441的两侧，所述源漏区700形成在所述缓冲层300上，位于所述金属栅极510及栅介质层441的两侧，并延伸一部分至所述侧墙600的下方，但与所述金属栅极510及栅介质层441无重叠部分。
其中，量子阱器件还包括源漏区电极800，所述源漏区电极800形成在所述源漏区700上。
综上，在本发明实施例提供的量子阱器件及其形成方法中，提出了一种量子阱器件的形成方法，能够形成具有高迁移率的量子阱器件，并且形成的量子阱器件具有较高的击穿电压，从而获得具有较好的性能及可靠性的量子阱器件。
上述仅为本发明的优选实施例而已，并不对本发明起到任何限制作用。任何所属技术领域的技术人员，在不脱离本发明的技术方案的范围内，对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动，均属未脱离本发明的技术方案的内容，仍属于本发明的保护范围之内。

Claims (25)

1.一种量子阱器件的形成方法，其特征在于，包括步骤：
提供图形化的衬底；
在图形化的所述衬底表面形成缓冲层；
对所述缓冲层进行刻蚀处理，形成鱼鳍状结构；
在所述缓冲层及鱼鳍状结构表面上依次沉积量子阱层、阻挡层、覆盖层及介质层；
在所述介质层表面形成金属层；
对所述金属层和介质层进行刻蚀，形成金属栅极和栅介质层；
在所述金属栅极和栅介质层的两侧形成侧墙；
依次刻蚀所述覆盖层、阻挡层及量子阱层形成源漏凹陷区，所述源漏凹陷区暴露出所述缓冲层并延伸至所述侧墙的下方；
在所述源漏凹陷区中形成掺杂的源漏区。
2.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述图形化的衬底为设有Σ型凹槽的衬底。
3.如权利要求2所述的量子阱器件的形成方法，其特征在于，所述Σ型凹槽的衬底的形成步骤包括：
提供衬底；
在所述衬底上形成图案化的掩模层，所述图案化的掩模层暴露出部分衬底；
采用干法刻蚀刻蚀暴露出的衬底，形成圆弧状凹槽；
采用湿法刻蚀对所述圆弧状凹槽进行刻蚀，形成Σ型凹槽；
去除所述图案化的掩模层。
4.如权利要求3所述的量子阱器件的形成方法，其特征在于，所述湿法刻蚀采用KOH溶液或者TMAH溶液。
5.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述衬底材质为硅、蓝宝石或者SiC。
6.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述缓冲层材质为AlN或AlGaN，其厚度范围是1μm～10μm。
7.如权利要求6所述的量子阱器件的形成方法，其特征在于，所述缓冲层采用MOCVD、ALD或者MBE工艺形成。
8.如权利要求1所述的量子阱器件的形成方法，其特征在于，采用BCl3对所述缓冲层进行刻蚀处理，形成鱼鳍状结构。
9.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述量子阱层材质为GaN、InGaN、AlGaN、锗、III-V或者II-VI族元素，其厚度范围是10nm～100nm。
10.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述阻挡层材质为AlN、InGaN、AlGaN、III-V或者II-VI族元素，其厚度范围是10nm～100nm。
11.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述覆盖层为GaN，其厚度范围为10nm～50nm。
12.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述介质层的材质为二氧化硅、氧化铝、氧化锆或氧化铪，其厚度范围是1nm～5nm。
13.如权利要求1所述的量子阱器件的形成方法，其特征在于，量子阱层、阻挡层、覆盖层及介质层采用MOCVD、ALD或MBE工艺形成。
14.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述金属层的材质为NiAu或CrAu。
15.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述金属层采用PVD、MOCVD、ALD或MBE工艺形成。
16.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述侧墙的材质为氮化硅。
17.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述源漏凹陷区的形成步骤包括：
采用干法刻蚀依次去除位于所述侧墙两侧暴露出的覆盖层、阻挡层及量子阱层，暴露出所述缓冲层；
采用湿法刻蚀去除位于所述侧墙下方的覆盖层、阻挡层及量子阱层，形成源漏凹陷区，所述源漏凹陷区与所述金属栅极和栅介质层不存在重叠部分。
18.如权利要求17所述的量子阱器件的形成方法，其特征在于，所述干法刻蚀采用的气体为BCl3。
19.如权利要求17所述的量子阱器件的形成方法，其特征在于，所述湿法刻蚀采用质量分数为30％～50％的NaOH溶液刻蚀去除所述量子阱层和覆盖层。
20.如权利要求17所述的量子阱器件的形成方法，其特征在于，所述湿法刻蚀采用HF溶液刻蚀去除所述阻挡层。
21.如权利要求1所述的量子阱器件的形成方法，其特征在于，所述源漏区材质为硅掺杂的GaN。
22.如权利要求21所述的量子阱器件的形成方法，其特征在于，所述源漏区采用MOCVD、ALD或者MBE工艺形成。
23.如权利要求1所述的量子阱器件的形成方法，其特征在于，在形成源漏区后，在所述源漏区上形成源漏区电极。
24.一种量子阱器件，采用如权利要求1至23中任一种所述的量子阱器件的形成方法形成，其特征在于，包括：图形化的衬底、设有鱼鳍状结构的缓冲层、量子阱层、阻挡层、覆盖层、金属栅极、栅介质层、侧墙及源漏区，其中，所述设有鱼鳍状结构的缓冲层形成在所述图形化的衬底上，所述量子阱层、阻挡层、覆盖层、金属栅极及栅介质层依次形成在所述设有鱼鳍状结构的缓冲层上，所述侧墙形成在所述金属栅极及栅介质层的两侧，所述源漏区形成在所述缓冲层上，位于所述金属栅极及栅介质层的两侧，并延伸一部分至所述侧墙的下方。
25.如权利要求24所述的量子阱器件，其特征在于，还包括源漏区电极，所述源漏区电极形成在所述源漏区上。
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