CN106611781A - 量子阱器件及其形成方法 - Google Patents
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Abstract
本发明提出了一种量子阱器件及其形成方法,能够形成具有高迁移率的量子阱器件,并且形成的量子阱器件具有较高的击穿电压,从而获得具有较好的性能及可靠性的量子阱器件。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种量子阱器件及其形成方法。
背景技术
高电子迁移率晶体管(HEMT)的基本结构由一个调制掺杂异质结及其源漏结构组成。存在于调制掺杂异质结中的二维电子气(2-DEG),由于不受电离杂质离子散射的影响,其迁移率非常高。HEMT是电压控制器件,栅极电压Vg可控制异质结势阱的深度,从而控制势阱中2-DEG的面密度,进而控制器件的工作电流。对于GaAs体系的HEMT,通常其中的n-AlxGa1-xAs控制层应该是耗尽的。若n-AlxGa1-xAs层厚度较大、掺杂浓度又高,则在Vg=0时就存在有2-DEG,为耗尽型器件,反之则为增强型器件(Vg=0时,肖特基耗尽层即延伸到本征GaAs层内部);对于HEMT,主要是要控制好宽禁带半导体层(控制层)的掺杂浓度和厚度,特别是厚度。在考虑HEMT中的2-DEG面密度Ns时,通常只需要考虑异质结势阱中的两个二维子能带(i=0和1)即可。2-DEG面电荷密度Ns将受到栅极电压Vg的控制。
发明内容
本发明的目的在于提供一种量子阱器件及其形成方法,能够获得具有高迁移率的量子阱器件。
为了实现上述目的,本发明提出了一种量子阱器件的形成方法,包括步骤:
提供衬底,在所述衬底的表面形成具有鳍状结构的缓冲层;
在所述缓冲层及鳍状结构表面上依次沉积量子阱沟道层、阻挡层及介质层;
在所述鳍状结构两侧的介质层表面形成金属栅极,所述金属栅极高度低于所述鳍状结构的高度;
在鳍状结构两侧暴露出的介质层表面及金属栅极的两侧形成侧墙;
依次刻蚀位于鳍状结构及缓冲层表面暴露出的介质层及阻挡层,暴露出源漏区域的所述量子阱沟道层;
在暴露出的源漏区域的量子阱沟道层内进行掺杂,形成源极和漏极;
在所述源极和漏极上形成源漏电极。
进一步的,在所述的量子阱器件的形成方法中,所述具有鳍状结构的缓冲层的形成步骤包括:
在所述衬底上形成所述缓冲层;
在所述缓冲层表面形成图案化的光阻;
以所述图案化的光阻作为掩膜,干法刻蚀所述缓冲层,形成鳍状结构。
进一步的,在所述的量子阱器件的形成方法中,所述缓冲层的材质为AlN,厚度范围是100nm~5000nm。
进一步的,在所述的量子阱器件的形成方法中,所述缓冲层采用MOCVD、ALD或者MBE工艺形成。
进一步的,在所述的量子阱器件的形成方法中,所述量子阱沟道层的材质为N-型GaN,厚度范围是1nm~100nm。
进一步的,在所述的量子阱器件的形成方法中,所述阻挡层的材质为AlN。
进一步的,在所述的量子阱器件的形成方法中,所述量子阱沟道层及阻挡层均采用外延生长工艺形成。
进一步的,在所述的量子阱器件的形成方法中,所述介质层的材质为二氧化硅、氧化铝、氧化锆或氧化铪,厚度范围是1nm~5nm。
进一步的,在所述的量子阱器件的形成方法中,所述介质层采用CVD、MOCVD、ALD或MBE工艺形成。
进一步的,在所述的量子阱器件的形成方法中,所述金属栅极的材质为NiAu或CrAu。
进一步的,在所述的量子阱器件的形成方法中,所述金属层采用CVD、PVD、MOCVD、ALD或MBE工艺形成。
进一步的,在所述的量子阱器件的形成方法中,所述侧墙的材质为氮化硅。
进一步的,在所述的量子阱器件的形成方法中,采用选择性刻蚀工艺依次刻蚀位于鳍状结构及缓冲层表面暴露出的介质层及阻挡层,暴露出源漏区域的所述量子阱沟道层。
进一步的,在所述的量子阱器件的形成方法中,采用离子注入或离子扩散工艺对所述量子阱沟道层进行N+离子注入,形成源极和漏极。
在本发明中,还提出了一种量子阱器件,采用如上文所述的量子阱器件的形成方法形成,其特征在于,包括:衬底、设有鳍状结构的缓冲层、量子阱沟道层、阻挡层、金属栅极、介质层、侧墙及源漏极,其中,所述设有鳍状结构的缓冲层形成在所述衬底上,所述量子阱沟道层、阻挡层、介质层及金属栅极依次形成在所述鳍状结构的两侧,所述侧墙形成在鳍状结构两侧暴露出的介质层表面及金属栅极的两侧,所述源极形成在金属栅极两侧的量子阱沟道层内,所述漏极形成在所述及鳍状结构顶部暴露出的量子阱沟道层内。
进一步的,在所述的量子阱器件中,还包括源漏极电极,所述源漏极电极形成在所述源极和漏极上。
与现有技术相比,本发明的有益效果主要体现在:提出了一种量子阱器件的形成方法,能够形成具有高迁移率的量子阱器件,并且形成的量子阱器件具有较高的击穿电压,从而获得具有较好的性能及可靠性的量子阱器件。
附图说明
图1为本发明一实施例中量子阱器件的形成方法的流程图;
图2至图9为本发明一实施例中形成量子阱器件过程中的剖面示意图。
具体实施方式
下面将结合示意图对本发明的量子阱器件及其形成方法进行更详细的描述,其中表示了本发明的优选实施例,应该理解本领域技术人员可以修改在此描述的本发明,而仍然实现本发明的有利效果。因此,下列描述应当被理解为对于本领域技术人员的广泛知道,而并不作为对本发明的限制。
为了清楚,不描述实际实施例的全部特征。在下列描述中,不详细描述公知的功能和结构,因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中,必须做出大量实施细节以实现开发者的特定目标,例如按照有关系统或有关商业的限制,由一个实施例改变为另一个实施例。另外,应当认为这种开发工作可能是复杂和耗费时间的,但是对于本领域技术人员来说仅仅是常规工作。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图1,在本发明中,提出了一种量子阱器件的形成方法,包括步骤:
S100:提供衬底,在所述衬底的表面形成具有鳍状结构的缓冲层;
S200:在所述缓冲层及鳍状结构表面上依次沉积量子阱沟道层、阻挡层及介质层;
S300:在所述鳍状结构两侧的介质层表面形成金属栅极,所述金属栅极高度低于所述鳍状结构的高度;
S400:在鳍状结构两侧暴露出的介质层表面及金属栅极的两侧形成侧墙;
S500:依次刻蚀位于鳍状结构及缓冲层表面暴露出的介质层及阻挡层,暴露出源漏区域的所述量子阱沟道层;
S600:在暴露出的源漏区域的量子阱沟道层内进行掺杂,形成源极和漏极;
S700:在所述源极和漏极上形成源漏电极。
具体的,请参考图2,在步骤S100中,所述衬底100可以为硅衬底、蓝宝石衬底或者SiC衬底等,其还可以是设有Σ型凹槽等图形的衬底。
在所述衬底100表面形成缓冲层200;所述缓冲层200材质为AlN,其厚度范围是100nm~5000nm,例如是3000nm。所述缓冲层200可以采用MOCVD(Metal-organic Chemical Vapor Deposition,金属有机化合物化学气相沉淀)、ALD(Atomic layer deposition,原子层沉积)或者MBE(Molecular Beam Epitaxy,分子束外延)工艺形成。
接着,在所述缓冲层200上形成鳍形结构210,其形成步骤包括:
在所述衬底上形成所述缓冲层;
在所述缓冲层表面形成图案化的光阻;
以所述图案化的光阻作为掩膜,干法刻蚀所述缓冲层,形成鳍状结构(Fin)。
接着,请参考图3和图4,在所述缓冲层200及鳍状结构210表面上依次沉积量子阱沟道层310、阻挡层320及介质层330;其中,所述量子阱沟道层310材质为N-型GaN,在本实施例中,其厚度范围是1nm~100nm,例如是50nm。所述阻挡层320材质为AlN。所述介质层330的材质为二氧化硅、氧化铝、氧化锆或氧化铪,其厚度范围是1nm~5nm,例如是3nm。其中,所述量子阱沟道层310、阻挡层320及介质层330均可以采用CVD、MOCVD、ALD或MBE等工艺形成。
接着,请参考图5,在所述鳍状结构两侧的介质层330表面形成金属栅极400,所述金属栅极400高度低于所述鳍状结构210的高度;其中,所述金属栅极400的材质为NiAu或CrAu等,其可以采用PVD(Physical Vapor Deposition,物理气相沉积)、MOCVD、ALD或MBE工艺形成。
请参考图6,在鳍状结构两侧暴露出的介质层330表面及金属栅极400的两侧形成侧墙500;所述侧墙500的材质为氮化硅。
接着,请参考图7,刻蚀位于鳍状结构210及缓冲层200表面暴露出的介质层330及阻挡层320,暴露出源漏区域的所述量子阱沟道层310;其中,采用选择性刻蚀工艺进行刻蚀,去除所述部分介质层330及阻挡层320,暴露出位于鳍状结构210顶部的量子阱沟道层310,后续作为漏极,以及位于金属栅极400两侧缓冲层200上的量子阱沟道层310,后续作为源极。
接着,请参考图8,采用离子注入或离子扩散工艺对所述量子阱沟道层310进行N+离子注入,形成源极311和漏极312。形成的量子阱层310、阻挡层320及源极311和漏极312结构,调制掺杂异质结中的量子阱层310可以形成二维电子气(2-DEG,如图中虚线所示),由于不受电离杂质离子散射的影响,其迁移率非常高,从而可以使形成的量子阱器件具有较高的迁移率。
接着,请参考图9,在所述源极311和漏极312上形成源漏电极600。
在本实施例的另一方面还提出了一种量子阱器件,采用如上文所述的量子阱器件的形成方法形成,包括:衬底100、设有鳍状结构210的缓冲层200、量子阱沟道层310、阻挡层320、金属栅极400、介质层330、侧墙500及源极311和漏极312,其中,所述设有鳍状结构的缓冲层200形成在所述衬底100上,所述量子阱沟道层310、阻挡层320、介质层330及金属栅极400依次形成在所述鳍状结构210的两侧,所述侧墙500形成在鳍状结构210两侧暴露出的介质层330表面及金属栅极400的两侧,所述源极311形成在金属栅极400两侧的量子阱沟道层310内,所述漏极312形成在所述及鳍状结构210顶部暴露出的量子阱沟道层310内。
其中,量子阱器件还包括源漏极电极600,所述源漏极电极600形成在所述源极311和漏极312上。
综上,在本发明实施例提供的量子阱器件及其形成方法中,提出了一种量子阱器件的形成方法,能够形成具有高迁移率的量子阱器件,并且形成的量子阱器件具有较高的击穿电压,从而获得具有较好的性能及可靠性的量子阱器件。
上述仅为本发明的优选实施例而已,并不对本发明起到任何限制作用。任何所属技术领域的技术人员,在不脱离本发明的技术方案的范围内,对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动,均属未脱离本发明的技术方案的内容,仍属于本发明的保护范围之内。
Claims (16)
1.一种量子阱器件的形成方法,其特征在于,包括步骤:
提供衬底,在所述衬底的表面形成具有鳍状结构的缓冲层;
在所述缓冲层及鳍状结构表面上依次沉积量子阱沟道层、阻挡层及介质层;
在所述鳍状结构两侧的介质层表面形成金属栅极,所述金属栅极高度低于所述鳍状结构的高度;
在鳍状结构两侧暴露出的介质层表面及金属栅极的两侧形成侧墙;
依次刻蚀位于鳍状结构及缓冲层表面暴露出的介质层及阻挡层,暴露出源漏区域的所述量子阱沟道层;
在暴露出的源漏区域的量子阱沟道层内进行掺杂,形成源极和漏极;
在所述源极和漏极上形成源漏电极。
2.如权利要求1所述的量子阱器件的形成方法,其特征在于,所述具有鳍状结构的缓冲层的形成步骤包括:
在所述衬底上形成所述缓冲层;
在所述缓冲层表面形成图案化的光阻;
以所述图案化的光阻作为掩膜,干法刻蚀所述缓冲层,形成鳍状结构。
3.如权利要求2所述的量子阱器件的形成方法,其特征在于,所述缓冲层的材质为AlN,厚度范围是100nm~5000nm。
4.如权利要求2所述的量子阱器件的形成方法,其特征在于,所述缓冲层采用MOCVD、ALD或者MBE工艺形成。
5.如权利要求1所述的量子阱器件的形成方法,其特征在于,所述量子阱沟道层的材质为N-型GaN,厚度范围是1nm~100nm。
6.如权利要求1所述的量子阱器件的形成方法,其特征在于,所述阻挡层的材质为AlN。
7.如权利要求5或6所述的量子阱器件的形成方法,其特征在于,所述量子阱沟道层及阻挡层均采用外延生长工艺形成。
8.如权利要求1所述的量子阱器件的形成方法,其特征在于,所述介质层的材质为二氧化硅、氧化铝、氧化锆或氧化铪,厚度范围是1nm~5nm。
9.如权利要求8所述的量子阱器件的形成方法,其特征在于,所述介质层采用CVD、MOCVD、ALD或MBE工艺形成。
10.如权利要求1所述的量子阱器件的形成方法,其特征在于,所述金属栅极的材质为NiAu或CrAu。
11.如权利要求10所述的量子阱器件的形成方法,其特征在于,所述金属层采用CVD、PVD、MOCVD、ALD或MBE工艺形成。
12.如权利要求1所述的量子阱器件的形成方法,其特征在于,所述侧墙的材质为氮化硅。
13.如权利要求1所述的量子阱器件的形成方法,其特征在于,采用选择性刻蚀工艺依次刻蚀位于鳍状结构及缓冲层表面暴露出的介质层及阻挡层,暴露出源漏区域的所述量子阱沟道层。
14.如权利要求1所述的量子阱器件的形成方法,其特征在于,采用离子注入或离子扩散工艺对所述量子阱沟道层进行N+离子注入,形成源极和漏极。
15.一种量子阱器件,采用如权利要求1至14中任一种所述的量子阱器件的形成方法形成,其特征在于,包括:衬底、设有鳍状结构的缓冲层、量子阱沟道层、阻挡层、金属栅极、介质层、侧墙及源极和漏极,其中,所述设有鳍状结构的缓冲层形成在所述衬底上,所述量子阱沟道层、阻挡层、介质层及金属栅极依次形成在所述鳍状结构的两侧,所述侧墙形成在鳍状结构两侧暴露出的介质层表面及金属栅极的两侧,所述源极形成在金属栅极两侧的量子阱沟道层内,所述漏极形成在所述及鳍状结构顶部暴露出的量子阱沟道层内。
16.如权利要求15所述的量子阱器件,其特征在于,还包括源漏极电极,所述源漏极电极形成在所述源极和漏极上。
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