CN105190896A - Resurf iii-n高电子迁移率晶体管 - Google Patents

Resurf iii-n高电子迁移率晶体管 Download PDF

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CN105190896A
CN105190896A CN201480024429.2A CN201480024429A CN105190896A CN 105190896 A CN105190896 A CN 105190896A CN 201480024429 A CN201480024429 A CN 201480024429A CN 105190896 A CN105190896 A CN 105190896A
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gallium nitride
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N·蒂皮兰尼
S·彭德哈卡尔
J·约翰
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Texas Instruments Inc
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Abstract

本发明涉及一种包括GaN？FET(124)的半导体装置(100)，在阻挡层(112)下面的低缺陷层(110)以及电隔离层(108)中的至少一个III-N半导体层中，所述半导体装置(100)具有n型掺杂质。所述n型掺杂的载流子面密度是二维电子气的载流子面密度的1％到200％。

Description

RESURF III-N高电子迁移率晶体管
技术领域
本发明总体涉及半导体装置，且更具体地，涉及RESURFIII-N高电子迁移率晶体管(HEMT)。
背景技术
氮化镓场效应晶体管(GaNFET)在二维电子气下面的半导体层中可具有陷阱，其在操作过程中引起不期望的不稳定性。
发明内容
在形成GaNFET通道的二维电子气下面的至少一个III-N半导体层中，包括GaNFET的半导体装置具有n型掺杂质。N型掺杂的载流子面密度遮蔽二维电子气免受其下面的陷阱电荷和图像电荷。
附图说明
图1至图4为包括GaNFET的示例性半导体装置的横截面图。
具体实施方式
下列描述相关主题且在此以引用的方式并入：申请号US13/886,378；US2014/0042452Al；申请号US13/886,429(与此同时提交对应的PCT申请TI-71209WO)；申请号US13/886,652(与此同时提交对应的PCT申请TI-71492WO)；申请号US13/886,709；以及申请号US13/886,744(与此同时提交对应的PCT申请TI-72605WO)。
包括GaNFET的半导体装置在形成GaNFET通道的二维电子气下面的至少一个III-N半导体层中具有n型掺杂。n型掺杂的载流子面密度遮蔽二维电子气免受其下面的陷阱电荷和图像电荷。
III-氮化物(III-N)半导体材料为这样的材料，其中族III(硼族)元素(硼、铝、镓，铟)在半导体材料中提供一部分原子且氮原子提供剩余物。III-N半导体材料的实例为氮化镓、硼氮化镓、铝氮化镓、氮化铟和铟铝氮化镓。III-N材料可用可变下标书写以表示可能的化学计量学的范围。例如，铝氮化镓可写为AlxGa1-xN，且铟铝氮化镓可写为InxAlyGa1-x-yN。GaNFET为包括III-N半导体材料的场效应晶体管的实例。
在一个实施例中，“载流子面密度”为用于感兴趣结构的每单位顶部表面积的自由载流子的净面密度(例如，每平方厘米的载流子)。在第一实例中，二维电子气的载流子面密度是生成二维电子气的阻挡层的顶部表面处一平方厘米下的二维电子气中的电子数量。在第二实例中，n型掺杂层的载流子面密度为n型掺杂层的顶部表面处一平方厘米下的n型掺杂层的传导带中的电子数量。掺杂层的载流子面密度可通过沿垂直轴，垂直于掺杂层的顶部表面，从掺杂层的底部表面到顶部表面对掺杂密度积分(例如，每立方厘米的载流子)进行估计。
降低的表面场(RESURF)区域对降低邻近半导体区域中的电场是有用的。在一个实例中，RESURF区域为具有与邻接半导体区域的导电类型相反的导电类型的半导体区域。在PhilipsJ，Res.351-13,1980(飞利浦杂志，1980年35期1-13)中Appels等人在“ThinLayerHighVoltageDevices(薄层高电压装置)”中描述了RESURF结构。
图1至图4为包括GaNFET的示例性半导体装置的横截面图。参照图1，半导体装置100在基底102上形成，基底102可为，例如，硅片，或其它适于GaNFET制造的基底。失配隔离层104在基底102上形成。失配隔离层104可为，例如，100至300纳米的氮化铝。缓冲层106在失配隔离层104上形成。缓冲层106可为，例如，1至7微米厚且包括AlxGa1-xN分级层的叠层，其在失配隔离层104处富含铝，而在缓冲层106的顶部表面处富含镓。
电隔离层108在缓冲层106上形成。电隔离层108可为，例如，300至2000纳米的半绝缘氮化镓。电隔离层108可为，例如，半绝缘以在电隔离层108下面的层和电隔离层608上面的层之间提供所需水平的电隔离。可替换地，电隔离层108可掺杂有n型或p型杂质以降低电荷陷阱对半导体装置100中的电流密度的不良影响。
低缺陷层110在电隔离层108上形成。低缺陷层110可为，例如，25至1000纳米的氮化镓。低缺陷层110可经形成以便最小化晶体缺陷，所述晶体缺陷可对电子迁移率有不利影响。低缺陷层110的形成方法可导致低缺陷层110掺杂有碳、铁或其它杂质种类，例如，具有少于1017cm-3的掺杂密度。
阻挡层112在低缺陷层110上形成。阻挡层112可为，例如，2至30纳米的AlxGa1-xN或InxAlyGa1-x-yN。阻挡层112中族III元素的组合物可为，例如，24％至28％的氮化铝和72％至76％的氮化镓。在低缺陷层110上形成阻挡层112在正好在阻挡层112下面的低缺陷层110中生成二维电子气，其中具有电子密度即载流子面密度，例如，1×1012至2×1013cm-2。可选择的覆盖层114可在阻挡层112上形成。覆盖层114可为，例如，2至5纳米的氮化镓。可选择的栅极介电层116可在阻挡层112和覆盖层114(如果存在的话)上方形成，从而提供所需的阈值电压。栅极介电层116可包括，例如，氮化硅。
在电隔离层108和/或低缺陷层110的形成过程中，n型杂质被添加以至于电隔离层108和低缺陷层110的载流子面密度为二维电子气下面的陷阱电荷和图像电荷提供屏蔽。在目前实例的一个版本中，电隔离层108和低缺陷层110的载流子面密度可为二维电子气的载流子面密度的10％至200％。
添加的n型杂质可主要包括，例如，硅和/或锗杂质。添加的n型杂质可在电隔离层108和/或低缺陷层110的外延生长过程中添加。可替换地，在形成电隔离层108和/或低缺陷层110后，添加的n型杂质可通过离子注入添加。添加的n型杂质的平均掺杂密度可为，例如，1×1016cm-3至1×1017cm-3。添加的n型杂质的分布可基本均匀，或可被分级以至于掺杂区域底部处的掺杂密度比掺杂区域顶部处的掺杂密度高。
栅极118在阻挡层112和栅极介电层116(如果存在的话)的上方形成。栅极118可包括，例如，III-N半导体材料以提供耗尽型FET。其它类型的栅极在目前实例的范围内。源极触点120经形成延伸到阻挡层112中，以便形成连接到低缺陷层110中的二维电子气的隧穿连接(tunnelingconnection)。类似地，漏极触点122经形成延伸到阻挡层112中，以便形成连接到二维电子气的隧穿连接。栅极118、源极触点120和漏极触点122是半导体装置100的GaNFET124的部分。在目前实例的一个版本中，半导体装置100可包括其它有源组件，诸如除GaNFET124之外的晶体管或二极管。在另一个版本中，GaNFET124可为半导体装置110的唯一有源组件。源极触点120可以与栅极118横向分开，例如，500至1500纳米。漏极触点122与栅极118横向分开一段距离，该距离取决于GaNFET124的最大操作电压。例如，在设计用于200伏特最大操作电压的GaNFET124中，漏极触点122可以与栅极118横向分开1至8微米。在设计用于600伏特最大操作电压的GaNFET124中，漏极触点122可以与栅极118横向分开8至20微米。GaNFET124可在图1描述的层结构中和在不同的层结构上形成。
参照图2，半导体装置200在基底202上形成，失配隔离层204在基底202上形成，缓冲层206在失配隔离层204上形成，且电隔离层208在缓冲层206上形成，例如，如参照图1所述的。在目前实例中，电隔离层208没有如参照图1所讨论的添加的n型杂质。
p型氮化镓层226在电隔离层208上形成。p型氮化镓层226可为，例如，200纳米至1200纳米厚，且可包括低分数的铝和/或铟以匹配电隔离层208的化学计量关系。p型氮化镓层226掺杂有p型杂质，诸如具有1×1017cm-3至8×1019cm-3示例性掺杂密度的镁。P型杂质可在p型氮化镓层226的外延生长过程中添加或在形成p型氮化镓层226后可通过离子注入添加。
低缺陷层210在p型氮化镓层226上形成。低缺陷层210可为，例如，50至1000纳米的氮化镓。N型杂质添加到低缺陷层210以至于低缺陷层210的载流子面密度是随后生成的二维电子气的载流子面密度的1％至200％。p型氮化镓层226的掺杂密度经选择以提供低缺陷层210的载流子面密度的70％至140％的载流子面密度。
例如，参照图1所述，阻挡层212在低缺陷层210上形成。如参照图1所述，在低缺陷层210上形成阻挡层212在低缺陷层210中生成了二维电子气。可选择的覆盖层214可在阻挡层212上形成。可选择的栅极凹处228可在阻挡层212中形成。覆盖层214在栅极凹处228中形成。栅极218，例如，钛钨的金属栅极218，在栅极凹处228中的覆盖层214上形成以提供耗尽型FET。在栅极凹处228中形成栅极218可以提供期望的阈值电压。其它类型的栅极在目前实例的范围内。
漏极触点222在阻挡层212中形成，例如，参照图1所述。源极触点220在阻挡层212中形成以与二维电子气电接触。源极触点220也可选择地与p型氮化镓层226电接触。栅极218、源极触点220和漏极触点222是半导体装置200的GaNFET224的部分。
在半导体装置200的操作过程中，通过低缺陷层210中的添加的n型杂质提供的电子可有利地填充低缺陷层210中的一部分陷阱。P型氮化镓层226可提供RESURF层以有利地降低来自栅极218的电场且因此减少移进和移出陷阱的电子移动。
参照图3，半导体装置300在基底302上形成，失配隔离层304在基底302上形成，缓冲层306在失配隔离层304上形成，且电隔离层308在缓冲层306上形成，例如，参照图1所述。
图形化的P型氮化镓层326在电隔离层308上形成，从源极触点区域延伸，经过栅极区域，且在漏极区域前停止。图形化的P型氮化镓层326的厚度和掺杂特性如参照图2所述。在目前实例的一个版本中，通过植入掩膜，部分p型氮化镓层326可通过离子植入p型杂质到电隔离层308的顶部部分形成，从而转化其为具有所需掺杂密度的p型。在另一个版本中，均厚(blanket)p型氮化镓层可使用外延生长工艺生长，且随后用刻蚀工艺图形化。
低缺陷层310在部分p型氮化镓层326和电隔离层308上形成。低缺陷层310可为，例如，50至1000纳米的氮化镓。在低缺陷层310，和可能电隔离层308的形成过程中，n型杂质被添加以至于低缺陷层310和电隔离层308的载流子面密度为随后生成的二维电子气的载流子面密度的1％至200％。部分p型氮化镓层326的掺杂密度经选择以提供低缺陷层310的载流子面密度的70％至140％的载流子面密度。
例如，参照图1所述，阻挡层312在低缺陷层310上形成。参照图1所述，在低缺陷层310上形成阻挡层312在低缺陷层310中生成了二维电子气。可选择的覆盖层314可在阻挡层312上形成。可选择的栅极凹处328可在阻挡层312中形成。覆盖层314在栅极凹处328中形成。栅极介电层316在覆盖层314(如果存在的话)上方和阻挡层312上方形成。栅极介电层316可为，例如，10至20纳米的氮化硅，其通过低压化学气相沉积(LPCVD)或等离子体增强化学气相沉积(PECVD)形成。在目前实例的其它版本中，栅极介电层316可包括氮化硅、二氧化硅，氧氮化硅和/或氧化铝中的一层或更多层。栅极介电层316在栅极凹处328中形成。金属栅极318在栅极凹处328中的栅极介电层316上形成以提供增强型FET。在栅极凹处328中形成栅极318可提供所需的阈值电压。其它类型的栅极在目前实例的范围内。
参照图2所述，源极触点320在阻挡层312中形成以与二维电子气和部分p型氮化镓层326电接触。例如，参照图1所述，漏极触点322在阻挡层312中形成。栅极318、源极触点320和漏极触点322为半导体装置300的GaNFET324的部分。
在半导体装置300的操作过程中，低缺陷层310中添加的n型杂质可有利地填充如参照图1和图2所述的一部分陷阱。参照图2所述，部分P型氮化镓层326可提供RESURF层以有利地降低来自栅极318的电场。与图2的GaNFET224相比，形成在漏极区前终止的部分p型氮化镓层326可增加GaNFET324的漏极源极击穿电压。
参照图4，半导体装置400在基底402上形成，失配隔离层404在基底402上形成，且缓冲层406在失配隔离层404上形成，例如，参照图1所述。
p型氮化镓层426在缓冲层406上形成。P型氮化镓层426的厚度和掺杂特点如参照图2所述。低缺陷层410在p型氮化镓层426上形成。低缺陷层410可为，例如，50至1000纳米的氮化镓。在低缺陷层410的形成过程中，n型杂质被添加以至于低缺陷层410和电隔离层408的载流子面密度是随后生成的二维电子气的载流子面密度的1％至200％。p型氮化镓层426的掺杂密度经选择以提供低缺陷层410的载流子面密度的70％至140％的载流子面密度。
例如，参照图1所述，阻挡层412在低缺陷层410上形成。参照图1所述，在低缺陷层410上形成阻挡层412在低缺陷层410中生成了二维电子气。可选择的覆盖层414可在阻挡层412上形成。P型III-N半导体栅极418在覆盖层414上形成以提供增强型FET。P型III-N半导体栅极418可包括，例如，AlxGa1-xN或InxAlyGa1-x-yN中的一层或更多层。P型III-N半导体栅极418可包括半导体材料上方的金属层。
参照图2所述，源极触点420在阻挡层412中形成以与二维电子气和p型氮化镓层426电接触。例如，参照图1所述，漏极触点422在阻挡层412中形成。栅极418、源极触点420和漏极触点422是半导体装置400的GaNFET424的部分。
在半导体装置400的操作过程中，低缺陷层410中的添加的n型杂质可有利地填充如参照图1和图2所述的一部分陷阱。参照图2所述，P型氮化镓层426可提供RESURF层以有利地降低来自栅极418的电场。在缓冲层406上形成p型氮化镓层426可有利地降低半导体装置400的制造成本和复杂性。
本领域技术人员应该理解，可对所述实施例进行修改，且也应理解，在本权利要求范围内的许多其它实施例是可行的。

Claims (20)

1.一种半导体装置，其包括：
基底；
在所述基底上方形成的电隔离层，所述电隔离层主要包括氮化镓；
在所述电隔离层上方形成的低缺陷层，所述低缺陷层主要包括氮化镓；
在所述低缺陷层上形成的III-N半导体材料的阻挡层；以及
在所述阻挡层上方形成的氮化镓场效应晶体管即GaNFET的栅极；
其中所述电隔离层和所述低缺陷层中的至少一个包括添加的n型杂质以至于所述添加的n型杂质的载流子面密度为所述低缺陷层中的二维电子气的载流子面密度的1％到200％，所述二维电子气通过所述低缺陷层上所述阻挡层的形成而生成。
2.根据权利要求1所述的半导体装置，且包括在所述电隔离层和所述低缺陷层之间形成的p型氮化镓层，所述p型氮化镓层在所述GaNFET的源极触点下和所述栅极下延伸，所述p型氮化镓层的载流子面密度是所述低缺陷层的载流子面密度的70％到140％。
3.根据权利要求2所述的半导体装置，其中所述p型氮化镓层不在所述GaNFET的漏极触点下延伸。
4.根据权利要求2所述的半导体装置，其中所述p型氮化镓层的p型杂质种类主要为镁。
5.根据权利要求2所述的半导体装置，其中所述GaNFET的源极触点与所述p型氮化镓层电接触。
6.根据权利要求1所述的半导体装置，其中所述电隔离层基本没有所述添加的n型杂质。
7.根据权利要求1所述的半导体装置，其中所述低缺陷层基本没有所述添加的n型杂质。
8.根据权利要求1所述的半导体装置，其中大部分所述添加的n型杂质的n型杂质种类从由硅和锗组成的组中选取。
9.根据权利要求1所述的半导体装置，其中所述添加的n型杂质的n型杂质种类主要是碳。
10.根据权利要求1所述的半导体装置，其中所述添加的n型杂质的所述载流子面密度是所述二维电子气的所述载流子面密度的10％到200％。
11.根据权利要求1所述的半导体装置，其中所述添加的n型杂质的平均掺杂密度为1×1016cm-3到1×1017cm-3。
12.根据权利要求1所述的半导体装置，其中所述添加的n型杂质基本均匀分布。
13.根据权利要求1所述的半导体装置，其中对所述添加的n型杂质分级以便在添加的n型杂质底部处的掺杂密度比所述添加的n型杂质顶部处的掺杂密度高。
14.一种半导体装置，其包括：
基底；
在所述基底上方形成的p型氮化镓层；
在所述p型氮化镓层上方形成的低缺陷层，所述低缺陷层主要包括氮化镓；
在所述低缺陷层上形成的III-N半导体材料的阻挡层；以及
在所述阻挡层上方形成的氮化镓场效应晶体管即GaNFET的栅极；
其中：
所述低缺陷层包括添加的n型杂质以至于所述添加的n型杂质的载流子面密度是所述低缺陷层中的二维电子气的载流子面密度的1％到200％，所述二维电子气通过所述低缺陷层上的所述阻挡层的形成生成；且
所述p型氮化镓层的载流子面密度是所述低缺陷层的所述载流子面密度的70％到140％。
15.根据权利要求14所述的半导体装置，其中所述p型氮化镓层的p型杂质种类主要是镁。
16.根据权利要求14所述的半导体装置，其中所述GaNFET的源极触点与所述p型氮化镓层电接触。
17.根据权利要求14所述的半导体装置，其中所述添加的n型杂质的n型杂质种类主要为硅。
18.根据权利要求14所述的半导体装置，其中所述添加的n型杂质的n型杂质种类主要为碳。
19.根据权利要求14所述的半导体装置，其中所述添加的n型杂质的平均掺杂密度为1×1016cm-3到1×1017cm-3。
20.根据权利要求14所述的半导体装置，其中所述添加的n型杂质基本均匀分布。
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