WO2015175915A1 - Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage - Google Patents

Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage Download PDF

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Publication number
WO2015175915A1
WO2015175915A1 PCT/US2015/031041 US2015031041W WO2015175915A1 WO 2015175915 A1 WO2015175915 A1 WO 2015175915A1 US 2015031041 W US2015031041 W US 2015031041W WO 2015175915 A1 WO2015175915 A1 WO 2015175915A1
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Prior art keywords
current
drift region
region
gates
transistor
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PCT/US2015/031041
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French (fr)
Inventor
Srabanti Chowdhury
Jeonghee Kim
Chirag Gupta
Stacia Keller
Umesh K. Mishra
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The Regents Of The University Of California
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Publication of WO2015175915A1 publication Critical patent/WO2015175915A1/en
Priority to US15/344,377 priority Critical patent/US10312361B2/en

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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
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    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • This invention relates to trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage.
  • one or more embodiments of the present invention disclose novel trenched vertical power field-effect transistor structures with improved on- resistance and breakdown voltage.
  • One or more embodiments of the invention are fabricated by direct wafer-bonding of the drift region to the lateral channel, although other methods of fabrication can be employed.
  • the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state.
  • the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region.
  • One or more embodiments of the present invention further disclose a superjunction current aperture vertical electron transistor (S JCAVET) for ultra-low on-resistance.
  • SJCAVET is a vertical device that is comprised of two parts. One part is a lateral channel that controls current flow from source to drain, wherein this channel may provide conductance via two-dimensional electron gas (2-DEG), a doped channel, or both.
  • the second part is a drift region or a voltage blocking region which carries the current via either a vertical or sloped 2-DEG and/or through an adjacent doped region.
  • the current flow from the lateral channel to the vertical drift region is confined substantially to an aperture defined by one or more current blocking layers (CBLs).
  • CBLs current blocking layers
  • the device voltage blocking layers in the off- state, can be completely depleted at voltages lower than the desired breakdown voltage enabling ultra-low on resistance and high breakdown voltage.
  • One or more embodiments of the invention further disclose the first true vertical GaN based transistors, where the gating is performed also on electrons traveling perpendicular to the surface in a vertical channel.
  • An extremely low drift region spreading resistance is achieved by insertion of a two dimensional electron gas produced at an (Al,Ga,In)N/GaN heterojunction present on either side of the channel (referred to as the trench), significantly improving on the device performance by utilizing the full area of the drift region for conduction.
  • the gating of the device can be either via a MOS structure to create a vertical MOSFET or a p-n junction to create a vertical JFET. Similar to the Current Aperture Vertical Electron Transistor
  • both MOS and JFET have in common that the voltage in the off-state of the device is substantially held in the vertical direction in the n- drift region.
  • the electrically active device area can be equal to the geometric chip area.
  • a vertical transistor e.g., III -nitride device
  • a vertical transistor comprising a lateral channel connected to a drift region; a source contact to the lateral channel; a drain contact to the drift region; and one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact
  • the drift region comprises a current blocking structure; voltage is predominantly held in a vertical direction in an off-state; the current is channeled through an aperture in the current-blocking structure after it flows from under the one or more gates, into the drift region in an on-state; and the one or more gates and/or the current blocking structure (i) induce a two dimensional electron gas at one or more sidewalls of the gates and/or of the current blocking structure, and/or (ii) the current blocking structure comprises different material regions that can provide a compensating charge, wherein the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the
  • the current-blocking structure can be comprised of trenches filled with insulator and metal to provide the compensating charge.
  • the current-blocking structure can be comprised of trenches filled with alternating layers of semiconductor material to provide the compensating charge.
  • the current blocking structure can have the one or more sidewalls adjacent to the current carrying region of the drift region, and be structured such that the one or more sidewalls reduce resistance to the current's flow in the current carrying drift region.
  • the device can comprise a part A bonded to a part B, wherein the Part A comprises the one or more gates, the source, and the lateral channel; the Part B comprises the drift region that carries the current flow via a vertical or sloped two- dimensional electron gas (2-DEG) and along the sidewall; and the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by the current blocking structure.
  • the Part A comprises the one or more gates, the source, and the lateral channel
  • the Part B comprises the drift region that carries the current flow via a vertical or sloped two- dimensional electron gas (2-DEG) and along the sidewall; and the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by the current blocking structure.
  • 2-DEG two- dimensional electron gas
  • the drift region can be a voltage blocking region that can be fully depleted at voltages lower than a desired breakdown voltage.
  • the current blocking structure can have one or more dimensions and materials, and the current-carrying region can have one or more dimensions and doping, such that an electric field held in the current blocking region is less than its breakdown field in the off-state, and the current-carrying region becomes fully depleted in the off- state, thus enabling a breakdown voltage of the device.
  • the gates can deplete the lateral channel adjacent the gates' sidewalls, so that the current flows predominantly from under the gate to the drift region.
  • the device can be a transistor further comprising a first Ill-nitride layer on a second Ill-nitride layer and comprising the lateral channel; a polar c-plane interface and nonpolar and/or semipolar interfaces between the first Ill-nitride layer (e.g., GaN) and the second Ill-nitride layer (e.g., AlGaN); the source contact to the lateral channel; and the drift region, comprising one or more doped Gallium Nitride (GaN) layers, wherein the polar interface is between the drift region and one or more gates.
  • the transistor can further comprise a plurality of trenches in one or more of the Ill-nitride layers, wherein the trenches shape the lateral channel; and one of the gates in each of the trenches.
  • the source contact can form metal regions between the gates and mitigate high field regions at the gate edges, ensuring the peak field is in the bulk of the device.
  • a polarization induced two dimensional electron gas (2DEG) can be formed in regions between the trenches, resulting in the 2DEG which spreads the current efficiently in the drift region to make the full chip area active.
  • the channel comprising the 2DEG along the vertical non-polar (e.g., m-plane) and/or semipolar interfacesis induced only under forward bias on the gates and the 2DEG on the polar c-plane is always present for all operating conditions.
  • the transistor can further comprise a dielectric layer between the gates and the lateral channel, or the dielectric layer between the gates and the second Ill-nitride layer and along the interfaces; and wherein the dielectric provides negligible threshold shift under gate voltages between -10 V and + 10V.
  • the transistor's electrically active device area can be equal to a geometric chip area on which the device is formed and a device having an on resistance of 1 mQcm 2 can have three times smaller chip area for the same R on as a 3mQcm 2 device.
  • the transistor can be a Gallium Nitride (GaN) based vertical transistor, including but not limited to, a vertical metal oxide semiconductor field effect transistors (MOSFET) or a vertical junction field effect transistor (JFET).
  • GaN Gallium Nitride
  • MOSFET vertical metal oxide semiconductor field effect transistors
  • JFET vertical junction field effect transistor
  • One or more embodiments of the invention further disclose a method of fabricating a vertical transistor, comprising depositing a semiconductor structure comprising a lateral channel connected to a drift region; depositing a source contact to the lateral channel; depositing a drain contact to the drift region; depositing one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact; and forming a trench region around a current carrying region of the drift region; and wherein: the trench region comprises a current blocking structure comprising different material layers that can provide a compensating charge, the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in an off-state, modulation of a current from a source to a drain occurs in the lateral channel, voltage is predominantly held in a vertical direction in the off-state, and the current is channeled through an aperture in the current-blocking structure after it flows from under the gates into the drift region in an on- state.
  • One or more embodiments of the invention further disclose a method of fabricating a transistor, comprising growing n-type GaN layers on a GaN substrate to serve as drift and channel layers; growing n ++ GaN on the drift n-type GaN layer to serve as a contact layer; etching trenches in one or more of the GaN layers to form multiple channels in one or more of the GaN layers; growing one or more Ill-Nitride layers on top of the channel GaN layer inside and outside the trenches, growing a first dielectric layer on the Ill-nitride layers inside and outside the trenches; depositing a planar metal layer on the first dielectric layer, etching the metal to leave a metal only in the trenches, wherein the metal forms one or more gates; covering the device with a second dielectric layer; etching the second dielectric to remove a portion of the second dielectric to expose the tops of the channel GaN layer outside the trenches; depositing metal on regions exposed by removal of the second dielectric layer to form
  • One or more embodiments of the invention further disclose a method of fabricating a Gallium Nitride based transistor, comprising growing one or more first III -nitride layers and one or more second III -nitride layers on a Gallium Nitride substrate, wherein polar c-plane interfaces between the first and second Ill-nitride layers are formed, a drift region, comprising one or more doped Gallium Nitride layers, is formed, and a conductive channel is formed; forming nonpolar and/or semipolar interfaces in one or more of the Ill-nitride layers; depositing one or more source contacts to the conductive channel; depositing a drain contact to the drift region, depositing one or more gates that modulate the conductive channel formed at the interfaces and a current passing through the conductive channel between the source contacts and the drain contacts, wherein: a polar interface is between the drift region and the one or more gates, the current from the source contact to the drain contact spreads laterally in the drift region in an on-state of
  • FIG. 1 is a schematic of the device structure according to one embodiment of the present invention.
  • FIG. 2 is a schematic of a first modified design of the device structure.
  • FIG. 3 is a schematic of a second modified design of the device structure.
  • FIGS. 4(a)-4(f) illustrate a method of fabricating a semiconductor device, showing how to fabricate the device shown in FIG. 1.
  • FIG. 5 is a schematic of a proposed semiconductor device according to one embodiment of the present invention.
  • FIG. 6 shows the schematic of FIG. 1 divided into two regions labeled as Part A and B.
  • FIG. 7 shows Part A of FIG. 6 further sub-divided into regions labeled as Regions 71, 72 and 73.
  • FIG. 8 shows Part B of FIG. 6 further sub-divided into regions labeled as Regions 84, 85, 86, 87,88 and 89.
  • FIG. 9(a)-(c) show Region 85 of FIG. 8 further defined as a trench region including modulation doping.
  • FIG. 10 is a cross-sectional schematic of a device illustrating limitations of a SiC MOSFET are effectively addressed by GaN based devices, and showing Source (S), Drain (D), and gate (G) contacts.
  • FIG. 11 is a cross-sectional schematic of a CAVET showing current modulation laterally under the gate with electrons flowing through the aperture vertically into the drain.
  • FIG. 12 is a cross-sectional schematic of a Vertical MOS transistor with a highly conductive lateral two dimensional electron gas (2DEG) to reduce drift region spreading resistance.
  • 2DEG highly conductive lateral two dimensional electron gas
  • FIG. 13 shows cross-sectional schematics illustrating a Vertical Metal Oxide Semiconductor High Electron Mobility (MOSHEMT) process flow where the 2DEG along vertical m-plane is induced only under forward bias on the gate and the 2DEG on the c-plane is always present for all operating conditions.
  • MOSHEMT Vertical Metal Oxide Semiconductor High Electron Mobility
  • FIG. 14 plots capacitance per centimeter square (microfarads per centimeter square, ⁇ /cm 2 ) as a function of gate bias (Volts, V), showing a first pair of upward and downward sweeps measured with an additional 10 minute stress in accumulation for a MOS capacitor (MOSCAP) with 25 nanometers (nm) AI 2 O 3 grown in-situ by Metal Organic Chemical Vapor Deposition (MOCVD) at 1000 °C.
  • MOSCAP MOS capacitor
  • MOCVD Metal Organic Chemical Vapor Deposition
  • FIG. 15 is a flowchart illustrating a method of fabricating a device according to an embodiment of the invention.
  • FIG. 16 is a flowchart illustrating a method of fabricating a device according to another embodiment of the invention.
  • FIG. 17 is a flowchart illustrating a method of fabricating a device according to a further embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION
  • One or more embodiments of present invention relate to novel vertical power low-loss semiconductor devices attainable by direct wafer-bonding, wherein the modulation of the current flow of the transistor occurs in a lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state.
  • the current is channeled through an aperture in a current- blocking region after it flows under the gate region into a drift region.
  • the current-carrying region in the drift region carries current either in a 2-dimensional or 3 -dimensional manner.
  • 2- dimensional vertical conduction along channels with high mobility will provide additional benefits such as an increase in device speed as well as a reduction in on- resistance (RO N ), thereby providing a design with benefits superior to Si-based superjunction-based field-effect transistors.
  • the main current-blocking region is based on, but not limited to, a metal- insulator combination. This region is fabricated by filling up the trenches with desired types and thicknesses of insulator and metal, respectively.
  • the insulator is deposited in a manner such that it is thicker at the bottom of the trench and thinner at the sidewalls, which simultaneously provides increased breakdown voltage (V BR ) and reduced RO N from the device.
  • the metal/insulator interface in the current-blocking region holds a sheet charge of the opposing polarity to that of the current-carrying region; thus, it fully compensates for the ionized dopant concentration in the current- carrying region. Therefore, the dimension of the insulator, as well as the doping and dimensions of the current-carrying regions, should be determined such that the electric field held in the insulator is much less than its breakdown field in the off-state. When this condition is met, the current-carrying region becomes fully depleted, thus enabling a high V BR of the device.
  • a laterally conductive channel material is directly wafer-bonded (i.e. strong bonds are formed between the separately grown, high- quality wafers by applying heat and pressure) to fabricate the desired device.
  • This lateral carrier flow can also be either 2-dimensional or 3 -dimensional depending on its design, but a 2-dimensional lateral conduction is preferred due to the advantages aforementioned in the description of 2-dimensional vertical conduction in the drift region and also in its ability to control the threshold voltage of the gate.
  • the source and gate electrodes are formed on the lateral wafer-bonded channel and the drain electrodes on the highly conductive bottom layer of the drift region, respectively.
  • the source electrodes are also connected to the metal that fills up the MIS-based current-blocking regions.
  • a lateral channel on top of a template that is comprised of a current-carrying region surrounded by current-blocking regions resembles the invention of the Current Aperture Vertical Electron Transistor (CAVET) [Ref. 1].
  • CAVET Current Aperture Vertical Electron Transistor
  • the lateral channel material for the case of a CAVET, is regrown by heteroepitaxy on its template.
  • the choice of the template material imposes no restriction on the choice of the lateral channel material. This gives an extra degree of freedom in terms of selecting the best material to be applied for each section of the structure to maximize the device performance.
  • Successful implementations of wafer-bonding in fabricating electrically active heterojunctions have been reported previously [Ref. 2- 4]. Further, the extension of deep MIS-gated regions into the drift region results in significant loss reduction.
  • the proposed structure can be constructed without bonding the lateral channel to the vertical drift region.
  • the deep trench can be formed after the material growth of the current carrying regions of the full device is completed.
  • This embodiment is enabled by the use of wafer-bonding technique, which can be performed at much lower temperatures than typical heteroepitaxy, allowing for the use of metal fillings in the trenches for the current-blocking regions. Therefore, the proposed MIS-based current-blocking regions can be implemented based on wafer- bonding and provide an enhanced V BR - along with a superior on-state performance (e.g. low RO N , high current) due to the 2-dimensional carrier flow - in comparison to other conventional transistors for high-power applications.
  • the device if electrons are chosen as the majority carrier, is termed a FABET (Fully Apertured Bonded Vertical Electron Transistor), representing that both the current and the voltage in the device are apertured.
  • This invention with a potentially very high breakdown voltage, as well as a superior on-state performance, is an excellent candidate for high-power switching applications. It will become further attractive for such applications by an
  • enhancement-mode i.e. normally off
  • the carriers originating from the source electrodes 14, flow through the lateral channel as a 2-dimensional flow 11 with a very low resistance. They are modulated at the overlap regions between the gate electrodes 15 and the current-blocking regions 3. Because of the electric field set up by the drain electrode 16 at the bottom of the device, the carriers are swept vertically through the aperture 12 by turning the corners of the current-blocking regions 3. Then, they flow through the current-carrying region 1 as a substantially 2-dimensional flow 6, again with an extremely low resistance, and reach the drain electrode 16 at the bottom.
  • the sheet charge at the interface of insulator-metal 7a-8 that fills up the trenches for forming the current-blocking regions 3 should appropriately compensate for the ionized dopants in the (relatively lowly doped or unintentionally doped) current- carrying region 1 without breaking down the insulator.
  • the thick insulator 7b at the bottom of the trench should be designed such that it supports the voltage in the off-state per device specifications. Therefore, a very low RO N (due to both the lateral and vertical 2-dimensional conduction with high mobility), as well as a very high breakdown voltage (due to the MIS-based current-blocking regions along with the use of a high breakdown material in the drift region), can be achieved in this device.
  • the device structure can be divided into two portions: the drift region A and the lateral channel B, as shown in FIG. 1, the two of which are wafer-bonded to one another in this embodiment. If the materials in region A and B can be grown epitaxially, then that interface need not be bonded.
  • the template possesses similar features to that of typical superjunction power devices, with alternating current-carrying and current-blocking regions that extend toward the bottom conductive layer 2, which is connected to the drain electrode 16.
  • a template grown on a conductive substrate is preferred, but it is also possible to place the drain electrode 16 laterally away from the bottom of the current-carrying region when using an insulating substrate or remove the substrate, whether it is conducting or insulating (examples include sapphire, ZnO, GaN, Ga 2 0 3 , SiC, Si, etc.).
  • FIG. 1 depicts a device fabricated on a conductive substrate.
  • the drift region For applications related to high-power operations, the best choice for the drift region would be a semiconductor material with a high breakdown electric field.
  • An example is an III-N material, although this structure can also be implemented in conventional elemental and compound semiconductors.
  • the current-carrying region 1 can be doped either n- or p-type: (1) uniform doping; (2) abruptly changed doping; or (3) graded doping.
  • the doping can be intentional or unintentional; it is not necessary to intentionally dope the region 1.
  • the electron concentration is designed to ensure depletion in all of the relevant regions and to obtain a lower peak electric field under the device off-state while maintaining a low on-resistance in the on-state.
  • variations in doping concentration throughout the current-carrying region i.e. as a function of both x and y as identified in FIG. 1) can be accommodated for enhanced conductivity and/or adjusting the electric field distribution in the device structure.
  • An important feature of this invention is the accommodation of a 2- dimensional carrier flow 6 in its vertical direction.
  • One way to achieve this is by a modulation doping 5 in the barrier material 4, which is regrown after the formation of trenches in the drift regions and will become a part of the MIS-based current-blocking regions.
  • a use of semiconductor material that is polar in the horizontal direction i.e. the x direction in FIG. 1) can be utilized such that the 2-dimensional carrier gas 6 is formed without substantial doping, but instead by polarization-induced charges.
  • the existence of 2-dimensional carriers 6 is very beneficial to reducing RO N , and it allows for even lower doping levels in the current-carrying region 1 without compromising RO N , thus resulting in an even higher V BR of the device.
  • Another important feature of this invention is the design of the current- blocking region that is comprised of an insulator-metal 7a,b-8 combination, which is placed adjacent to the aforementioned barrier material 4 that induces 2-dimensional carriers 6.
  • the sidewall insulator 7a blocks potential leakage between the metal 8 and the current-carrying region 1 and, under bias, supports the desired voltage per device specifications. Therefore, both the thickness of the insulator 7a as well as the doping and dimensions of the current-carrying region 1 should be designed such that the insulator can easily support the voltage required to completely deplete the region 1.
  • the insulator 7b is much thicker toward the bottom of the trenches than the sidewall insulator 7a, and this plays a critical role in significantly enhancing the V BR of the device.
  • Insulators 7a and 7b may be the same insulator or different insulators. It is important to determine the thickness d of insulator 7b such that the electric field held across the insulator in the off-state is not greater than the breakdown field of the insulator itself.
  • the trenched current-blocking layer extends down toward the highly conductive bottom layer 2, which represents either the conductive substrate or a highly doped layer grown on the substrate.
  • the depth of the current-blocking region i.e. depth of trench
  • FIG. 1 depicts a case of the current- blocking region that extends deeper into the highly conductive layer 2.
  • the dimensions di and d 2 should be appropriately adjusted such that the imposed tradeoff between the offered benefits in low RO N and high V BR is optimized.
  • Another type of current-blocking region 3, which defines the aperture 12, can be accommodated as desired.
  • the current flowing in the lateral channel B would be modulated where the current-blocking region 3 and the gate metal 15 overlap.
  • Its current-blocking (i.e. insulating) property can be obtained by (1) ion implantation, (2) employment of a material with an opposite doping type compared to the current-carrying region 1, or (3) insertion of a material that provides a high barrier height to the channel carrier type (e.g. insulator, semiconductor with a much higher bandgap, air-gap, etc.). Its location, as well as dimensions, can be optimized in a manner that it allows for a smooth transition of the lateral carrier flow 11 to the vertical flow 6 near the aperture 12.
  • the channel 9 preferably is comprised of a 2-dimensional carrier flow 11 , which ensures higher mobility of the carriers.
  • the 2-dimensional carrier in the channel can be realized either by accommodating a modulation doping in the barrier material 10 or by polarization engineering if a polar semiconductor such as III-N is implemented.
  • the interface 13 identifies the borderline between the drift region A and the lateral channel B, and may be an epitaxial or wafer-bonded interface .
  • the best choice for the lateral channel material would be a semiconductor material that offers high mobility for the majority carrier to enhance the device speed and on-state performance, including RO N , without presenting a barrier to carrier transfer across the wafer-bonded interface 13.
  • the source electrodes 14 are designed such that, in one embodiment, they contact the carriers in the lateral channel as well as the metal 8 that fills up the MIS- based current-blocking regions. Moreover, optional source and/or gate-connected field plates can be placed over the gate metal 15 after depositing the passivating insulator layer to further enhance the breakdown voltage.
  • the geometry of the gate electrode 15 can be varied. For instance, it can be defined by a uniform metallization (as shown in FIG. 1) or by a split-design metallization, where the flow of current from either source is modulated by physically separated gates (which may be electrically connected).
  • the transistor shown in FIG. 1 depicts a depletion-mode (i.e. normally on) device. However, its gate design can be altered such that it operates as an
  • enhancement-mode i.e. normally off
  • a fluorine-based treatment underneath the gate electrodes, recessed gate region, or doping of the gate barrier material with an opposite dopant type from the channel (e.g. p-type gate barrier for n-channel), etc.
  • FIG. 1 illustrates a semiconductor device, comprising a vertical device that is comprised of a lateral channel B bonded to a drift region A; wherein modulation of a current from a source 14 to a drain 16 occurs in the lateral channel B; voltage is predominantly held in a vertical direction in an off-state; and the current is channeled through an aperture 12 in a current-blocking region after it flows under a gate region 15 into the drift region A in an on-state.
  • FIG. l further illustrates the source and gate can be formed on the lateral channel B and the drain 16 can be formed on the drift region A.
  • the current-blocking region can be comprised of trenches filled with insulator 7a-b and metal 8, wherein the insulator 7b is thicker at a bottom of the trench and the insulator 7a is thinner at sidewalls of the trenches. c. Possible Modifications and Variations
  • FIG. 2 depicts a modified design of the MIS-based vertical power transistor.
  • the drift region Al is prepared by firstly etching off parts of the highly conductive layer 2 to form the voltage-holding regions, which are subsequently filled with dielectric 7b. After a planarization (if needed), the drift region A2 is either wafer- bonded to or regrown on the drift region Al . The interface 17 identifies the borderline between the two regions. As a result, the dielectric 7b (with a predetermined optimal thickness d) is placed fully within the highly conductive layer 2.
  • the remaining device regions A2 and B are identical to the regions A and B of the device structure shown in FIG. 1.
  • This invention also discloses the addition of spacers (e.g. rounded spacers with a radius of ⁇ d in the case of FIG. 2) to further enhance the breakdown voltage of the device. This is to address the device breakdown path in the off-state between the metal filling 8 and the highly conductive region 2.
  • the shape and dimensions of these spacers is based on device specifications, but are intended to minimize peaking of deleterious electric fields in the structure, which can reduce breakdown.
  • FIG. 3 shows another permutation of the proposed vertical power transistors. It features Schottky barrier based sidewalls 8, which are connected to the source regions of the devices (not shown in the figure). In the off-state, the depleted ionized (intentional or unintentional) dopants in the current-carrying region 1 would image on the sidewall metal 8. All of the regions Al, A2, and B can be either wafer-bonded to or regrown on each other.
  • the thickness d 3 of the dielectric material 7c (which can be the same as or different from the buried dielectric 7b) is another design knob available in the structure, and it can be varied from zero to any desired thickness to further enhance the overall device performance. d.
  • a template A comprised of layers 1 , 2 with desired doping concentrations and thicknesses is grown, preferably, on a conductive substrate.
  • the current-blocking regions 3 are formed by one of the aforementioned insulating methods, i.e., (1) ion implantation, (2) employment of a material with an opposite doping type compared to the current-carrying region 1, or (3) insertion of a material that provides a high barrier height to the channel carrier type (e.g. insulator, semiconductor with a much higher bandgap, air-gap, etc.) and thus define the aperture 12 of the device.
  • the channel carrier type e.g. insulator, semiconductor with a much higher bandgap, air-gap, etc.
  • the trenches are firstly formed by etching (shown in FIG. 4(a)), and subsequently a desired type of insulator 7b is deposited such that the trenches become completely filled (shown in FIG. 4(b)).
  • the insulator is dry-etched until its remaining thickness at the bottom is close to the desired thickness d (shown in FIG. 4(c)).
  • a layer of barrier material 4 (either modulation doped 5 or polarization-engineered or both) that induces 2-dimensional carriers 6 of a desired conductivity type in the drift region is deposited (shown in FIG. 4(d)), preferably using a selective regrowth method such as metalorganic chemical vapor deposition (MOCVD).
  • MOCVD metalorganic chemical vapor deposition
  • the insulator 7a is then deposited until it reaches the desired thickness for the trench sidewalls (shown in FIG. 4(e)); thus, this second deposition forms the sidewall layers for the MIS junctions in the current-blocking regions.
  • a desired type of metal 8 is deposited, which fills up the remaining regions of the trenches, thereby completing the current- blocking regions of the template (shown in FIG. 4(f)). It is noted that the process steps other than those represented in FIG. 2 can be also used to produce the identical current-blocking region profile. If necessary, a planarization of the template takes place to prepare a flat surface for wafer-bonding it to the lateral channel B. Post a low-temperature wafer-bonding process that does not alter the MIS junctions (especially metal) in the template, appropriate processes for source, gate, and drain regions are performed to complete the fabrication.
  • III-N based drift region There are some process developments that will play a critical role in successfully fabricating the proposed device with a III-N based drift region. These include III-N deep trench etching technique for current-blocking regions and sidewall AlGaN regrowth to achieve 2-dimensional vertical flow in the current-carrying regions. II. Superjunction Current Aperture Vertical Electron Transistor for Ultra-
  • One or more embodiments of the present invention disclose a semiconductor multi-junction device in Ill-nitride and non-III-nitride material systems, which aims at providing ultra-low on-resistance along with high breakdown voltage.
  • the proposed semiconductor device is a vertical device, namely, an SJCAVET that is comprised of two parts, namely, Parts A and B.
  • Part A of the device comprises a channel which controls current in the lateral direction by modulating a two-dimensional or three-dimensional channel. It contains at least one source and one gate.
  • Part B of the device is a drift region, which is a voltage blocking region that contains a substantial part of the blocked voltage in the off-state in the vertical dimension.
  • Current blocking layers form an aperture to restrict current flow from source to drain to the aperture from where it spreads to other conductive parts of the drift region.
  • the current blocking layers can be formed by or comprise either p-type regions, wide bandgap materials, insulators or any dielectric including air-gaps.
  • This vertical 2-DEG is achieved by modulation doping an AlGaN layer which is adjacent to the current carrying drift region.
  • the 2- DEG could be formed because of polarization differences.
  • Positive fixed charges of any form can be used to induce a 2-DEG in the drift region.
  • the device also has trenched p-n junctions which fully deplete laterally (x- direction) on applying a drain voltage substantially smaller than the breakdown voltage of the device. This allows the voltage to be held from source to drain in a region which has substantially a constant electric field in the y-direction rather than the decreasing electric field typical for doped drift regions. This is a phenomenon similar to Si superjunction devices.
  • FIG. 5 is a schematic of a proposed semiconductor device according to one embodiment of the present invention, illustrating a superjunction current aperture vertical electron transistor (SJCAVET) for ultra-low on-resistance, comprising a lateral channel (comprising 2-DEG inducing layers 500 and layer 502 comprising n(x,y) GaN) that controls current flow from source S to drain D, wherein this channel may provide conductance via two-dimensional electron gas (2-DEG), a doped channel, or both.
  • the device further comprises drift region or a voltage blocking region which carries the current via either a vertical or sloped 2-DEG and/or along with current through an adjacent doped region 504 comprising n(x,y) GaN.
  • the current flow from the lateral channel to the vertical drift region is confined substantially to an aperture 506 defined by one or more current blocking layers (CBLs).
  • CBLs current blocking layers
  • the proposed semiconductor device shown in FIG. 5 could be broadly divided into two regions labeled as Part A and B as shown in FIG. 6.
  • FIG. 6 illustrates a semiconductor multi-junction device, comprising the vertical device that is comprised of Parts A and B, wherein the Part A comprises at least one gate G, at least one source S, and the lateral channel that controls a current flow from the source S to a drain D; the Part B comprises a drift region that carries the current flow via a vertical or sloped two-dimensional electron gas (2-DEG) and along a sidewall 600; and the current flow from the lateral channel to the drift region is confined substantially to an aperture 506 defined by one or more current blocking layers (CBLs).
  • the Part A comprises at least one gate G, at least one source S, and the lateral channel that controls a current flow from the source S to a drain D
  • the Part B comprises a drift region that carries the current flow via a vertical or sloped two-dimensional electron gas (2-DEG) and along a sidewall 600; and the current flow from the lateral channel to the drift region is confined substantially to an aperture 506 defined by one or more current blocking layers (C
  • the part A is comprised of a channel that controls current in the lateral direction, and the least one gate G can be single, multiple or split gated, for example.
  • a 2-DEG is shown to be the sole current carrying region in Part A, although the channel could also have three-dimensional conductivity.
  • Part A can be further sub-divided into regions labeled as Regions 71, 72 and
  • Source contact (Region 71) to the 2-DEG is ohmic and acts as a source for electrons in the channel region.
  • the ohmic source contact can be achieved by multiple methods, such as regrowth, anneal, etc.
  • Region 72 provides the 2-DEG in the channel. This could be achieved in multiple ways, for example, by having a wide band gap material with a positive polarization interface followed by a lower band gap material. In absence of polarization, modulation doping can also be utilized to obtain the 2-DEG.
  • the main purpose of the layered structure in Region 72 which may comprise a single layer of c-plane (1000) AlGaN or multiple layers of AlGaN/AlN/GaN, is to induce 2-DEG in the channel.
  • Region 73 which is the region under the gate, modulates the charge in the 2- DEG channel, and thus controls the current flow.
  • the device may comprise a metal- oxide-semiconductor (MOS) structure with oxide, dielectric, or other wide band gap material buried under the gate (with an oxide shown in the figures).
  • MOS metal- oxide-semiconductor
  • the thickness of the oxide, dielectric, or other wide band gap material, is variable.
  • the doping concentration in Region 3 could be variable to meet design criteria.
  • the device shown is a depletion mode device (negative threshold
  • Part A All dimensions in Part A are variable and can be altered to meet design criteria.
  • Part B is shown in FIG. 8, and includes the drift region, as well as the drain.
  • Part B can be further sub-divided into regions labeled as Regions 84, 85, 86, 87, 88 and 89.
  • Region 84 is comprised of a current blocking layer (CBL).
  • CBL current blocking layer
  • the function of the CBL is to act as barrier to carrier flow through the CBL, thereby forcing and/or directing the source current from Part A through the gated region into the aperture in Part B, wherein this current is modulated by the lateral gate.
  • the CBL could be actualized by ion implantation, growth, insulating material, p-type GaN, and other methods. Aperture width could be varied to meet design criteria.
  • the dimensions of the current blocking layer are variable and can be altered to meet design criteria.
  • the current blocking layer is followed by the trenched structure (Region 85).
  • the trench could be angled and the ⁇ (theta) angle could vary from 5 degrees to 175 degrees from the horizontal plane.
  • the ⁇ (delta) spacing shown in the FIG. 8 could be positive, negative or zero, wherein the ⁇ represents the overlap of the trenched structure with the current blocking layer.
  • This trenched structure provides the opportunity to get a 2-DEG along the sidewalls 600, which is essential in reducing on-resistance.
  • the 2-DEG on the sidewalls could be achieved by modulation doping (shown as the dotted line along the trench structure).
  • the polarization charge at the interface between the wide band gap material followed by lower band gap material can provide the 2-DEG.
  • Graded polar regions can also be employed, so called 3-DEGs.
  • Region 5b) is comprised of opposite conductivity semiconductor to Region 86.
  • the lateral p-n junction formed between Regions 85 and 86 in Part B gets fully depleted, forming a space charge region, wherein the vertical electric field is substantially constant, unlike the decreasing electric field in one-dimensional n-type semiconductors. This leads to the highest breakdown voltage with the lowest on-resistance.
  • Region 5b) can be variably p-type doped in both the x and y directions to allow for the compensating charges 508 and to control the electric field.
  • variable p-type doping is difficult to control, a different method to achieve effective p-type doping may also be used. Specifically, the concept of super- lattice or multi-layer structures with modulation or uniform doping can be utilized to obtain compensating charges in the trenched structure shown in FIG. 9(a)-(c).
  • Alternating layers of modulation doped higher band gap material followed by lower band gap material would form the super-lattice or multi-layer structure and thus provide the necessary compensating charges.
  • FIG. 9(b) illustrates a variation of FIG. 9(a) comprising GaN layers 900 and AlGaN layers 902 that are uniformly doped with acceptors (Mg), wherein an AlGaN layer 902b is modulation doped with Si 904.
  • FIG. 9(c) illustrates a variation of FIG. 9(a) comprising GaN layers 906 and AlGaN layers 908, wherein AlGaN layers 908 are modulation doped with Mg 910 and AlGaN layer 908b is modulation doped with Si 912.
  • wider band gap material or narrow band gap material (well), or both wider band gap material (barrier) and narrow band gap material (well) can be doped (either modulation doped or uniformly doped with acceptors) to meet design criteria.
  • Different carrier concentration can be achieved by varying the dimensions, spacing, doping and number of the layers.
  • Polarization fields if available can also be utilized in super-lattices to provide the necessary charges for charge compensation.
  • the current blocking layer and p-type semiconductor region in the trenched structure can be electrically connected such that, in operation, there is no bias between them as shown in FIG. 5.
  • Region 86 shown in FIG. 8 is generally n-type with variable doping in both the x and y directions.
  • Region 87 is also of the same conductivity type as Region 86. Region 87 allows the spread of the current from 2-DEG towards the drain contact. Region 87 can also hold the blocking voltage, depending on the doping and thickness of the region. This may or may not involve the same semiconductor as in Region 86. The thickness of Region 87 is variable from zero to any positive value.
  • Region 88 is a highly conductive layer providing good ohmic contact to the drain (Region 89).
  • Parts A and B into the semiconductor device shown in FIG. 5 creates the aperture to allow the flow of current and can be achieved in multiple ways:
  • Part A can be regrown on top of Part B. This may or may not involve the same semiconductor in Regions 73, 84 and 86.
  • Part A can be wafer bonded to the top of Part B. Again, this may or may not involve the same semiconductor in Regions 73, 84 and 86. Bonding can be achieved in different ways.
  • This structure can be realized in different shapes and forms such as cylindrical, hexagonal and other geometries.
  • the source contact only contacts the CBL.
  • the source contact can also contact the p-type region below, including, but not limited to, the super-lattice or multi-channel region.
  • a semiconductor device can provide ultra- low on resistance with high breakdown voltage.
  • a semiconductor device can achieve low loss, reducing a major cost of a power converter system, the heat sink and enabling system-design flexibility.
  • III. GaN based vertical metal oxide semiconductor (MPS) transistors and junction field effect transistors (TFETS)
  • FIG. 10 illustrates Source S, Drain D, Gate G, inversion layer 1000, dielectric 1002, n " SiC, n + SiC, p-type region p, and n + type region p.
  • Contacts to SiC have a contact resistance of ⁇ 1 mflcm 2 whereas a GaN device can have low contact resistance made to n GaN.
  • the inversion layer has a contact resistance of ⁇ 1 mflcm 2 whereas a GaN device can comprise a 2DEG, high mobility channel.
  • the drift resistance in SiC is ⁇ 1 mQcm 2 whereas a GaN device can have a unique device structure to reduce drift resistance.
  • one or more embodiments of the invention propose a true vertical transistor, where the gating is also performed on electrons traveling perpendicular to the surface in a vertical channel (different from a CAVET, illustrated in FIG. 11).
  • FIG. 11 is a cross-sectional schematic of a CAVET showing current modulation laterally under the gate G with electrons flowing 1100 through the aperture 1102 (formed by Magnesium (Mg) implant 1104) vertically into the drain 1106. Also shown are n-type GaN (n GaN) layer 1108, n-type GaN (n + GaN) layer 1110, and source S contact.
  • n GaN n-type GaN
  • n + GaN n-type GaN
  • an extremely low drift region spreading resistance is achieved by the insertion of a two dimensional electron gas (2DEG) produced at the AlGaN/GaN heterojunction present on either side of the channel (the trench region 1200).
  • 2DEG two dimensional electron gas
  • the device comprises Source S, Drain D, n ' GaN layer 1202, n + GaN layer 1204, 1206, dielectric 1208, AI 2 O 3 , AlGaN layer 1210, vertical current flow 1212, 2DEG 1214 on either side of the channel, 2DEG 1216, and depleted region 1218.
  • the gating of this device can be either via a MOS structure to create a vertical MOSFET as is shown in FIG. 12, or a p-n junction to create a vertical JFET, where the p-region may be created by ion implantation and activation.
  • MOSFET MOSFET
  • embodiments of the invention have the ability of depositing the dielectric by high vacuum Atomic Layer Deposition (ALD), by MOCVD, by Chemical Vapor Deposition (CVD), or in-situ by MOCVD, for example.
  • ALD Atomic Layer Deposition
  • MOCVD Chemical Vapor Deposition
  • MOCVD Chemical Vapor Deposition
  • An alternate approach addresses epitaxially grown p-type regions.
  • FIG. 12 shows an embodiment of a normally-off Vertical MOSFET wherein the built-in voltage of the side gates fully deplete (depleted region 1218) the vertical channel in between.
  • Depletion-mode Vertical MOSFETs can be also fabricated. An example of the fabrication process is described below and shown in FIG. 13.
  • the first 6 um of GaN (doped n-type at 5xl0 15 cm ⁇ 3 ) are epitaxially grown on GaN substrates to serve as the drift and channel layer, followed by 0.5 ⁇ of epitaxial n ++ GaN or n + GaN to serve as a contact layer or layers, as shown in FIG. 13a.
  • 1.5 ⁇ deep multiple channels are formed using photolithography and dry etch techniques (Mask M, FIG.13b).
  • a blanket regrowth of AlGaN is then conducted.
  • a polarization induced 2DEG is formed in the regions between the channels (trench regions) resulting in a high conductivity two dimensional electron gas (2DEG) which spreads the current efficiently in the drift region to make the full chip area active (FIG. 13c).
  • Channels with either no or small 2DEG densities are formed along the sidewalls because of their non-polar or semi-polar nature enabling normally-off operation.
  • the regrowth is either followed by an in-situ growth of ⁇ 1 2 0 3 dielectric, or by an ex-situ technique such as ALD (FIG.13c). In the latter case, appropriate care to remove unintentional Si at the regrowth interface will be implemented [7].
  • FIG. 14 shows initial work done at the University of California, Santa Barbara
  • 1 micrometer (um) of Ti/Al (high workfunction metal 1300) is sputtered over the entire sample (FIG. 13d).
  • the spacing of the channels is designed to be 2 ⁇ . This enables the metal to be planar over the full sample.
  • a blanket etch is carried out to remove 1 micron of Aluminum (Al), leaving behind a gate length of 1 micron on the sidewalls (FIG.13e).
  • the device is covered with dielectric 1302 (FIG.13f).
  • a blanket-etch to remove a portion of the dielectric to expose the tops of the channels is then performed.
  • the AlGaN layer can be replaced by InAIN or any (B,Al,Ga,In)N layer, and the AI 2 O 3 can be replaced by any other dielectric, for example S1 3 N 4 or Si0 2 , or higher k dielectrics.
  • Incorporating no heterojunction material is also an embodiment which leads to a Vertical MOSFET and any of the above dielectrics maybe used as an example.
  • the process flow can be modified in any suitable other way to fabricate the device.
  • any other suitable growth technique can be used, for example molecular beam epitaxy (MBE) or chemical beam epitaxy (CBE), or hydride vapor phase epitaxy (HVPE), or a combination of different growth techniques.
  • MBE molecular beam epitaxy
  • CBE chemical beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • all materials can be (Al,Ga,In)N of constant or varying
  • FIG. 15 illustrates a method of fabricating a vertical transistor.
  • Block 1500 represents forming (e.g., depositing and/or bonding) a
  • the step can comprise bonding a part A to a part B, wherein the part A comprises the lateral channel and the Part B comprises the drift region.
  • the step can comprise growing Ill-nitride layers, comprising a channel region and a drift region, on or above a Gallium Nitride substrate.
  • the step can comprise growing/depositing one or more first Ill-nitride layers and one or more second III- nitride layers on or above a Gallium Nitride substrate to form the lateral channel, the drift region, and a contact layer, and for example, wherein polar c-plane interfaces between the layers are formed.
  • the drift region can comprise one or more doped III- nitride layers (e.g., Gallium Nitride layers), on a Gallium nitride substrate.
  • the step can comprise depositing a first Ill-nitride layer on a second Ill-nitride layer and comprising the lateral channel.
  • the channel region or conductive channel can comprise a two dimensional electron gas (2DEG) confined in the Ill-nitride layers, or confined in the first Ill-nitride layer by the interfaces with the second III- nitride layer.
  • the first Ill-nitride layer can be (e.g., doped) GaN and the second III- nitride layer can be AlGaN.
  • the first Ill-nitride layer can be grown on the drift region.
  • the lateral channel can provide conductance via a two-dimensional electron gas and/or a doped channel.
  • the drift region and channel region can be n-type.
  • the channel region can comprise a junction between a p-type region and an n-type region in the III -nitride layers, or the interfaces in the lateral channel can comprise junctions between a p-type region and an n-type region, wherein the p-type region is in the first Ill-nitride layer and the n-type region is in the second Ill-nitride layer, or the n-type region is in the first Ill-nitride layer and the p-type region is in the second III -nitride layer of the lateral channel.
  • Block 1502 represents forming one or more trench regions in the
  • the step can comprise forming a trench region around a current carrying region of the drift region, wherein the trench region comprises a current blocking structure comprising different material layers that can provide a compensating charge, and the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in the off-state.
  • the current-blocking structure can be comprised of trenches filled with insulator and metal, e.g., wherein the insulator is thicker at a bottom of the trench and thinner at sidewalls of the trenches.
  • the current-blocking structure can be comprised of trenches filled with alternating layers of (e.g., different) semiconductor material (e.g., alternating layers of different Ill-nitride material, e.g., alternating AlGaN and GaN layers).
  • the current blocking structure can comprise one or more sidewalls adjacent to a current carrying region of the drift region, and be structured such that the one or more sidewalls reduce resistance to the current's flow in the current carrying drift region.
  • the trench regions can be such that current flow can be carried via a vertical or sloped two-dimensional electron gas (2-DEG) and along the sidewall; and the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by the current blocking structure.
  • 2-DEG two-dimensional electron gas
  • One or more trenches can be formed in the Ill-nitride layers, wherein the trenches shape the lateral channel.
  • one or more trench regions in III- nitride layers of the semiconductor structure can be formed such that a polar c-plane interface and nonpolar and/or semipolar interfaces (e.g., m-plane interface) are between the first Ill-nitride layer and the second III -nitride layer forming the lateral channel and/or 2DEG.
  • Block 1504 represents depositing a source contact to the lateral region or channel region.
  • Block 1506 represents depositing a drain contact to the drift region.
  • Block 1508 represents depositing one or more gates positioned to modulate conductivity of the channel region and/or modulate current flowing vertically from the source contact, through the drift region, and to the drain contact.
  • a dielectric layer (e.g., Al 2 0 3 )can be formed between the gates and the lateral channel and/or between the gates and the second Ill-nitride layer and along the interfaces.
  • the dielectric can provide negligible threshold shift under gate voltages between -10 V and + 10V.
  • a polar interface can be between the drift region and the one or more gates.
  • One of the gates can be formed in each of the trenches formed in Block 1502.
  • Block 1510 represents the end result, a semiconductor (e.g., vertical) device.
  • a semiconductor e.g., vertical
  • the device can comprise a lateral channel connected (e.g., bonded) to a drift region; a source contact to the lateral region; a drain contact to the drift region; one or more gates positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact, wherein the drift region comprises a current blocking structure; voltage is predominantly held in a vertical direction in an off-state; the current is channeled through an aperture in the current-blocking structure after it flows from under a gate region into the drift region in an on-state; and the one or more gates and/or the current blocking structure induce a two dimensional electron gas at one or more sidewalls of the gates and/or of the current blocking structure.
  • the current blocking structure can comprise different material regions that can provide a compensating charge, and the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in the off-state.
  • the current-blocking structure can be comprised of trenches filled with insulator and metal to provide the compensating charge, or trenches filled with alternating layers of semiconductor material to provide the compensating charge.
  • the gates In the on state, the gates can deplete the lateral channel adjacent the gates' sidewalls, so that the current flows predominantly from under the gate to the drift region.
  • the device can be a transistor further comprising a first Ill-nitride layer on a second Ill-nitride layer and comprising the lateral channel; a polar c-plane interface and nonpolar and/or semipolar interfaces between the first Ill-nitride layer and the second Ill-nitride layer; the source contact to the lateral channel; and the drift region, comprising one or more doped Gallium Nitride layers, wherein the polar interface is between the drift region and one or more gates.
  • the trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage can be fabricated by direct wafer-bonding of the drift region to the lateral channel, the modulation of the current flow of the transistor can occur in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state, and when the device is in the on-state, the current can be channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region.
  • the device can comprise a (e.g., semiconductor multi-junction) device, comprising a vertical device that is comprised of Parts A and B; wherein the Part A comprises at least one gate, at least one source, and a lateral channel (e.g,. that controls a current flow from the source to a drain); the Part B comprises a drift region that carries the current flow via a vertical or sloped two-dimensional electron gas (2- DEG or 2DEG) and along a sidewall; and the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by one or more current blocking layers (CBLs) and/or the current blocking structure.
  • a (e.g., semiconductor multi-junction) device comprising a vertical device that is comprised of Parts A and B; wherein the Part A comprises at least one gate, at least one source, and a lateral channel (e.g,. that controls a current flow from the source to a drain); the Part B comprises a drift region that carries the current flow via
  • the first part A can be comprised of a Region 71 that includes the source; a
  • the second part B can be comprised of a Region 84 that is comprised of the current blocking layer; a Region 85 that is comprised of a trenched structure that provides the vertical or sloped two-dimensional electron gas along the sidewall; a Region 86 that is comprised of the drift region; a Region 87 that allows the current flow towards the drain; a Region 88 that provides ohmic contact to the drain; and a Region 89 that includes the drain.
  • the drift region can be a voltage blocking region that can be (e.g., fully) depleted at voltages lower than a desired breakdown voltage.
  • the current blocking structure can have one or more dimensions and materials, and the current-carrying regions can have doping and one or more dimensions, such that an electric field held in the current blocking region is (e.g., much) less than its breakdown field in the off-state, such that the current-carrying region becomes fully depleted in the off-state, thus enabling a breakdown voltage of the device.
  • One or more of the source contacts can form metal regions between the gates and mitigate high field regions at the gate edges, ensuring the peak field is in the bulk of the device.
  • a polarization induced 2DEG can be formed in regions between the trenches resulting in the high conductivity 2DEG which spreads the current efficiently in the drift region to make the full chip area active.
  • the 2DEG along the vertical non-polar and/or semipolar interfaces is induced only under forward bias on the gates and the 2DEG on the polar c-plane is always present for all operating conditions.
  • the nonpolar interface can include an m-plane interface.
  • the transistor's electrically active device area can be equal to a geometric chip area on which the device is formed.
  • a device having an on resistance of 1 ⁇ ⁇ 2 can have three times smaller chip area for the same R on as a 3mQcm 2 device.
  • the transistor can be a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a vertical Junction Field Effect Transistor.
  • MOSFET Metal Oxide Semiconductor High Electron Mobility Transistor
  • the transistor can comprise a Gallium Nitride based transistor, comprising III- nitride layers, comprising a channel region and a drift region, formed on or above a Gallium Nitride substrate; a source contact to the channel region; a drain contact to the drift region; one or more gates positioned to modulate conductivity of the channel region and modulate current flowing vertically through the Ill-nitride layers from the source contact, through the drift region, and to the drain contact, wherein the current from the source contact to the drain contact spreads laterally in the drift region in an on-state of the device, utilizing substantially a full area of the drift region for conduction, the gates modulate the current spreading laterally and passing from the source contact to the drain contact, and voltage in an off-state of the device is substantially held in the doped drift region in a vertical direction between the source and drain contacts.
  • a Gallium Nitride based transistor comprising III- nitride layers, comprising a channel region and a drift region, formed on or above a Gall
  • the transistor can comprise Gallium Nitride based transistor, comprising a polar c-plane interface between one or more first III -nitride layers and one or more second Ill-nitride layer formed on a Gallium Nitride substrate; nonpolar and/or semipolar interfaces between one of the first Ill-nitride layers and one of the second III -nitride layers; one or more source contacts to one of the first Ill-nitride layers; a drift region, comprising one or more doped Gallium Nitride layers, wherein the polar interface is between the drift region and one or more gates, a drain contact to the drift region, the gates, positioned adjacent to the interfaces, modulating a conductive channel formed at the interfaces and a current passing through the conductive channel between the source and the drain contacts, wherein: the current from the source contact to the drain contact spreads laterally in the drift region in an on-state of the device, the gates modulate the current spreading laterally and passing between the source and the drain contact, and voltage
  • FIG. 16 illustrates a method of fabricating a transistor.
  • Block 1600 represents growing n-type GaN layers on a GaN substrate to serve as drift and channel layers.
  • Block 1602 represents growing n ++ GaN on the drift n-type GaN layer to serve as a contact layer.
  • Block 1604 represents etching one or more trenches in one or more of the n- type GaN layers to form multiple channels in one or more of the n-type GaN layers.
  • Block 1606 represents growing one or more Ill-nitride layers (e.g., blanket regrowing III-Nitride) on top of the channel layers/n-type GaN layers inside and outside the trenches.
  • Ill-nitride layers e.g., blanket regrowing III-Nitride
  • Block 1608 represents growing a first dielectric layer on the one or more III- nitride layers/re-grown Ill-nitride layer, inside and outside the trenches.
  • Block 1610 represents depositing a planar metal layer on the first dielectric layer.
  • Block 1612 represents etching the metal to leave a metal only in the trenches, wherein the metal forms gates.
  • Block 1614 represents depositing and covering the device with a second dielectric layer.
  • Block 1616 represents etching the second dielectric to remove a portion of the second dielectric to expose the top of the channel GaN layer outside the trenches.
  • Block 1618 represents depositing metal on regions exposed by removal of the second dielectric layer to form a source ohmic contact to the channel GaN layer.
  • the depositing can form metal regions between the gates that mitigate high field regions at gate edges and ensure the peak field is in the bulk of the device.
  • Block 1620 represents depositing metal on the drift region to form a drain ohmic contact.
  • Unintentional Si at the regrowth interface can be removed.
  • FIG. 17 illustrates a method of fabricating a Gallium Nitride based transistor.
  • Block 1700 represents growing or depositing one or more first Ill-nitride layers and one or more second Ill-nitride layers on a Gallium Nitride substrate, wherein polar c-plane interfaces between the layers are formed, and a drift region, comprising one or more doped Gallium Nitride layers, is formed;
  • Block 1702 represents forming nonpolar and/or semipolar interfaces between the first Ill-nitride layer and the second Ill-nitride layer.
  • Block 1704 represents depositing one or more source contacts to the III -nitride layers.
  • Block 1706 represents depositing a drain contact to the drift region.
  • Block 1708 represents depositing one or more gates that modulate a conductive channel formed at the interfaces and a current passing through the conductive channel between the source and the drain contacts, wherein the polar interface is between the drift region and the one or more gates, the current from the source contact to the drain contact spreads laterally in the drift region in an on-state of the device, the gates modulate the current spreading laterally and passing between the source and the drain contact, and voltage in an off-state of the device is substantially held in the doped drift region in a vertical direction between the source and drain contacts.
  • (AlInGaN)" "(In,Al)GaN", or “GaN” as used herein, as well as the terms “Ill-nitride,” “Group-Ill nitride”, ⁇ - ⁇ ,” or “nitride,” used generally, refer to any alloy composition of the (Ga,Al,In,B)N semiconductors having the formula Ga w Al x In y B z N where 0 ⁇ w ⁇ l, 0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ z ⁇ l, and w + x + y + z l .
  • These terms are intended to be broadly construed to include respective nitrides of the single species, Ga, Al, In and B, as well as binary, ternary and quaternary
  • compositions of such Group III metal species are compositions of such Group III metal species. Accordingly, it will be appreciated that the discussion of the invention hereinafter in reference to GaN and AlGaN materials is applicable to the formation of various other (Ga,Al,In,B)N material species.
  • (Ga,Al,In,B)N materials within the scope of the invention may include minor quantities of dopants and/or other impurity or inclusional materials.
  • non-III-nitride or “non-III-N” refers to any semiconductor that is excluded from the definition provided for the term “Ill-nitride” or "III-N.”
  • non-III-nitride refers to any semiconductor that is excluded from the definition provided for the term “Ill-nitride.”
  • (Ga,Al,In,B)N devices are grown along the polar c-plane of the crystal, although this results in an undesirable quantum-confined Stark effect (QCSE), due to the existence of strong piezoelectric and spontaneous polarizations.
  • QCSE quantum-confined Stark effect
  • One approach to decreasing polarization effects in (Ga,Al,In,B)N devices is to grow the devices on nonpolar or semipolar planes of the crystal.
  • nonpolar plane includes the ⁇ 1 1-20 ⁇ planes, known collectively as a-planes, and the ⁇ 10-10 ⁇ planes, known collectively as m-planes. Such planes contain equal numbers of Group-Ill (e.g., gallium) and nitrogen atoms per plane and are charge-neutral. Subsequent nonpolar layers are equivalent to one another, so the bulk crystal will not be polarized along the growth direction.
  • Group-Ill e.g., gallium
  • semipolar plane can be used to refer to any plane that cannot be classified as c-plane, a-plane, or m-plane.
  • a semipolar plane would be any plane that has at least two nonzero h, i, or k Miller indices and a nonzero 1 Miller index. Subsequent semipolar layers are equivalent to one another, so the crystal will have reduced polarization along the growth direction.
  • on-resistance refers to the linear relationship between current and drain to source voltage when the device is turned on via gate control and positive bias is applied to the drain contact.
  • blocking voltage refers to the positive voltage applied to the drain contact when the device is off.

Abstract

Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. The modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region.

Description

TRENCHED VERTICAL POWER FIELD-EFFECT TRANSISTORS WITH IMPROVED ON-RESISTANCE AND BREAKDOWN VOLTAGE
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit under 35 U.S.C. Section 119(e) of the following co-pending and commonly-assigned U.S. Provisional Patent Applications:
U.S. Provisional Patent Application Serial No. 61/993,759, filed on May 15, 2014, by Umesh Mishra, Stacia Keller, and Srabanti Chowdhury, entitled
"GALLIUM NITRIDE (GAN) BASED VERTICAL METAL OXIDE
SEMICONDUCTOR (MOS) TRANSISTORS AND JUNCTION FIELD EFFECT TRANSISTORS (JFETS)", attorney's docket No. 30794.550-US-P1 (2014-718-1);
U.S. Provisional Patent Application Serial No. 62/075,556, filed on November 5, 2014, by Srabanti Chowdhury, Chirag Gupta, Stacia Keller and Umesh K. Mishra, entitled "SUPERJUNCTION CURRENT APERTURE VERTICAL ELECTRON TRANSISTOR FOR ULTRA-LOW ON-RESISTANCE", attorney's docket No. 30794.579-US-P1 (2015-302-1); and
U.S. Provisional Patent Application Serial No. 62/075,560, filed on November 5, 2014, by Jeonghee Kim, Stacia Keller, Srabanti Chowdhury and Umesh K. Mishra, entitled "TRENCHED VERTICAL POWER FIELD-EFFECT TRANSISTORS WITH IMPROVED ON-RESISTANCE AND BREAKDOWN VOLTAGE", attorney's docket No. 30794.580-US-P1 (2015-303-1);
all of which applications are incorporated by reference herein.
This application is related to U.S. Patent Application Serial No. 13/527,885, filed on June 20, 2012, by Srabanti Chowdhury, Ramya Yeluri, Christophe Hurni, Umesh K. Mishra, and Ilan Ben-Yaacov, entitled "CURRENT APERTURE
VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P-TYPE GALLIUM NITRIDE AS CURRENT
BLOCKING LAYER," attorney's docket No. 30794.417-US-U1 (client reference 2011-831), which application claims the benefit under 35 U.S.C. Section 119(e) of the following co-pending and commonly-assigned U.S. Provisional Patent Applications:
U.S. Provisional Patent Application Serial No. 61/499,076, filed on June 20, 2011, by Srabanti Chowdhury, Ramya Yeluri, Christopher Hurni, Umesh K. Mishra, and Ilan Ben-Yaacov, entitled "CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P- TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER" attorneys' docket number 30794.417-US-P1 (2011-831-1); and
U.S. Provisional Patent Application Serial No. 61/583,015, filed on January 4, 2012, by Srabanti Chowdhury, Ramya Yeluri, Christopher Hurni, Umesh K. Mishra, and Ilan Ben-Yaacov, entitled "CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P- TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER" attorneys' docket number 30794.417-US-P2 (2011-831-2),
all of which applications are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention.
This invention relates to trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage.
2. Description of the Related Art.
(Note: This application references a number of different publications as indicated throughout the specification by one or more reference numbers in brackets, e.g., [Ref. x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled "References." Each of these publications is incorporated by reference herein.)
Conventional transistors have performance limitations, particularly in power switching applications where power losses occur due to the switching. High power switching applications place unique demands on device structure. Generally, there is a need for low on-resistance along with high breakdown voltage in such devices. One or more embodiments of the present invention satisfy this need.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, one or more embodiments of the present invention disclose novel trenched vertical power field-effect transistor structures with improved on- resistance and breakdown voltage. One or more embodiments of the invention are fabricated by direct wafer-bonding of the drift region to the lateral channel, although other methods of fabrication can be employed. The modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region.
One or more embodiments of the present invention further disclose a superjunction current aperture vertical electron transistor (S JCAVET) for ultra-low on-resistance. The SJCAVET is a vertical device that is comprised of two parts. One part is a lateral channel that controls current flow from source to drain, wherein this channel may provide conductance via two-dimensional electron gas (2-DEG), a doped channel, or both. The second part is a drift region or a voltage blocking region which carries the current via either a vertical or sloped 2-DEG and/or through an adjacent doped region. The current flow from the lateral channel to the vertical drift region is confined substantially to an aperture defined by one or more current blocking layers (CBLs). In one or more embodiments of the device, in the off- state, the device voltage blocking layers can be completely depleted at voltages lower than the desired breakdown voltage enabling ultra-low on resistance and high breakdown voltage. One or more embodiments of the invention further disclose the first true vertical GaN based transistors, where the gating is performed also on electrons traveling perpendicular to the surface in a vertical channel. An extremely low drift region spreading resistance is achieved by insertion of a two dimensional electron gas produced at an (Al,Ga,In)N/GaN heterojunction present on either side of the channel (referred to as the trench), significantly improving on the device performance by utilizing the full area of the drift region for conduction. The gating of the device can be either via a MOS structure to create a vertical MOSFET or a p-n junction to create a vertical JFET. Similar to the Current Aperture Vertical Electron Transistor
(CAVET), both MOS and JFET have in common that the voltage in the off-state of the device is substantially held in the vertical direction in the n- drift region. To reduce on resistance and chip cost, the electrically active device area can be equal to the geometric chip area.
One or more embodiments of the invention disclose a vertical transistor (e.g., III -nitride device), comprising a lateral channel connected to a drift region; a source contact to the lateral channel; a drain contact to the drift region; and one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact, wherein the drift region comprises a current blocking structure; voltage is predominantly held in a vertical direction in an off-state; the current is channeled through an aperture in the current-blocking structure after it flows from under the one or more gates, into the drift region in an on-state; and the one or more gates and/or the current blocking structure (i) induce a two dimensional electron gas at one or more sidewalls of the gates and/or of the current blocking structure, and/or (ii) the current blocking structure comprises different material regions that can provide a compensating charge, wherein the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in the off-state.
The current-blocking structure can be comprised of trenches filled with insulator and metal to provide the compensating charge. The current-blocking structure can be comprised of trenches filled with alternating layers of semiconductor material to provide the compensating charge.
The current blocking structure can have the one or more sidewalls adjacent to the current carrying region of the drift region, and be structured such that the one or more sidewalls reduce resistance to the current's flow in the current carrying drift region.
The device can comprise a part A bonded to a part B, wherein the Part A comprises the one or more gates, the source, and the lateral channel; the Part B comprises the drift region that carries the current flow via a vertical or sloped two- dimensional electron gas (2-DEG) and along the sidewall; and the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by the current blocking structure.
The drift region can be a voltage blocking region that can be fully depleted at voltages lower than a desired breakdown voltage.
The current blocking structure can have one or more dimensions and materials, and the current-carrying region can have one or more dimensions and doping, such that an electric field held in the current blocking region is less than its breakdown field in the off-state, and the current-carrying region becomes fully depleted in the off- state, thus enabling a breakdown voltage of the device.
The gates can deplete the lateral channel adjacent the gates' sidewalls, so that the current flows predominantly from under the gate to the drift region.
The device can be a transistor further comprising a first Ill-nitride layer on a second Ill-nitride layer and comprising the lateral channel; a polar c-plane interface and nonpolar and/or semipolar interfaces between the first Ill-nitride layer (e.g., GaN) and the second Ill-nitride layer (e.g., AlGaN); the source contact to the lateral channel; and the drift region, comprising one or more doped Gallium Nitride (GaN) layers, wherein the polar interface is between the drift region and one or more gates. The transistor can further comprise a plurality of trenches in one or more of the Ill-nitride layers, wherein the trenches shape the lateral channel; and one of the gates in each of the trenches.
The source contact can form metal regions between the gates and mitigate high field regions at the gate edges, ensuring the peak field is in the bulk of the device.
A polarization induced two dimensional electron gas (2DEG) can be formed in regions between the trenches, resulting in the 2DEG which spreads the current efficiently in the drift region to make the full chip area active.
In one or more embodiments, the channel comprising the 2DEG along the vertical non-polar (e.g., m-plane) and/or semipolar interfacesis induced only under forward bias on the gates and the 2DEG on the polar c-plane is always present for all operating conditions.
The transistor can further comprise a dielectric layer between the gates and the lateral channel, or the dielectric layer between the gates and the second Ill-nitride layer and along the interfaces; and wherein the dielectric provides negligible threshold shift under gate voltages between -10 V and + 10V.
The transistor's electrically active device area can be equal to a geometric chip area on which the device is formed and a device having an on resistance of 1 mQcm2 can have three times smaller chip area for the same Ron as a 3mQcm2 device.
The transistor can be a Gallium Nitride (GaN) based vertical transistor, including but not limited to, a vertical metal oxide semiconductor field effect transistors (MOSFET) or a vertical junction field effect transistor (JFET).
One or more embodiments of the invention further disclose a method of fabricating a vertical transistor, comprising depositing a semiconductor structure comprising a lateral channel connected to a drift region; depositing a source contact to the lateral channel; depositing a drain contact to the drift region; depositing one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact; and forming a trench region around a current carrying region of the drift region; and wherein: the trench region comprises a current blocking structure comprising different material layers that can provide a compensating charge, the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in an off-state, modulation of a current from a source to a drain occurs in the lateral channel, voltage is predominantly held in a vertical direction in the off-state, and the current is channeled through an aperture in the current-blocking structure after it flows from under the gates into the drift region in an on- state.
One or more embodiments of the invention further disclose a method of fabricating a transistor, comprising growing n-type GaN layers on a GaN substrate to serve as drift and channel layers; growing n++ GaN on the drift n-type GaN layer to serve as a contact layer; etching trenches in one or more of the GaN layers to form multiple channels in one or more of the GaN layers; growing one or more Ill-Nitride layers on top of the channel GaN layer inside and outside the trenches, growing a first dielectric layer on the Ill-nitride layers inside and outside the trenches; depositing a planar metal layer on the first dielectric layer, etching the metal to leave a metal only in the trenches, wherein the metal forms one or more gates; covering the device with a second dielectric layer; etching the second dielectric to remove a portion of the second dielectric to expose the tops of the channel GaN layer outside the trenches; depositing metal on regions exposed by removal of the second dielectric layer to form a source ohmic contact to the channel GaN layer, forming metal regions between the gates that mitigate high field regions at gate edges and ensure the peak field is in the bulk of the device; and depositing metal on the contact layer to form a drain ohmic contact.
One or more embodiments of the invention further disclose a method of fabricating a Gallium Nitride based transistor, comprising growing one or more first III -nitride layers and one or more second III -nitride layers on a Gallium Nitride substrate, wherein polar c-plane interfaces between the first and second Ill-nitride layers are formed, a drift region, comprising one or more doped Gallium Nitride layers, is formed, and a conductive channel is formed; forming nonpolar and/or semipolar interfaces in one or more of the Ill-nitride layers; depositing one or more source contacts to the conductive channel; depositing a drain contact to the drift region, depositing one or more gates that modulate the conductive channel formed at the interfaces and a current passing through the conductive channel between the source contacts and the drain contacts, wherein: a polar interface is between the drift region and the one or more gates, the current from the source contact to the drain contact spreads laterally in the drift region in an on-state of the device, the gates modulate the current spreading laterally and passing between the source and the drain contact, and voltage in an off-state of the device is substantially held in the doped drift region in a vertical direction between the source and drain contacts.
BRIEF DESCRIPTION OF THE DRAWINGS
Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
FIG. 1 is a schematic of the device structure according to one embodiment of the present invention.
FIG. 2 is a schematic of a first modified design of the device structure.
FIG. 3 is a schematic of a second modified design of the device structure. FIGS. 4(a)-4(f) illustrate a method of fabricating a semiconductor device, showing how to fabricate the device shown in FIG. 1.
FIG. 5 is a schematic of a proposed semiconductor device according to one embodiment of the present invention.
FIG. 6 shows the schematic of FIG. 1 divided into two regions labeled as Part A and B.
FIG. 7 shows Part A of FIG. 6 further sub-divided into regions labeled as Regions 71, 72 and 73.
FIG. 8 shows Part B of FIG. 6 further sub-divided into regions labeled as Regions 84, 85, 86, 87,88 and 89. FIG. 9(a)-(c) show Region 85 of FIG. 8 further defined as a trench region including modulation doping.
FIG. 10 is a cross-sectional schematic of a device illustrating limitations of a SiC MOSFET are effectively addressed by GaN based devices, and showing Source (S), Drain (D), and gate (G) contacts.
FIG. 11 is a cross-sectional schematic of a CAVET showing current modulation laterally under the gate with electrons flowing through the aperture vertically into the drain.
FIG. 12 is a cross-sectional schematic of a Vertical MOS transistor with a highly conductive lateral two dimensional electron gas (2DEG) to reduce drift region spreading resistance.
FIG. 13 shows cross-sectional schematics illustrating a Vertical Metal Oxide Semiconductor High Electron Mobility (MOSHEMT) process flow where the 2DEG along vertical m-plane is induced only under forward bias on the gate and the 2DEG on the c-plane is always present for all operating conditions.
FIG. 14 plots capacitance per centimeter square (microfarads per centimeter square, μΡ/cm2) as a function of gate bias (Volts, V), showing a first pair of upward and downward sweeps measured with an additional 10 minute stress in accumulation for a MOS capacitor (MOSCAP) with 25 nanometers (nm) AI2O3 grown in-situ by Metal Organic Chemical Vapor Deposition (MOCVD) at 1000 °C.
FIG. 15 is a flowchart illustrating a method of fabricating a device according to an embodiment of the invention.
FIG. 16 is a flowchart illustrating a method of fabricating a device according to another embodiment of the invention.
FIG. 17 is a flowchart illustrating a method of fabricating a device according to a further embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION
In the following description of the preferred embodiment, reference is made to a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.
Technical Description
I. Trenched Vertical Power Field-Effect Transistors
a. Principle of Operation Of One or More Embodiments
One or more embodiments of present invention relate to novel vertical power low-loss semiconductor devices attainable by direct wafer-bonding, wherein the modulation of the current flow of the transistor occurs in a lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current- blocking region after it flows under the gate region into a drift region.
Depending on its design, the current-carrying region in the drift region carries current either in a 2-dimensional or 3 -dimensional manner. Implementing 2- dimensional vertical conduction along channels with high mobility will provide additional benefits such as an increase in device speed as well as a reduction in on- resistance (RON), thereby providing a design with benefits superior to Si-based superjunction-based field-effect transistors.
The main current-blocking region is based on, but not limited to, a metal- insulator combination. This region is fabricated by filling up the trenches with desired types and thicknesses of insulator and metal, respectively. The insulator is deposited in a manner such that it is thicker at the bottom of the trench and thinner at the sidewalls, which simultaneously provides increased breakdown voltage (VBR) and reduced RON from the device.
Under a high drain bias, the metal/insulator interface in the current-blocking region holds a sheet charge of the opposing polarity to that of the current-carrying region; thus, it fully compensates for the ionized dopant concentration in the current- carrying region. Therefore, the dimension of the insulator, as well as the doping and dimensions of the current-carrying regions, should be determined such that the electric field held in the insulator is much less than its breakdown field in the off-state. When this condition is met, the current-carrying region becomes fully depleted, thus enabling a high VBR of the device.
On top of the drift region, bounded in part by trenched metal-insulator- semiconductor (MIS) based regions, a laterally conductive channel material is directly wafer-bonded (i.e. strong bonds are formed between the separately grown, high- quality wafers by applying heat and pressure) to fabricate the desired device. This lateral carrier flow can also be either 2-dimensional or 3 -dimensional depending on its design, but a 2-dimensional lateral conduction is preferred due to the advantages aforementioned in the description of 2-dimensional vertical conduction in the drift region and also in its ability to control the threshold voltage of the gate.
The source and gate electrodes are formed on the lateral wafer-bonded channel and the drain electrodes on the highly conductive bottom layer of the drift region, respectively. The source electrodes are also connected to the metal that fills up the MIS-based current-blocking regions.
The placement of a lateral channel on top of a template that is comprised of a current-carrying region surrounded by current-blocking regions resembles the invention of the Current Aperture Vertical Electron Transistor (CAVET) [Ref. 1]. However, it is noted that the lateral channel material, for the case of a CAVET, is regrown by heteroepitaxy on its template.
In this embodiment of the invention, which utilizes direct wafer-bonding instead of heteroepitaxy, the choice of the template material imposes no restriction on the choice of the lateral channel material. This gives an extra degree of freedom in terms of selecting the best material to be applied for each section of the structure to maximize the device performance. Successful implementations of wafer-bonding in fabricating electrically active heterojunctions have been reported previously [Ref. 2- 4]. Further, the extension of deep MIS-gated regions into the drift region results in significant loss reduction.
In the event that the materials in the channel and drift region are substantially similar, then the proposed structure can be constructed without bonding the lateral channel to the vertical drift region. In this case, the deep trench can be formed after the material growth of the current carrying regions of the full device is completed.
This embodiment is enabled by the use of wafer-bonding technique, which can be performed at much lower temperatures than typical heteroepitaxy, allowing for the use of metal fillings in the trenches for the current-blocking regions. Therefore, the proposed MIS-based current-blocking regions can be implemented based on wafer- bonding and provide an enhanced VBR - along with a superior on-state performance (e.g. low RON, high current) due to the 2-dimensional carrier flow - in comparison to other conventional transistors for high-power applications. The device, if electrons are chosen as the majority carrier, is termed a FABET (Fully Apertured Bonded Vertical Electron Transistor), representing that both the current and the voltage in the device are apertured.
This invention, with a potentially very high breakdown voltage, as well as a superior on-state performance, is an excellent candidate for high-power switching applications. It will become further attractive for such applications by an
implementation of the enhancement-mode (i.e. normally off) gating scheme.
Referring to FIG. 1, in the on- state, the carriers originating from the source electrodes 14, flow through the lateral channel as a 2-dimensional flow 11 with a very low resistance. They are modulated at the overlap regions between the gate electrodes 15 and the current-blocking regions 3. Because of the electric field set up by the drain electrode 16 at the bottom of the device, the carriers are swept vertically through the aperture 12 by turning the corners of the current-blocking regions 3. Then, they flow through the current-carrying region 1 as a substantially 2-dimensional flow 6, again with an extremely low resistance, and reach the drain electrode 16 at the bottom. The sheet charge at the interface of insulator-metal 7a-8 that fills up the trenches for forming the current-blocking regions 3 should appropriately compensate for the ionized dopants in the (relatively lowly doped or unintentionally doped) current- carrying region 1 without breaking down the insulator. Also, the thick insulator 7b at the bottom of the trench should be designed such that it supports the voltage in the off-state per device specifications. Therefore, a very low RON (due to both the lateral and vertical 2-dimensional conduction with high mobility), as well as a very high breakdown voltage (due to the MIS-based current-blocking regions along with the use of a high breakdown material in the drift region), can be achieved in this device. b. Device Structure According To One Or More Embodiments
The device structure can be divided into two portions: the drift region A and the lateral channel B, as shown in FIG. 1, the two of which are wafer-bonded to one another in this embodiment. If the materials in region A and B can be grown epitaxially, then that interface need not be bonded.
(i) Drift Region A
The template possesses similar features to that of typical superjunction power devices, with alternating current-carrying and current-blocking regions that extend toward the bottom conductive layer 2, which is connected to the drain electrode 16. Hence, a template grown on a conductive substrate is preferred, but it is also possible to place the drain electrode 16 laterally away from the bottom of the current-carrying region when using an insulating substrate or remove the substrate, whether it is conducting or insulating (examples include sapphire, ZnO, GaN, Ga203, SiC, Si, etc.). FIG. 1 depicts a device fabricated on a conductive substrate.
For applications related to high-power operations, the best choice for the drift region would be a semiconductor material with a high breakdown electric field. An example is an III-N material, although this structure can also be implemented in conventional elemental and compound semiconductors. The current-carrying region 1 can be doped either n- or p-type: (1) uniform doping; (2) abruptly changed doping; or (3) graded doping. The doping can be intentional or unintentional; it is not necessary to intentionally dope the region 1. It is noted that the electron concentration is designed to ensure depletion in all of the relevant regions and to obtain a lower peak electric field under the device off-state while maintaining a low on-resistance in the on-state. On the other hand, variations in doping concentration throughout the current-carrying region (i.e. as a function of both x and y as identified in FIG. 1) can be accommodated for enhanced conductivity and/or adjusting the electric field distribution in the device structure.
An important feature of this invention is the accommodation of a 2- dimensional carrier flow 6 in its vertical direction. One way to achieve this is by a modulation doping 5 in the barrier material 4, which is regrown after the formation of trenches in the drift regions and will become a part of the MIS-based current-blocking regions. Also, a use of semiconductor material that is polar in the horizontal direction (i.e. the x direction in FIG. 1) can be utilized such that the 2-dimensional carrier gas 6 is formed without substantial doping, but instead by polarization-induced charges. The existence of 2-dimensional carriers 6 is very beneficial to reducing RON, and it allows for even lower doping levels in the current-carrying region 1 without compromising RON, thus resulting in an even higher VBR of the device.
Another important feature of this invention is the design of the current- blocking region that is comprised of an insulator-metal 7a,b-8 combination, which is placed adjacent to the aforementioned barrier material 4 that induces 2-dimensional carriers 6. The sidewall insulator 7a blocks potential leakage between the metal 8 and the current-carrying region 1 and, under bias, supports the desired voltage per device specifications. Therefore, both the thickness of the insulator 7a as well as the doping and dimensions of the current-carrying region 1 should be designed such that the insulator can easily support the voltage required to completely deplete the region 1.
Further, as depicted in FIG. 1, the insulator 7b is much thicker toward the bottom of the trenches than the sidewall insulator 7a, and this plays a critical role in significantly enhancing the VBR of the device. Insulators 7a and 7b may be the same insulator or different insulators. It is important to determine the thickness d of insulator 7b such that the electric field held across the insulator in the off-state is not greater than the breakdown field of the insulator itself.
The trenched current-blocking layer extends down toward the highly conductive bottom layer 2, which represents either the conductive substrate or a highly doped layer grown on the substrate. The depth of the current-blocking region (i.e. depth of trench) can be shallower, identical, or deeper compared to the position of the interface between the regions 1 and 2. FIG. 1 depicts a case of the current- blocking region that extends deeper into the highly conductive layer 2. The dimensions di and d2 should be appropriately adjusted such that the imposed tradeoff between the offered benefits in low RON and high VBR is optimized.
Another type of current-blocking region 3, which defines the aperture 12, can be accommodated as desired. When it is incorporated as shown in FIG. 1, the current flowing in the lateral channel B would be modulated where the current-blocking region 3 and the gate metal 15 overlap. Its current-blocking (i.e. insulating) property can be obtained by (1) ion implantation, (2) employment of a material with an opposite doping type compared to the current-carrying region 1, or (3) insertion of a material that provides a high barrier height to the channel carrier type (e.g. insulator, semiconductor with a much higher bandgap, air-gap, etc.). Its location, as well as dimensions, can be optimized in a manner that it allows for a smooth transition of the lateral carrier flow 11 to the vertical flow 6 near the aperture 12.
(ii) Lateral Channel B
The channel 9 preferably is comprised of a 2-dimensional carrier flow 11 , which ensures higher mobility of the carriers. The 2-dimensional carrier in the channel can be realized either by accommodating a modulation doping in the barrier material 10 or by polarization engineering if a polar semiconductor such as III-N is implemented. The interface 13 identifies the borderline between the drift region A and the lateral channel B, and may be an epitaxial or wafer-bonded interface . The best choice for the lateral channel material would be a semiconductor material that offers high mobility for the majority carrier to enhance the device speed and on-state performance, including RON, without presenting a barrier to carrier transfer across the wafer-bonded interface 13.
The source electrodes 14 are designed such that, in one embodiment, they contact the carriers in the lateral channel as well as the metal 8 that fills up the MIS- based current-blocking regions. Moreover, optional source and/or gate-connected field plates can be placed over the gate metal 15 after depositing the passivating insulator layer to further enhance the breakdown voltage.
The geometry of the gate electrode 15 can be varied. For instance, it can be defined by a uniform metallization (as shown in FIG. 1) or by a split-design metallization, where the flow of current from either source is modulated by physically separated gates (which may be electrically connected).
The transistor shown in FIG. 1 depicts a depletion-mode (i.e. normally on) device. However, its gate design can be altered such that it operates as an
enhancement-mode (i.e. normally off) device by employing a fluorine-based treatment underneath the gate electrodes, recessed gate region, or doping of the gate barrier material with an opposite dopant type from the channel (e.g. p-type gate barrier for n-channel), etc.
Thus, FIG. 1 illustrates a semiconductor device, comprising a vertical device that is comprised of a lateral channel B bonded to a drift region A; wherein modulation of a current from a source 14 to a drain 16 occurs in the lateral channel B; voltage is predominantly held in a vertical direction in an off-state; and the current is channeled through an aperture 12 in a current-blocking region after it flows under a gate region 15 into the drift region A in an on-state. FIG. l further illustrates the source and gate can be formed on the lateral channel B and the drain 16 can be formed on the drift region A. FIG. 1 further illustrates the current-blocking region can be comprised of trenches filled with insulator 7a-b and metal 8, wherein the insulator 7b is thicker at a bottom of the trench and the insulator 7a is thinner at sidewalls of the trenches. c. Possible Modifications and Variations
FIG. 2 depicts a modified design of the MIS-based vertical power transistor.
The drift region Al is prepared by firstly etching off parts of the highly conductive layer 2 to form the voltage-holding regions, which are subsequently filled with dielectric 7b. After a planarization (if needed), the drift region A2 is either wafer- bonded to or regrown on the drift region Al . The interface 17 identifies the borderline between the two regions. As a result, the dielectric 7b (with a predetermined optimal thickness d) is placed fully within the highly conductive layer 2. The remaining device regions A2 and B are identical to the regions A and B of the device structure shown in FIG. 1.
This invention also discloses the addition of spacers (e.g. rounded spacers with a radius of ~d in the case of FIG. 2) to further enhance the breakdown voltage of the device. This is to address the device breakdown path in the off-state between the metal filling 8 and the highly conductive region 2. The shape and dimensions of these spacers is based on device specifications, but are intended to minimize peaking of deleterious electric fields in the structure, which can reduce breakdown.
To suppress the potential increase in resistance near the interface between the dielectric 7b and the current-carrying region 1 at the interface 17, a highly doped but thin (thus it has negligible impact to the device VBR) interlayer can be accommodated at the bottom of the drift region A2. In doing so, the design space for trade-off between RON and VBR potentially present in the device depicted in FIG. 1 (which is determined by di and d2) is expanded.
FIG. 3 shows another permutation of the proposed vertical power transistors. It features Schottky barrier based sidewalls 8, which are connected to the source regions of the devices (not shown in the figure). In the off-state, the depleted ionized (intentional or unintentional) dopants in the current-carrying region 1 would image on the sidewall metal 8. All of the regions Al, A2, and B can be either wafer-bonded to or regrown on each other. The thickness d3 of the dielectric material 7c (which can be the same as or different from the buried dielectric 7b) is another design knob available in the structure, and it can be varied from zero to any desired thickness to further enhance the overall device performance. d. Method of Fabrication According To One Or More Embodiments To fabricate the device shown in FIG. 1, according to one embodiment of the present invention, a template A comprised of layers 1 , 2 with desired doping concentrations and thicknesses is grown, preferably, on a conductive substrate. The current-blocking regions 3 are formed by one of the aforementioned insulating methods, i.e., (1) ion implantation, (2) employment of a material with an opposite doping type compared to the current-carrying region 1, or (3) insertion of a material that provides a high barrier height to the channel carrier type (e.g. insulator, semiconductor with a much higher bandgap, air-gap, etc.) and thus define the aperture 12 of the device. The trenches are firstly formed by etching (shown in FIG. 4(a)), and subsequently a desired type of insulator 7b is deposited such that the trenches become completely filled (shown in FIG. 4(b)). The insulator is dry-etched until its remaining thickness at the bottom is close to the desired thickness d (shown in FIG. 4(c)). Next, a layer of barrier material 4 (either modulation doped 5 or polarization-engineered or both) that induces 2-dimensional carriers 6 of a desired conductivity type in the drift region is deposited (shown in FIG. 4(d)), preferably using a selective regrowth method such as metalorganic chemical vapor deposition (MOCVD). The insulator 7a is then deposited until it reaches the desired thickness for the trench sidewalls (shown in FIG. 4(e)); thus, this second deposition forms the sidewall layers for the MIS junctions in the current-blocking regions. Next, a desired type of metal 8 is deposited, which fills up the remaining regions of the trenches, thereby completing the current- blocking regions of the template (shown in FIG. 4(f)). It is noted that the process steps other than those represented in FIG. 2 can be also used to produce the identical current-blocking region profile. If necessary, a planarization of the template takes place to prepare a flat surface for wafer-bonding it to the lateral channel B. Post a low-temperature wafer-bonding process that does not alter the MIS junctions (especially metal) in the template, appropriate processes for source, gate, and drain regions are performed to complete the fabrication.
It is also noted that other embodiments could use different methods of fabrication that those described herein with regards to FIG. 4.
There are some process developments that will play a critical role in successfully fabricating the proposed device with a III-N based drift region. These include III-N deep trench etching technique for current-blocking regions and sidewall AlGaN regrowth to achieve 2-dimensional vertical flow in the current-carrying regions. II. Superjunction Current Aperture Vertical Electron Transistor for Ultra-
Low On-Resistance
a. Principle of Operation Of One or More Embodiments
One or more embodiments of the present invention disclose a semiconductor multi-junction device in Ill-nitride and non-III-nitride material systems, which aims at providing ultra-low on-resistance along with high breakdown voltage. Specifically, the proposed semiconductor device is a vertical device, namely, an SJCAVET that is comprised of two parts, namely, Parts A and B.
Part A of the device comprises a channel which controls current in the lateral direction by modulating a two-dimensional or three-dimensional channel. It contains at least one source and one gate.
Part B of the device is a drift region, which is a voltage blocking region that contains a substantial part of the blocked voltage in the off-state in the vertical dimension. Current blocking layers form an aperture to restrict current flow from source to drain to the aperture from where it spreads to other conductive parts of the drift region. The current blocking layers can be formed by or comprise either p-type regions, wide bandgap materials, insulators or any dielectric including air-gaps.
An important feature of the device in one embodiment is a vertical or sloped
2-DEG on the sidewall to reduce the resistance to current flow, thereby achieving ultra-low on-resistance. This vertical 2-DEG is achieved by modulation doping an AlGaN layer which is adjacent to the current carrying drift region.
If the crystal were such that the crystal were polar in the x-direction, the 2- DEG could be formed because of polarization differences. Positive fixed charges of any form can be used to induce a 2-DEG in the drift region.
The device also has trenched p-n junctions which fully deplete laterally (x- direction) on applying a drain voltage substantially smaller than the breakdown voltage of the device. This allows the voltage to be held from source to drain in a region which has substantially a constant electric field in the y-direction rather than the decreasing electric field typical for doped drift regions. This is a phenomenon similar to Si superjunction devices.
Together these features provide for ultra-low on-resistance (RON) and high breakdown voltage. This device structure is highly advantageous for high power switching applications. b. Device Structure According To One Or More Embodiments
FIG. 5 is a schematic of a proposed semiconductor device according to one embodiment of the present invention, illustrating a superjunction current aperture vertical electron transistor (SJCAVET) for ultra-low on-resistance, comprising a lateral channel (comprising 2-DEG inducing layers 500 and layer 502 comprising n(x,y) GaN) that controls current flow from source S to drain D, wherein this channel may provide conductance via two-dimensional electron gas (2-DEG), a doped channel, or both. The device further comprises drift region or a voltage blocking region which carries the current via either a vertical or sloped 2-DEG and/or along with current through an adjacent doped region 504 comprising n(x,y) GaN. The current flow from the lateral channel to the vertical drift region is confined substantially to an aperture 506 defined by one or more current blocking layers (CBLs).
The proposed semiconductor device shown in FIG. 5 could be broadly divided into two regions labeled as Part A and B as shown in FIG. 6.
FIG. 6 illustrates a semiconductor multi-junction device, comprising the vertical device that is comprised of Parts A and B, wherein the Part A comprises at least one gate G, at least one source S, and the lateral channel that controls a current flow from the source S to a drain D; the Part B comprises a drift region that carries the current flow via a vertical or sloped two-dimensional electron gas (2-DEG) and along a sidewall 600; and the current flow from the lateral channel to the drift region is confined substantially to an aperture 506 defined by one or more current blocking layers (CBLs).
The part A is comprised of a channel that controls current in the lateral direction, and the least one gate G can be single, multiple or split gated, for example. A 2-DEG is shown to be the sole current carrying region in Part A, although the channel could also have three-dimensional conductivity.
Part A can be further sub-divided into regions labeled as Regions 71, 72 and
73 as shown in FIG. 3.
Source contact (Region 71) to the 2-DEG is ohmic and acts as a source for electrons in the channel region. The ohmic source contact can be achieved by multiple methods, such as regrowth, anneal, etc.
Region 72 provides the 2-DEG in the channel. This could be achieved in multiple ways, for example, by having a wide band gap material with a positive polarization interface followed by a lower band gap material. In absence of polarization, modulation doping can also be utilized to obtain the 2-DEG. The main purpose of the layered structure in Region 72, which may comprise a single layer of c-plane (1000) AlGaN or multiple layers of AlGaN/AlN/GaN, is to induce 2-DEG in the channel.
Region 73, which is the region under the gate, modulates the charge in the 2- DEG channel, and thus controls the current flow. The device may comprise a metal- oxide-semiconductor (MOS) structure with oxide, dielectric, or other wide band gap material buried under the gate (with an oxide shown in the figures). The thickness of the oxide, dielectric, or other wide band gap material, is variable. The doping concentration in Region 3 could be variable to meet design criteria.
The device shown is a depletion mode device (negative threshold
voltage/normally on), but it could also be enhancement mode device as well (positive threshold voltage/normally off). This can be achieved using ion implantation, recess etch, p-type gate, and other methods.
All dimensions in Part A are variable and can be altered to meet design criteria.
Part B is shown in FIG. 8, and includes the drift region, as well as the drain.
Part B can be further sub-divided into regions labeled as Regions 84, 85, 86, 87, 88 and 89.
Region 84 is comprised of a current blocking layer (CBL). The function of the CBL is to act as barrier to carrier flow through the CBL, thereby forcing and/or directing the source current from Part A through the gated region into the aperture in Part B, wherein this current is modulated by the lateral gate. The CBL could be actualized by ion implantation, growth, insulating material, p-type GaN, and other methods. Aperture width could be varied to meet design criteria. The dimensions of the current blocking layer are variable and can be altered to meet design criteria.
The current blocking layer is followed by the trenched structure (Region 85).
The trench could be angled and the Θ (theta) angle could vary from 5 degrees to 175 degrees from the horizontal plane. The δ (delta) spacing shown in the FIG. 8 could be positive, negative or zero, wherein the δ represents the overlap of the trenched structure with the current blocking layer. This trenched structure provides the opportunity to get a 2-DEG along the sidewalls 600, which is essential in reducing on-resistance. The 2-DEG on the sidewalls could be achieved by modulation doping (shown as the dotted line along the trench structure).
If the nature of the interface is polar, then the polarization charge at the interface between the wide band gap material followed by lower band gap material (Region 86) can provide the 2-DEG. Graded polar regions can also be employed, so called 3-DEGs.
Region 5b) is comprised of opposite conductivity semiconductor to Region 86. When a blocking voltage is applied to the semiconductor device, the lateral p-n junction formed between Regions 85 and 86 in Part B gets fully depleted, forming a space charge region, wherein the vertical electric field is substantially constant, unlike the decreasing electric field in one-dimensional n-type semiconductors. This leads to the highest breakdown voltage with the lowest on-resistance. Region 5b) can be variably p-type doped in both the x and y directions to allow for the compensating charges 508 and to control the electric field.
Since variable p-type doping is difficult to control, a different method to achieve effective p-type doping may also be used. Specifically, the concept of super- lattice or multi-layer structures with modulation or uniform doping can be utilized to obtain compensating charges in the trenched structure shown in FIG. 9(a)-(c).
Alternating layers of modulation doped higher band gap material followed by lower band gap material (GawAlxInyBzN / GawAlxInyBzN) would form the super-lattice or multi-layer structure and thus provide the necessary compensating charges.
Alternatively, the super-lattice or multi-layer region can also be uniformly doped with acceptors and produce substantially the same results. FIG. 9(b) illustrates a variation of FIG. 9(a) comprising GaN layers 900 and AlGaN layers 902 that are uniformly doped with acceptors (Mg), wherein an AlGaN layer 902b is modulation doped with Si 904. FIG. 9(c) illustrates a variation of FIG. 9(a) comprising GaN layers 906 and AlGaN layers 908, wherein AlGaN layers 908 are modulation doped with Mg 910 and AlGaN layer 908b is modulation doped with Si 912.
To re-emphasize, wider band gap material (barrier), or narrow band gap material (well), or both wider band gap material (barrier) and narrow band gap material (well), can be doped (either modulation doped or uniformly doped with acceptors) to meet design criteria. Different carrier concentration can be achieved by varying the dimensions, spacing, doping and number of the layers. Polarization fields if available can also be utilized in super-lattices to provide the necessary charges for charge compensation.
The current blocking layer and p-type semiconductor region in the trenched structure can be electrically connected such that, in operation, there is no bias between them as shown in FIG. 5.
Region 86 shown in FIG. 8 is generally n-type with variable doping in both the x and y directions.
Region 87 is also of the same conductivity type as Region 86. Region 87 allows the spread of the current from 2-DEG towards the drain contact. Region 87 can also hold the blocking voltage, depending on the doping and thickness of the region. This may or may not involve the same semiconductor as in Region 86. The thickness of Region 87 is variable from zero to any positive value.
Region 88 is a highly conductive layer providing good ohmic contact to the drain (Region 89). c. Possible Modifications and Variations
Various alterations can be made to this device design.
The combination of Parts A and B into the semiconductor device shown in FIG. 5 creates the aperture to allow the flow of current and can be achieved in multiple ways:
(a) Part A can be regrown on top of Part B. This may or may not involve the same semiconductor in Regions 73, 84 and 86. (b) Part A can be wafer bonded to the top of Part B. Again, this may or may not involve the same semiconductor in Regions 73, 84 and 86. Bonding can be achieved in different ways.
(c) This structure can be realized in different shapes and forms such as cylindrical, hexagonal and other geometries.
(d) Note also that, in the drawings, the source contact only contacts the CBL. In practice, the source contact can also contact the p-type region below, including, but not limited to, the super-lattice or multi-channel region.
A semiconductor device according to one or more embodiments of the invention can provide ultra- low on resistance with high breakdown voltage. A semiconductor device according to one or more embodiments of the invention can achieve low loss, reducing a major cost of a power converter system, the heat sink and enabling system-design flexibility. III. GaN based vertical metal oxide semiconductor (MPS) transistors and junction field effect transistors (TFETS)
a. Introduction
Three novel and practical approaches are proposed that have the common theme of markedly reducing chip size compared to commercially available lateral GaN on Si based High Electron Mobility Transistors (HEMTs), coupled with simplicity of fabrication processes to reduce cost. These result in vertical devices where the voltage in the off-state is substantially held in the vertical dimension, completely different from the devices qualified and in the market today. The limitations facing Silicon Carbide (SiC) MOSFETs today are shown in FIG. 10. FIG. 10 illustrates Source S, Drain D, Gate G, inversion layer 1000, dielectric 1002, n" SiC, n+ SiC, p-type region p, and n+type region p. Contacts to SiC have a contact resistance of ~ 1 mflcm2 whereas a GaN device can have low contact resistance made to n GaN. The inversion layer has a contact resistance of ~ 1 mflcm2 whereas a GaN device can comprise a 2DEG, high mobility channel. The drift resistance in SiC is ~ 1 mQcm2 whereas a GaN device can have a unique device structure to reduce drift resistance.
Here, one or more embodiments of the invention propose a true vertical transistor, where the gating is also performed on electrons traveling perpendicular to the surface in a vertical channel (different from a CAVET, illustrated in FIG. 11).
FIG. 11 is a cross-sectional schematic of a CAVET showing current modulation laterally under the gate G with electrons flowing 1100 through the aperture 1102 (formed by Magnesium (Mg) implant 1104) vertically into the drain 1106. Also shown are n-type GaN (n GaN) layer 1108, n-type GaN (n+ GaN) layer 1110, and source S contact.
In one embodiment, illustrated in FIG. 12, an extremely low drift region spreading resistance is achieved by the insertion of a two dimensional electron gas (2DEG) produced at the AlGaN/GaN heterojunction present on either side of the channel (the trench region 1200). This can significantly improve on the device performance by utilizing the full area of the drift region for conduction. The device comprises Source S, Drain D, n'GaN layer 1202, n+GaN layer 1204, 1206, dielectric 1208, AI2O3, AlGaN layer 1210, vertical current flow 1212, 2DEG 1214 on either side of the channel, 2DEG 1216, and depleted region 1218.
The gating of this device can be either via a MOS structure to create a vertical MOSFET as is shown in FIG. 12, or a p-n junction to create a vertical JFET, where the p-region may be created by ion implantation and activation. In the case of the MOSFET, embodiments of the invention have the ability of depositing the dielectric by high vacuum Atomic Layer Deposition (ALD), by MOCVD, by Chemical Vapor Deposition (CVD), or in-situ by MOCVD, for example. An alternate approach addresses epitaxially grown p-type regions.
To reduce the on resistance R<,n(in the ιηΩΰΐη2 range) while simultaneously reducing chip cost, it is essential that the electrically active device area be equal to the geometric chip area. For example a 1 ιηΩΰΐη2 device has three times smaller chip area for the same R<,n as a 3 ιηΩΰΐη2 device. b. MOSHEMT schematic (FIG. 12) and process flow (FIG. 13)
FIG. 12 shows an embodiment of a normally-off Vertical MOSFET wherein the built-in voltage of the side gates fully deplete (depleted region 1218) the vertical channel in between. Depletion-mode Vertical MOSFETs can be also fabricated. An example of the fabrication process is described below and shown in FIG. 13. The first 6 um of GaN (doped n-type at 5xl015cm~3) are epitaxially grown on GaN substrates to serve as the drift and channel layer, followed by 0.5 μιη of epitaxial n++GaN or n+ GaN to serve as a contact layer or layers, as shown in FIG. 13a. Next, 1.5 μιη deep multiple channels are formed using photolithography and dry etch techniques (Mask M, FIG.13b). A blanket regrowth of AlGaN is then conducted. A polarization induced 2DEG is formed in the regions between the channels (trench regions) resulting in a high conductivity two dimensional electron gas (2DEG) which spreads the current efficiently in the drift region to make the full chip area active (FIG. 13c).
Channels with either no or small 2DEG densities are formed along the sidewalls because of their non-polar or semi-polar nature enabling normally-off operation. The regrowth is either followed by an in-situ growth of Α1203 dielectric, or by an ex-situ technique such as ALD (FIG.13c). In the latter case, appropriate care to remove unintentional Si at the regrowth interface will be implemented [7].
FIG. 14 shows initial work done at the University of California, Santa Barbara
(UCSB) on MOCVD dielectrics (that shows minimum threshold shift under voltage for dielectrics deposited in-situ after planar Ga-polar GaN growth, showing the feasibility of this approach.
After dielectric deposition (by Metalorganic Chemical Vapor Deposition (MOCVD) or Plasma Enhanced Atomic Layer Deposition (PEALD) as examples), 1 micrometer (um) of Ti/Al (high workfunction metal 1300) is sputtered over the entire sample (FIG. 13d). The spacing of the channels is designed to be 2 μιη. This enables the metal to be planar over the full sample. A blanket etch is carried out to remove 1 micron of Aluminum (Al), leaving behind a gate length of 1 micron on the sidewalls (FIG.13e). Next, the device is covered with dielectric 1302 (FIG.13f). A blanket-etch to remove a portion of the dielectric to expose the tops of the channels is then performed. The Ti and the AI2O3 dielectric is then removed (FIG.13g) and aluminum metal 1304 is deposited over the whole sample to form the source ohmic contact and active pads (FIG.13h). The metal regions 1306 between the active gates (FIG. 13d and 13e) mitigate high field regions at gate edges and ensure the peak field is in the bulk of the device (FIG. 13h). c. Possible Modifications
In the Vertical MOSHEMT process, the AlGaN layer can be replaced by InAIN or any (B,Al,Ga,In)N layer, and the AI2O3 can be replaced by any other dielectric, for example S13N4 or Si02 , or higher k dielectrics. Incorporating no heterojunction material is also an embodiment which leads to a Vertical MOSFET and any of the above dielectrics maybe used as an example.
The process flow can be modified in any suitable other way to fabricate the device.
For all devices, instead of MOCVD, any other suitable growth technique can be used, for example molecular beam epitaxy (MBE) or chemical beam epitaxy (CBE), or hydride vapor phase epitaxy (HVPE), or a combination of different growth techniques. Also all materials can be (Al,Ga,In)N of constant or varying
compositions. d. Advantages and Improvements
The disclosed devices designs allow the fabrication of devices that exceed the performance of current GaN based transistors for power switching applications, as well as SiC MOSFETs, by allowing high voltage operation in combination with an extremely low contact resistance, high switching speed, and low drift resistance. IV. Process Steps
a. First Example
FIG. 15 illustrates a method of fabricating a vertical transistor.
Block 1500 represents forming (e.g., depositing and/or bonding) a
semiconductor structure comprising a lateral channel connected to a drift region. The step can comprise bonding a part A to a part B, wherein the part A comprises the lateral channel and the Part B comprises the drift region.
The step can comprise growing Ill-nitride layers, comprising a channel region and a drift region, on or above a Gallium Nitride substrate. The step can comprise growing/depositing one or more first Ill-nitride layers and one or more second III- nitride layers on or above a Gallium Nitride substrate to form the lateral channel, the drift region, and a contact layer, and for example, wherein polar c-plane interfaces between the layers are formed. The drift region can comprise one or more doped III- nitride layers (e.g., Gallium Nitride layers), on a Gallium nitride substrate.
The step can comprise depositing a first Ill-nitride layer on a second Ill-nitride layer and comprising the lateral channel. The channel region or conductive channel can comprise a two dimensional electron gas (2DEG) confined in the Ill-nitride layers, or confined in the first Ill-nitride layer by the interfaces with the second III- nitride layer. The first Ill-nitride layer can be (e.g., doped) GaN and the second III- nitride layer can be AlGaN. The first Ill-nitride layer can be grown on the drift region.
The lateral channel can provide conductance via a two-dimensional electron gas and/or a doped channel.
The drift region and channel region can be n-type. The channel region can comprise a junction between a p-type region and an n-type region in the III -nitride layers, or the interfaces in the lateral channel can comprise junctions between a p-type region and an n-type region, wherein the p-type region is in the first Ill-nitride layer and the n-type region is in the second Ill-nitride layer, or the n-type region is in the first Ill-nitride layer and the p-type region is in the second III -nitride layer of the lateral channel.
Block 1502 represents forming one or more trench regions in the
semiconductor structure.
The step can comprise forming a trench region around a current carrying region of the drift region, wherein the trench region comprises a current blocking structure comprising different material layers that can provide a compensating charge, and the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in the off-state.
The current-blocking structure can be comprised of trenches filled with insulator and metal, e.g., wherein the insulator is thicker at a bottom of the trench and thinner at sidewalls of the trenches. The current-blocking structure can be comprised of trenches filled with alternating layers of (e.g., different) semiconductor material (e.g., alternating layers of different Ill-nitride material, e.g., alternating AlGaN and GaN layers).
The current blocking structure can comprise one or more sidewalls adjacent to a current carrying region of the drift region, and be structured such that the one or more sidewalls reduce resistance to the current's flow in the current carrying drift region.
The trench regions can be such that current flow can be carried via a vertical or sloped two-dimensional electron gas (2-DEG) and along the sidewall; and the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by the current blocking structure.
One or more trenches can be formed in the Ill-nitride layers, wherein the trenches shape the lateral channel. For example, one or more trench regions in III- nitride layers of the semiconductor structure can be formed such that a polar c-plane interface and nonpolar and/or semipolar interfaces (e.g., m-plane interface) are between the first Ill-nitride layer and the second III -nitride layer forming the lateral channel and/or 2DEG. Block 1504 represents depositing a source contact to the lateral region or channel region.
Block 1506 represents depositing a drain contact to the drift region.
Block 1508 represents depositing one or more gates positioned to modulate conductivity of the channel region and/or modulate current flowing vertically from the source contact, through the drift region, and to the drain contact.
A dielectric layer (e.g., Al203)can be formed between the gates and the lateral channel and/or between the gates and the second Ill-nitride layer and along the interfaces. The dielectric can provide negligible threshold shift under gate voltages between -10 V and + 10V.
A polar interface can be between the drift region and the one or more gates. One of the gates can be formed in each of the trenches formed in Block 1502.
Block 1510 represents the end result, a semiconductor (e.g., vertical) device.
The device can comprise a lateral channel connected (e.g., bonded) to a drift region; a source contact to the lateral region; a drain contact to the drift region; one or more gates positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact, wherein the drift region comprises a current blocking structure; voltage is predominantly held in a vertical direction in an off-state; the current is channeled through an aperture in the current-blocking structure after it flows from under a gate region into the drift region in an on-state; and the one or more gates and/or the current blocking structure induce a two dimensional electron gas at one or more sidewalls of the gates and/or of the current blocking structure. The current blocking structure can comprise different material regions that can provide a compensating charge, and the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in the off-state.
The current-blocking structure can be comprised of trenches filled with insulator and metal to provide the compensating charge, or trenches filled with alternating layers of semiconductor material to provide the compensating charge. In the on state, the gates can deplete the lateral channel adjacent the gates' sidewalls, so that the current flows predominantly from under the gate to the drift region.
The device can be a transistor further comprising a first Ill-nitride layer on a second Ill-nitride layer and comprising the lateral channel; a polar c-plane interface and nonpolar and/or semipolar interfaces between the first Ill-nitride layer and the second Ill-nitride layer; the source contact to the lateral channel; and the drift region, comprising one or more doped Gallium Nitride layers, wherein the polar interface is between the drift region and one or more gates.
In one or more embodiments, the trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage can be fabricated by direct wafer-bonding of the drift region to the lateral channel, the modulation of the current flow of the transistor can occur in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state, and when the device is in the on-state, the current can be channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region.
The device can comprise a (e.g., semiconductor multi-junction) device, comprising a vertical device that is comprised of Parts A and B; wherein the Part A comprises at least one gate, at least one source, and a lateral channel (e.g,. that controls a current flow from the source to a drain); the Part B comprises a drift region that carries the current flow via a vertical or sloped two-dimensional electron gas (2- DEG or 2DEG) and along a sidewall; and the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by one or more current blocking layers (CBLs) and/or the current blocking structure.
The first part A can be comprised of a Region 71 that includes the source; a
Region 72 that includes the lateral channel; and a Region 73 that comprises a region under the gate. The second part B can be comprised of a Region 84 that is comprised of the current blocking layer; a Region 85 that is comprised of a trenched structure that provides the vertical or sloped two-dimensional electron gas along the sidewall; a Region 86 that is comprised of the drift region; a Region 87 that allows the current flow towards the drain; a Region 88 that provides ohmic contact to the drain; and a Region 89 that includes the drain.
The drift region can be a voltage blocking region that can be (e.g., fully) depleted at voltages lower than a desired breakdown voltage.
The current blocking structure can have one or more dimensions and materials, and the current-carrying regions can have doping and one or more dimensions, such that an electric field held in the current blocking region is (e.g., much) less than its breakdown field in the off-state, such that the current-carrying region becomes fully depleted in the off-state, thus enabling a breakdown voltage of the device.
One or more of the source contacts can form metal regions between the gates and mitigate high field regions at the gate edges, ensuring the peak field is in the bulk of the device.
A polarization induced 2DEG can be formed in regions between the trenches resulting in the high conductivity 2DEG which spreads the current efficiently in the drift region to make the full chip area active.
In one or more embodiments, the 2DEG along the vertical non-polar and/or semipolar interfaces is induced only under forward bias on the gates and the 2DEG on the polar c-plane is always present for all operating conditions. The nonpolar interface can include an m-plane interface.
The transistor's electrically active device area can be equal to a geometric chip area on which the device is formed. A device having an on resistance of 1 ι Ωΰΐ 2 can have three times smaller chip area for the same Ron as a 3mQcm2 device.
The transistor can be a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a vertical Junction Field Effect Transistor. The MOSFET can be a Metal Oxide Semiconductor High Electron Mobility Transistor
(MOSHEMT).
The transistor can comprise a Gallium Nitride based transistor, comprising III- nitride layers, comprising a channel region and a drift region, formed on or above a Gallium Nitride substrate; a source contact to the channel region; a drain contact to the drift region; one or more gates positioned to modulate conductivity of the channel region and modulate current flowing vertically through the Ill-nitride layers from the source contact, through the drift region, and to the drain contact, wherein the current from the source contact to the drain contact spreads laterally in the drift region in an on-state of the device, utilizing substantially a full area of the drift region for conduction, the gates modulate the current spreading laterally and passing from the source contact to the drain contact, and voltage in an off-state of the device is substantially held in the doped drift region in a vertical direction between the source and drain contacts.
The transistor can comprise Gallium Nitride based transistor, comprising a polar c-plane interface between one or more first III -nitride layers and one or more second Ill-nitride layer formed on a Gallium Nitride substrate; nonpolar and/or semipolar interfaces between one of the first Ill-nitride layers and one of the second III -nitride layers; one or more source contacts to one of the first Ill-nitride layers; a drift region, comprising one or more doped Gallium Nitride layers, wherein the polar interface is between the drift region and one or more gates, a drain contact to the drift region, the gates, positioned adjacent to the interfaces, modulating a conductive channel formed at the interfaces and a current passing through the conductive channel between the source and the drain contacts, wherein: the current from the source contact to the drain contact spreads laterally in the drift region in an on-state of the device, the gates modulate the current spreading laterally and passing between the source and the drain contact, and voltage in an off-state of the device is substantially held in the doped drift region in a vertical direction between the source and drain contacts. b. Additional Examples
FIG. 16 illustrates a method of fabricating a transistor. Block 1600 represents growing n-type GaN layers on a GaN substrate to serve as drift and channel layers.
Block 1602 represents growing n++ GaN on the drift n-type GaN layer to serve as a contact layer.
Block 1604 represents etching one or more trenches in one or more of the n- type GaN layers to form multiple channels in one or more of the n-type GaN layers.
Block 1606 represents growing one or more Ill-nitride layers (e.g., blanket regrowing III-Nitride) on top of the channel layers/n-type GaN layers inside and outside the trenches.
Block 1608 represents growing a first dielectric layer on the one or more III- nitride layers/re-grown Ill-nitride layer, inside and outside the trenches.
Block 1610 represents depositing a planar metal layer on the first dielectric layer.
Block 1612 represents etching the metal to leave a metal only in the trenches, wherein the metal forms gates.
Block 1614 represents depositing and covering the device with a second dielectric layer.
Block 1616 represents etching the second dielectric to remove a portion of the second dielectric to expose the top of the channel GaN layer outside the trenches.
Block 1618 represents depositing metal on regions exposed by removal of the second dielectric layer to form a source ohmic contact to the channel GaN layer. The depositing can form metal regions between the gates that mitigate high field regions at gate edges and ensure the peak field is in the bulk of the device.
Block 1620 represents depositing metal on the drift region to form a drain ohmic contact.
Unintentional Si at the regrowth interface can be removed.
FIG. 17 illustrates a method of fabricating a Gallium Nitride based transistor.
Block 1700 represents growing or depositing one or more first Ill-nitride layers and one or more second Ill-nitride layers on a Gallium Nitride substrate, wherein polar c-plane interfaces between the layers are formed, and a drift region, comprising one or more doped Gallium Nitride layers, is formed;
Block 1702 represents forming nonpolar and/or semipolar interfaces between the first Ill-nitride layer and the second Ill-nitride layer.
Block 1704 represents depositing one or more source contacts to the III -nitride layers.
Block 1706 represents depositing a drain contact to the drift region.
Block 1708 represents depositing one or more gates that modulate a conductive channel formed at the interfaces and a current passing through the conductive channel between the source and the drain contacts, wherein the polar interface is between the drift region and the one or more gates, the current from the source contact to the drain contact spreads laterally in the drift region in an on-state of the device, the gates modulate the current spreading laterally and passing between the source and the drain contact, and voltage in an off-state of the device is substantially held in the doped drift region in a vertical direction between the source and drain contacts.
Nomenclature
The terms "(AlInGaN)" "(In,Al)GaN", or "GaN" as used herein, as well as the terms "Ill-nitride," "Group-Ill nitride", ΊΙΙ-Ν," or "nitride," used generally, refer to any alloy composition of the (Ga,Al,In,B)N semiconductors having the formula GawAlxInyBzN where 0≤w < l, 0 < x < l, 0 < y < l, 0 < z < l, and w + x + y + z = l . These terms are intended to be broadly construed to include respective nitrides of the single species, Ga, Al, In and B, as well as binary, ternary and quaternary
compositions of such Group III metal species. Accordingly, it will be appreciated that the discussion of the invention hereinafter in reference to GaN and AlGaN materials is applicable to the formation of various other (Ga,Al,In,B)N material species.
Furthermore, (Ga,Al,In,B)N materials within the scope of the invention may include minor quantities of dopants and/or other impurity or inclusional materials. The term "non-III-nitride" or "non-III-N" refers to any semiconductor that is excluded from the definition provided for the term "Ill-nitride" or "III-N."
The term "non-III-nitride" refers to any semiconductor that is excluded from the definition provided for the term "Ill-nitride."
Many (Ga,Al,In,B)N devices are grown along the polar c-plane of the crystal, although this results in an undesirable quantum-confined Stark effect (QCSE), due to the existence of strong piezoelectric and spontaneous polarizations. One approach to decreasing polarization effects in (Ga,Al,In,B)N devices is to grow the devices on nonpolar or semipolar planes of the crystal.
The term "nonpolar plane" includes the {1 1-20} planes, known collectively as a-planes, and the {10-10} planes, known collectively as m-planes. Such planes contain equal numbers of Group-Ill (e.g., gallium) and nitrogen atoms per plane and are charge-neutral. Subsequent nonpolar layers are equivalent to one another, so the bulk crystal will not be polarized along the growth direction.
The term "semipolar plane" can be used to refer to any plane that cannot be classified as c-plane, a-plane, or m-plane. In crystallographic terms, a semipolar plane would be any plane that has at least two nonzero h, i, or k Miller indices and a nonzero 1 Miller index. Subsequent semipolar layers are equivalent to one another, so the crystal will have reduced polarization along the growth direction.
The term "on-resistance" refers to the linear relationship between current and drain to source voltage when the device is turned on via gate control and positive bias is applied to the drain contact.
The term "blocking voltage" refers to the positive voltage applied to the drain contact when the device is off.
References
The following references are incorporated by reference herein:
[1] U.S. Publication No. 2012/0319127, filed June 20, 2012, published December 20, 2012, by S. Chowdhury, R. Yeluri, C. Hurni, U. K. Mishra, and I. Ben- Yaacov, and entitled "Current Aperture Vertical Electron Transistors with Ammonia Molecular Beam Epitaxy Grown P-type Gallium Nitride as a Current Blocking Layer."
[2] J. Kim, N. G. Toledo, S. Lai, J. Lu, T. E. Buehl, and U. K. Mishra. "Wafer- Bonded p-n Heterojunction of GaAs and Chemomechanically Polished N-Polar GaN," IEEE Electron Device Lett., 34, no. 1, pp. 42-44, (2013).
[3] S. Lai, J. Lu, M. Guidry, B. Thibeault, S. P. DenBaars, and U. K. Mishra. "Controlling electronic properties of wafer-bonded interfaces among dissimilar materials: A path to developing novel wafer-bonded devices," IEEE Device Research Conference (DRC), pp. 121-122, (2013).
[4] J. Kim, S. Lai, M. A. Laurent, and U. K. Mishra. "Vertical electron transistors with Ino.53Gao.47As channel and N-polar Ino.1Gao.9N/GaN drain achieved by direct wafer-bonding," IEEE Device Research Conference (DRC), pp. 221-222, (2014).
[5] U.S. Patent No. 5,438,215, issued August 1, 1995, to Tihanyi, and entitled "Power MOSFET."
[6] U.S. Patent No. 6,677,643, issued January 13, 2004, to Iwamoto et al, and entitled "Super-junction semiconductor device."
[7] Srabanti Chowdhuri, PhD thesis, University of California, Santa Barbara, December 2010.
Conclusion
This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS:
1. A vertical transistor, comprising:
a lateral channel connected to a drift region;
a source contact to the lateral channel;
a drain contact to the drift region; and
one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact, wherein:
the drift region comprises a current blocking structure; voltage is predominantly held in a vertical direction in an off-state; the current is channeled through an aperture in the current-blocking structure after it flows from under the one or more gates, into the drift region in an on-state; and
the one or more gates and/or the current blocking structure:
(i) induce a two dimensional electron gas at one or more sidewalls of the gates and/or of the current blocking structure, and/or
(ii) the current blocking structure comprises different material regions that can provide a compensating charge, wherein the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in the off-state.
2. The device of claim 1, wherein the current-blocking structure is comprised of trenches filled with insulator and metal to provide the compensating charge.
3. The device of claim 1, wherein the current-blocking structure is comprised of trenches filled with alternating layers of semiconductor material to provide the compensating charge.
4. The device of claim 1, wherein the device is a III -nitride device.
5. The device of claim 1, wherein the current blocking structure:
has the one or more sidewalls adjacent to the current carrying region of the drift region, and
is structured such that the one or more sidewalls reduce resistance to the current's flow in the current carrying drift region.
6. The device of claim 1, comprising:
a part A bonded to a part B, wherein:
the Part A comprises the one or more gates, the source, and the lateral channel;
the Part B comprises the drift region that carries the current flow via a vertical or sloped two-dimensional electron gas (2-DEG) and along the sidewall; and
the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by the current blocking structure.
7. The device of claim 1, wherein the drift region is a voltage blocking region that can be fully depleted at voltages lower than a desired breakdown voltage.
8. The device of claim 1, wherein:
the current blocking structure has one or more dimensions and materials, and the current-carrying region has one or more dimensions and doping, such that:
an electric field held in the current blocking region is less than its breakdown field in the off-state, and
the current-carrying region becomes fully depleted in the off-state, thus enabling a breakdown voltage of the device.
9. The device of claim 1, wherein, in the on state, the gates deplete the lateral channel adjacent the gates' sidewalls, so that the current flows predominantly from under the gate to the drift region.
10. The device of claim 1, wherein the device is a transistor further comprising:
a first Ill-nitride layer on a second Ill-nitride layer and comprising the lateral channel;
a polar c-plane interface and nonpolar and/or semipolar interfaces between the first Ill-nitride layer and the second Ill-nitride layer;
the source contact to the lateral channel; and
the drift region, comprising one or more doped Gallium Nitride layers, wherein the polar interface is between the drift region and one or more gates.
11. The transistor of claim 10, further comprising:
a plurality of trenches in one or more of the Ill-nitride layers, wherein the trenches shape the lateral channel; and
one of the gates in each of the trenches.
12. The transistor of claim 11, wherein the source contact forms metal regions between the gates and mitigates high field regions at the gate edges, ensuring the peak field is in the bulk of the device.
13. The transistor of claim 11 , wherein a polarization induced two dimensional electron gas (2DEG) is formed in regions between the trenches, resulting in the 2DEG which spreads the current efficiently in the drift region to make the full chip area active.
14. The transistor of claim 13, wherein the channel comprising the 2DEG along the vertical non-polar and/or semipolar interfaces is induced only under forward bias on the gates and the 2DEG on the polar c-plane is always present for all operating conditions.
15. The transistor of claim 14, wherein the non-polar interface includes an m-plane interface.
16. The transistor of claim 15, wherein the first Ill-nitride layer is GaN and the second Ill-nitride layer is AlGaN.
17. The transistor of claim 10, further comprising:
a dielectric layer between the gates and the lateral channel, or
the dielectric layer between the gates and the second Ill-nitride layer and along the interfaces; and
wherein the dielectric provides negligible threshold shift under gate voltages between -10 V and + 10V.
18. The transistor of claim 10, wherein the transistor's electrically active device area is equal to a geometric chip area on which the device is formed and a device having an on resistance of 1 mflcm2 has three times smaller chip area for the same R<,n as a 3ιηΩΰΐη2 device.
19. The transistor of claim 10, wherein the transistor is a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a vertical Junction Field
Effect Transistor.
20. A method of fabricating a vertical transistor, comprising: depositing a semiconductor structure comprising a lateral channel connected to a drift region;
depositing a source contact to the lateral channel;
depositing a drain contact to the drift region;
depositing one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact; and
forming a trench region around a current carrying region of the drift region; and wherein:
the trench region comprises a current blocking structure comprising different material layers that can provide a compensating charge,
the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in an off-state, modulation of a current from a source to a drain occurs in the lateral channel,
voltage is predominantly held in a vertical direction in the off-state, and
the current is channeled through an aperture in the current-blocking structure after it flows from under the gates into the drift region in an on-state.
21. A method of fabricating a transistor, comprising:
growing n-type GaN layers on a GaN substrate to serve as drift and channel layers;
growing n++ GaN on the drift n-type GaN layer to serve as a contact layer; etching trenches in one or more of the GaN layers to form multiple channels in one or more of the GaN layers;
growing one or more III-Nitride layers on top of the channel GaN layer inside and outside the trenches, growing a first dielectric layer on the Ill-nitride layers inside and outside the trenches;
depositing a planar metal layer on the first dielectric layer,
etching the metal to leave a metal only in the trenches, wherein the metal forms one or more gates;
covering the device with a second dielectric layer;
etching the second dielectric to remove a portion of the second dielectric to expose the tops of the channel GaN layer outside the trenches;
depositing metal on regions exposed by removal of the second dielectric layer to form a source ohmic contact to the channel GaN layer, forming metal regions between the gates that mitigate high field regions at gate edges and ensure the peak field is in the bulk of the device; and
depositing metal on the contact layer to form a drain ohmic contact.
22. A method of fabricating a Gallium Nitride based transistor, comprising:
growing one or more first Ill-nitride layers and one or more second Ill-nitride layers on a Gallium Nitride substrate, wherein:
polar c-plane interfaces between the first and second Ill-nitride layers are formed,
a drift region, comprising one or more doped Gallium Nitride layers, is formed, and
a conductive channel is formed;
forming nonpolar and/or semipolar interfaces in one or more of the Ill-nitride layers;
depositing one or more source contacts to the conductive channel;
depositing a drain contact to the drift region, depositing one or more gates that modulate the conductive channel formed at the interfaces and a current passing through the conductive channel between the source contacts and the drain contacts, wherein:
a polar interface is between the drift region and the one or more gates, the current from the source contact to the drain contact spreads laterally in the drift region in an on-state of the device,
the gates modulate the current spreading laterally and passing between the source and the drain contact, and
voltage in an off-state of the device is substantially held in the doped drift region in a vertical direction between the source and drain contacts.
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