KR20140016105A - Nitride semiconductor device and method for manufacturing the same - Google Patents

Abstract

A nitride semiconductor device and a manufacturing method thereof are disclosed. Embodiments of the present invention are able to solve the problem of the characteristics of current features generated by an existing recess process and improve the characteristics of a semiconductor device according to the same by partially etching an area under a gate in a recess gate process. The embodiments of the present invention are able to compensate a current reduction phenomenon which is generated in the recess process by minimizing a channel area in which an electron concentration decreases by a discontinuous partial etching of the area under the gate. The embodiments of the present invention are able to minimize the current reduction by preventing a two-dimensional electron gas channel from being removed from the lower part of a gate electrode between a source electrode and a drain electrode by forming a recess area discontinuously and are also able to change a nitride semiconductor device which is a normally-on form which is the disadvantage of an HFET device, as an example, into a normally-off form through a deplection area which has a large surface area which is generated in the area which is etched partially and discontinuously.

Description

[0001] NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor device in the form of normally off and a manufacturing method thereof.

The nitride semiconductor is a broadband bandgap compound semiconductor and is capable of emitting light up to a visible range and broadly to the ultraviolet range. Blue-violet laser diodes and blue light-emitting diodes are used in a wide range of fields ranging from optical pickup devices, traffic lights, public displays, liquid crystal backlights, and lighting.

Nitride semiconductors are attracting attention due to their high critical electric field, low on resistance, high temperature and high frequency operation characteristics compared to silicon and are being studied as materials for next generation semiconductor devices.

BACKGROUND ART [0002] Metal-oxide semiconductor field-effect-transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) are generally used for high output power devices. In addition, devices such as a high electron mobility transistor (HEMT), a heterojunction field-effect transistor (HFET), and a MOSFET are studied as a gallium nitride (GaN) .

HEMTs are used for high frequency communication devices and the like by using high mobility of electrons. On the other hand, in the case of MOSFETs, the characteristics of the device are lower than those of GaN due to the absence of a good gate oxide film and the difficulty of ion implantation and heat diffusion processes to selectively form P-type or N-type regions. The effect is not noticeable.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET). Referring to FIG. 1, a general HFET includes a substrate 1, a first GaN layer 2 formed on the substrate, an AlGaN layer 3 formed on the first GaN layer, 2 GaN layer 4, a gate electrode 5, a source electrode 6 and a drain electrode 7 formed on the second GaN layer.

A typical HFET switches a two-dimensional electron gas (2DEG) current flowing from a drain electrode to a source electrode through a schottky gate electrode.

In the case of a general HFET device, the quality of the Schottky characteristic using the gate operation can have a large influence on the switching characteristics of the device. Therefore, the role of minimizing leakage on the gate side and expanding the depletion region is of the utmost importance. Also, there is a need for a technique of moving the threshold voltage (supply voltage) in the positive direction so that the current flow of the 2DEG channel in the heterojunction structure is normally turned off.

Although many attempts have been made to use the HFET device as a high output power device because of excellent voltage and current characteristics, the HFET device has a disadvantage of having a normally on shape unlike other devices such as MOSFET and IGBT. In the case of a normally on element, it is difficult to make it complicated in forming a circuit. For this reason, methods such as plasma treatment, p-GaN growth, and recess gate have been studied as a method for increasing the threshold voltage.

The recess gate method, which is the most common method of increasing the threshold voltage, is a method of etching the AlGaN layer in the region under the gate to reduce the concentration of 2DEG channel flowing in the region. In general, a structure change due to plasma energy occurs through the recess process, and a leakage current increases in the gate region. Therefore, a metal insulator semiconductor HFET (MISHFET) device is applied to apply an insulating film after the recess process.

During the recess process, lowering the concentration of 2DEG may result in poor current characteristics. As a result, the HFET device may have a normally off shape, but a large current characteristic, which is an existing advantage, may be reduced.

In order to overcome these disadvantages, a method of increasing the thickness of the AlGaN layer, a method of fabricating an AlN / GaN HFET device by replacing the AlGaN layer with an aluminum nitride layer, or a p-GaN layer deposition method is studied. It is becoming. However, these generally have a problem that high quality epitaxial layer growth is difficult. In thick AlGaN growth and AlN layer growth, a material structure may be broken due to stress due to a difference in lattice constant of the epi layer. In the p-GaN layer deposition, p-type doping is not properly performed due to the characteristics of GaN, and thus deposition may be difficult.

It is an object of the present invention to provide a nitride semiconductor device and a method of manufacturing the same, which partially etch a region below the gate to partially etch it away.

According to an embodiment, a nitride semiconductor device includes a buffer layer formed on a substrate, a nitride layer semiconductor, a recessed region, a barrier layer formed on the buffer layer, and a gate electrode formed on the recessed region; And a source electrode and a drain electrode respectively contacted on the barrier layer.

The recess region is formed between the source electrode and the drain electrode, and is formed to have an area equal to or less than the area occupied by the gate electrode.

In addition, the recess region may be formed in a plurality of etching regions discontinuously.

In addition, the plurality of etching regions may be arranged in a predetermined pattern in the recess region.

The distance between the plurality of etching regions may be 1 to 100 nanometers.

A nitride semiconductor device according to another embodiment includes a buffer layer formed on a substrate, a nitride layer semiconductor, a barrier region formed on the buffer layer, a barrier layer formed on the buffer layer, and a gate electrode formed on the recess region; And a cap layer formed between the barrier layer and the electrodes, the source electrode and the drain electrode being in contact with each other on the barrier layer, and made of aluminum gallium nitride.

The buffer layer has a two-dimensional electron gas channel thereon, and the recess region is formed on the two-dimensional electron gas channel or to a depth of a portion of the buffer layer.

In the nitride semiconductor device according to another embodiment, the gate electrode includes a gate insulating layer formed on the recess region.

According to an embodiment, a method of manufacturing a nitride semiconductor device may include forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a source electrode and a drain electrode on the barrier layer, and And forming a recessed region in the barrier layer between the electrode and the drain electrode, and forming a gate electrode over the recessed region. In the forming of the recess region, the recess region is formed to have an area less than or equal to an area occupied by the gate electrode.

Embodiments of the present invention may solve the problem of current characteristic reduction caused by the conventional recess process by partially etching the region under the gate during the recess gate process, thereby improving the characteristics of the semiconductor device. .

Embodiments of the present invention can compensate for a current reduction phenomenon occurring in the recess process by minimizing a channel region in which electron concentration is reduced through discontinuous partial etching of an area under the gate.

Embodiments of the present invention solve the problem that all of the two-dimensional electron gas channels are removed by discontinuously forming the recess region under the gate electrode, and two-dimensional under the gate electrode between the source electrode and the drain electrode. The current reduction can be minimized by not removing all electron gas channels.

Embodiments of the present invention can change the normally-on form, which is a disadvantage of a nitride semiconductor device, for example, an HFET device, to a normally-off form through a depletion region having a large surface area occurring in a discontinuously partially etched region. .

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET);
2 and 3 are views showing the structure of the nitride semiconductor device according to the embodiments of the present invention;
4 through 6 illustrate various types of recessed areas in embodiments of the present invention;
7 is a flowchart schematically illustrating a method of manufacturing a nitride semiconductor device according to one embodiment;
8A to 8D are exemplary diagrams for describing an operation of manufacturing a nitride semiconductor according to an embodiment; And
9 illustrates a structure of a nitride semiconductor device according to another exemplary embodiment.

2, a nitride semiconductor device according to an embodiment includes a buffer layer, a barrier layer, and a gate electrode, a source electrode, and a drain electrode.

The buffer layer 10 is formed on the substrate 1 and is made of a nitride semiconductor. The barrier layer 20 is formed over the buffer layer 10 and has a recess region 30. The gate electrode 40 is formed over the recess region 30. In addition, the source electrode 50 and the drain electrode 60 are in contact with each other on the barrier layer 20.

The substrate 1 may be an insulating substrate such as a sapphire substrate or the like. The substrate 1 may be formed of one of a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and a silicon (Si) substrate. The substrate 1 may be removed after fabrication of the nitride semiconductor device. In this case, the structure of the final device may be a structure in which the substrate 1 is not provided.

The buffer layer 10 is a undoped GaN layer (undoped GaN) or a high resistance GaN layer doped with one of Carbon, Iron (Fe), Magnesium (Mg), and combinations thereof. The thickness of the buffer layer 10 is 0.5 to 10 micrometers (μm), preferably 0.6 to 3 μm. The impurity concentration doped in the buffer layer 10 has a 1e17 / cm ³ to about 1e20 / cm ^3. Preferably, so as to have a concentration of 1e18 / cm ³ to about 1e19 / cm ^3. A two dimensional electron gas channel (2DEG) is formed above the buffer layer 10, that is, below the portion where the buffer layer 10 and the barrier layer 20 come into contact with each other.

The buffer layer 10 may be formed by various methods. A metal organic chemical vapor deposition (MOCVD), a molecular beam epitaxy (MBE), a hydride vapor phase epitaxy (HVPE), a plasma enhanced chemical vapor deposition (PECVD), sputtering, and AtOhmic Layer Deposition (ALD). However, considering the crystallinity of the buffer layer 10, the buffer layer 10 is generally fabricated by metal-organic chemical vapor deposition. TMGa as a raw material of Ga, and NH ₃ as a raw material of N are synthesized at a high temperature in a reactor to perform epitaxial growth.

Although not illustrated, the buffer layer 10 may include a low resistance layer between the substrate 1 and the substrate 1. The low-resistance layer is generally made of an n-type gallium nitride (n-GaN). The thickness of the low resistance layer is 0.01 to 10 micrometers ([mu] m). Preferably, the low resistance layer is grown to a thickness of 0.1 to 2 μm. The low resistance layer may also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, etc., as well as the buffer layer.

Although not shown, an AlGaN layer made of Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1) may be further formed between the buffer layer 10 and the substrate 1.

The barrier layer 20 is made of aluminum gallium nitride (AlGaN), that is, Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1). The barrier layer 20 has a thickness of 0 to 100 nanometers (nm). Preferably it is grown to 0-10 nm. The Al composition of AlGaN is about 1 to 100%, preferably about 10 to 50%. The barrier layer 20, like the buffer layer 10, may also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, or the like.

For example, as shown in FIGS. 8A and 8B, after the GaN buffer layer 10 in which the 2DEG is formed on the substrate 1 is grown to 0.5 to 10 μm, preferably 0.6 to 3 μm, the AlGaN barrier layer is grown. A nitride semiconductor device according to an embodiment is manufactured by growing (20) to a thickness of 0 to 100 nm, preferably 0 to 10 nm.

Referring to FIG. 3, a nitride semiconductor device according to another embodiment includes a buffer layer 20 formed on a substrate 1, a nitride layer semiconductor, and a recess region 30, and the buffer layer 10. A barrier layer 20 formed thereon, a gate electrode 40 formed on the recess region 30, a source electrode 50 and a drain electrode 60 contacting the barrier layer 20, respectively; It is formed between the barrier layer 20 and the electrode, and comprises a cap layer 70 made of aluminum gallium nitride.

Like the barrier layer 20, the cap layer 70 is made of aluminum gallium nitride (AlGaN), that is, Al _x Ga _{1 - x} N (0 ≦ _x ≦ 1). Al composition may use 0 to 100%. The thickness is grown to 0 to 10 nanometers, preferably 0 to 5 nm.

In this case, the recess region 30 may be formed by etching the cap layer 70, the barrier layer 20, and a portion of the buffer layer 10.

For example, as shown in FIGS. 8A and 8B, after the GaN buffer layer 10 in which the 2DEG is formed on the substrate 1 is grown to 0.5 to 10 μm, preferably 0.6 to 3 μm, the AlGaN barrier layer is grown. (20) is grown to a thickness of 0 to 100 nm, preferably 0 to 10 nm, and then the AlGaN cap layer 70 is grown to 0 to 10 nm, preferably 0 to 5 nm to nitride according to another embodiment A semiconductor device is manufactured.

After the epitaxial growth, the isolation process is performed to define the inter-device region, and the source electrode and the drain electrode are deposited.

That is, after epitaxial growth, as shown in FIG. 8C, the source electrode 50 is formed on the barrier layer 20 or the cap layer 70. The source electrode 50 is formed in the part where the gate electrode 40 is not formed, and consists of metal.

The source electrode 50 is formed of ohmic contacts. For example, the source electrode 50 uses a Ti / Al based structure, and may be used after or without heat treatment. As an example, the source electrode 50 is formed by a lift-off process by depositing Ti / Al / Ti / Au using an electron beam evaporator with a thickness of 30/100/20/200 nm, respectively. .

After epitaxial growth, as shown in FIG. 8C, the drain electrode 60 is formed on the barrier layer 20 or the cap layer 70. The drain electrode 60 is formed in a portion where the gate electrode 40 is not formed, and is made of metal.

The drain electrode 60 is formed of ohmic contact. For example, the drain electrode 60 uses a Ti / Al based structure, and may be used after or without heat treatment.

After contacting the source electrode 50 and the drain electrode 60, as shown in FIG. 8D, the recess region 30 is defined and a recess process is performed.

As shown in FIG. 4, in the nitride semiconductor device according to example embodiments of the inventive concept, the recess region 30 is positioned between the source electrode 50 and the drain electrode 60. The recess region 30 is preferably formed to have an area equal to or smaller than the area occupied by the gate electrode 40.

Referring to FIG. 5, in the recess region 30, a plurality of etching regions 31 may be discontinuously formed. 6, in the recess region 30, a plurality of etching regions 31 may be disposed in a predetermined pattern. In FIG. 5 or FIG. 6, only circular or elliptical shapes are disclosed, but may have other shapes. In addition, in FIG. 6, although the form arranged in two lines, it may be arranged in a different pattern.

The recess region 30 discontinuously and partially etches to remove all two-dimensional electron gas channels formed at the top of the buffer layer 10, that is, below the portion where the buffer layer 10 and the barrier layer 20 are in contact with each other. No, but some exist. The remaining two-dimensional electron gas channels, which are not all removed, can minimize current reduction.

The distance between the plurality of etching regions 31 may be 1 to 100 nanometers (nm). First, the recess region 30 is defined discontinuously and partially. The discontinuous and partial etching regions 31 may extend the depletion region not only on the z axis but also on the x and y axes to create a normally off characteristic. In order to make the normally off characteristic, it is preferable to set the distance between the etching regions to 1 to 100 nm.

The recess process etches the barrier layer using chlorine-based etch gases, for example Cl ₂ and BCl ₃ -based gases. In addition, the recess process can etch to the upper or lower layer, that is, the buffer layer, of the 2DEG channel using an etching gas. The gate electrode 40 is deposited on the recess region 30, and the width of the region is the same as the recess region, or 0 to 5 micrometers (the region of the source electrode 50 or the drain electrode 60). in μm). In addition, the gate electrode 40 may be made of an electrode having high work function such as Ni, Ir, Pd, or Pt.

Referring to FIG. 9, the gate electrode 40 may include a gate insulating layer 41 formed on the recess region 30. The gate insulating layer 41 prevents leakage current of the gate electrode. The gate insulating layer 41 is made of at least one of silicon oxide (SiO ₂ ), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), and silicon nitride (SiN). Here, the gate electrode is formed on the gate insulating film layer 41. The nitride semiconductor device may have a MIS (Metal-Insulator-Semiconductor) structure.

The gate insulating film layer 41 can be formed in various ways (methods). For example, based on at least one of metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, sputtering, and atomic layer deposition. For example, the source electrode 50 is formed on the substrate grown to the barrier layer 20 or the cap layer 70 through a manufacturing process, and the gate insulating layer 41 is deposited using a thermal evaporator or PECVD, and then deposited. A gate electrode is formed on the gate insulating film layer, that is, the oxide.

Referring to FIG. 7, a method of manufacturing a nitride semiconductor device according to an embodiment may include forming a buffer layer on a substrate (S10), forming a barrier layer on the buffer layer (S20), and a source on the barrier layer. Forming an electrode and a drain electrode (S30), forming a recess region in the barrier layer between the source electrode and the drain electrode (S40), and forming a gate electrode on the recess region ( S50) is configured to include.

In the forming of the recess region (S40), the recess region is formed to have an area less than or equal to the area occupied by the gate electrode.

The buffer layer is a undoped GaN layer (undoped GaN) or a high resistance GaN layer doped with one of carbon, iron (Fe), magnesium (Mg), and combinations thereof. The thickness of the buffer layer is 0.5 to 10 m, preferably 0.6 to 3 m. The impurity concentration doped in the buffer layer is 1e17 / cm ³ to 1e20 / cm ³ . Preferably, so as to have a concentration of 1e18 / cm ³ to about 1e19 / cm ^3. A two dimensional electron gas channel (2DEG) is formed above the buffer layer, that is, below the portion where the buffer layer and the barrier layer come into contact with each other.

The buffer layer may be formed by various methods. For example, based on at least one of metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, sputtering, and atomic layer deposition. However, considering the crystallinity of the buffer layer, the buffer layer is generally fabricated by metal-organic chemical vapor deposition. TMGa, which is a raw material of Ga, and NH ₃ , which is a raw material of N, are synthesized at a high temperature in the reactor for epitaxial growth (S10).

The barrier layer is made of aluminum gallium nitride (AlGaN), that is, Al _x Ga _{1 - x} N (0 _{? X} ? 1). The thickness of the barrier layer is grown to be 0 to 100 nm, preferably 0 to 10 nm. Al composition of AlGaN is grown to 1 to 100%, preferably 10 to 50% (S20). The barrier layer, like the buffer layer, may also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, or the like.

Referring back to FIG. 7, the method of manufacturing a nitride semiconductor device according to another embodiment may further include forming a cap layer on the barrier layer using aluminum gallium nitride (S21).

The cap layer, like the barrier layer, is made of aluminum gallium nitride (AlGaN), that is, Al _x Ga _1-x N (0 ≦ _x ≦ 1). Al composition may use 0 to 100%. The thickness is grown to 0 to 10 nm, preferably 0 to 5 nm (S21). The cap layer, like the buffer layer and the barrier layer, may be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, or the like.

After the epitaxial growth, an isolation process is performed to define the region between the devices and to deposit the source electrode and the drain electrode (S30).

That is, after epi growth, a source electrode is formed on the barrier layer or the cap layer as shown in FIG. 8C. The source electrode is formed at a portion where no gate electrode is formed, and is made of metal. The source electrode is formed of ohmic contacts.

After epi growth, as shown in FIG. 8C, a drain electrode is formed on the barrier layer or the cap layer. The drain electrode is also formed in a portion where the gate electrode is not formed and is made of metal. The drain electrode is also formed by ohmic contact.

Referring to FIG. 5, the recess region may be formed in a plurality of etching regions discontinuously. In addition, referring to FIG. 6, in the recess region, a plurality of etching regions may be arranged in a predetermined pattern. In FIG. 5 or FIG. 6, only circular or elliptical shapes are disclosed, but may have other shapes. In addition, in FIG. 6, although the form arranged in two lines, it may be arranged in a different pattern. Discontinuous and partially etched regions can extend the depletion region not only on the z axis but also on the x and y axes to create a normally off characteristic. In order to make the normally off characteristic, it is preferable to set the distance between the etching regions to 1 to 100 nm.

In the above embodiments, the forming of the recess region may be performed by discontinuously and partially etching the portion of the two-dimensional electron gas channel without removing all of the two-dimensional electron gas channels formed on the upper portion of the buffer layer, that is, below the portion where the buffer layer and the barrier layer contact each other. To exist. The remaining two-dimensional electron gas channels, which are not all removed, can minimize current reduction.

The recess process etches the barrier layer using chlorine-based etch gases, for example Cl ₂ and BCl ₃ -based gases. In addition, the recess process can etch to the upper or lower layer, that is, the buffer layer, of the 2DEG channel using an etching gas. The gate electrode is deposited over the recessed region (S50). The width of the gate electrode region may be the same as the recess region or may extend by 0 to 5 μm in the region of the source electrode or the drain electrode. The gate electrode is preferably made of an electrode having a high work function such as Ni, Ir, Pd, or Pt.

The manufacturing methods may further include forming a gate insulating layer on the recess region. The gate insulating film layer is made of at least one of silicon oxide, hafnium oxide, aluminum oxide, and silicon nitride. Here, the gate electrode is formed on the gate insulating film layer. The nitride semiconductor device may have a MIS (Metal-Insulator-Semiconductor) structure.

The gate insulating film layer may be formed by various methods. For example, based on at least one of metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, sputtering, and atomic layer deposition. For example, a source electrode is formed on a substrate grown to a barrier layer or a cap layer through a fabrication process, a gate insulating layer is deposited using a thermal evaporator or PECVD, and then a gate electrode is formed on the deposited gate insulating layer do.

As described above, the nitride semiconductor device and the method of manufacturing the same according to the embodiments of the present invention solve the problem of current characteristic reduction caused by the conventional recess process by partially etching the region under the gate during the recess gate process. In this way, the characteristics of the semiconductor device can be improved. Embodiments of the present invention can compensate for a current reduction phenomenon occurring during the recess process by minimizing a channel region in which electron concentration is reduced through discontinuous partial etching of the region under the gate, and discontinuous partial etching. The depletion region having a large surface area occurring in one region can change the normally on form, which is a disadvantage of a nitride semiconductor device, for example, an HFET device, to a normally off form.

1: substrate 10: buffer layer
20: barrier layer 30: recessed region
31: etching region 40: gate electrode
41: gate insulating layer 50: source electrode
60: drain electrode

Claims (21)

A buffer layer formed on the substrate and made of a nitride semiconductor;
A barrier layer having a recessed region, said barrier layer formed over said buffer layer;
A gate electrode formed on the recess region; And
And a source electrode and a drain electrode respectively contacted on the barrier layer.
The recess area is,
A nitride semiconductor device, wherein the nitride semiconductor element is formed between the source electrode and the drain electrode and has an area equal to or smaller than the area occupied by the gate electrode. The method according to claim 1,
The recess area is,
A nitride semiconductor device, characterized in that a plurality of etching regions are formed discontinuously. The method of claim 2,
The recess area is,
The nitride semiconductor device is characterized in that the plurality of etching regions are arranged in a predetermined pattern. The method of claim 2,
The distance between the plurality of etching regions, 1 to 100 nanometers, characterized in that the nitride semiconductor device. The method according to claim 1,
The buffer layer,
The upper two-dimensional electron gas channel,
The recess area is,
The nitride semiconductor device is formed on the two-dimensional electron gas channel or to the depth of a portion of the buffer layer. 6. The method of claim 5,
The recess area is,
The nitride semiconductor device of claim 2, wherein the two-dimensional electron gas channel is etched to exist. The method according to claim 1,
The gate electrode
And a gate insulating layer formed over the recess region. The method of claim 7, wherein
The gate insulating layer is,
A nitride semiconductor device comprising at least one of silicon oxide, hafnium oxide, aluminum oxide, and silicon nitride. 9. The method according to any one of claims 1 to 8,
Wherein:
An insulating substrate, a gallium nitride substrate, a silicon carbide substrate, and a silicon substrate. 9. The method according to any one of claims 1 to 8,
The buffer layer,
A nitride semiconductor device comprising gallium nitride and having a thickness of 0.5 to 10 micrometers. 9. The method according to any one of claims 1 to 8,
Wherein the barrier layer comprises
A nitride semiconductor device comprising aluminum gallium nitride and having a thickness of 0 to 100 nanometers. 9. The method according to any one of claims 1 to 8,
And a cap layer formed between the barrier layer and the electrodes and formed of aluminum gallium nitride. Forming a buffer layer on the substrate;
Forming a barrier layer over the buffer layer;
Forming a source electrode and a drain electrode on the barrier layer;
Forming a recessed region in the barrier layer between the source electrode and the drain electrode; And
Forming a gate electrode over the recess region;
Wherein forming the recessed region comprises:
And the recess region is formed to have an area equal to or smaller than the area occupied by the gate electrode. The method of claim 13,
Wherein forming the recessed region comprises:
And forming a plurality of etching regions discontinuously. 15. The method of claim 14,
Wherein forming the recessed region comprises:
The nitride semiconductor device is etched so that a portion of the two-dimensional electron gas channel present on the buffer layer. 15. The method of claim 14,
Wherein forming the recessed region comprises:
And arranging the plurality of etching regions in a predetermined pattern. 15. The method of claim 14,
Wherein forming the recessed region comprises:
And forming a distance between the plurality of etching regions to be 1 to 100 nanometers. The method of claim 13,
Wherein forming the gate electrode comprises:
Forming a gate insulating layer in the recess region; And
Forming the gate electrode on the gate insulating layer; and manufacturing the nitride semiconductor device. 19. The method according to any one of claims 13 to 18,
Wherein forming the source electrode and the drain electrode comprises:
The source electrode or the drain electrode is formed by an ohmic contact. 19. The method according to any one of claims 13 to 18,
The buffer layer and the barrier layer,
A method of manufacturing a nitride semiconductor device, characterized in that it is formed based on one or more of metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, sputtering, and atomic layer deposition. 19. The method according to any one of claims 13 to 18,
And forming a cap layer on the barrier layer using aluminum gallium nitride.

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