KR101952176B1 - Enhancement nitride semiconductor device and method for manufacturing the same - Google Patents

Abstract

An enhancement nitride semiconductor device and a method of manufacturing the same are disclosed. The embodiments of the present invention improve the stability and leakage current characteristics of the enhancement nitride semiconductor device and improve the problems of the conventional recess gate etching process and insulating film application process exposed in the atmosphere. Embodiments of the present invention prevent recessed etched surfaces from contacting the atmosphere by depositing a recessed gate process and boron nitride with high electrical insulation by ICP (Inductive Coupled Plasma) etch equipment, So that the manufacturing process can be simplified and the time can be shortened. Embodiments of the present invention not only prevent the substrate from being exposed to the atmosphere by allowing the coating after etching to proceed directly in a chamber but also use a boron nitride which is a material having excellent electrical insulation as a gate insulating film, , Thereby improving the stability of the device and device manufacturing process.

Description

TECHNICAL FIELD [0001] The present invention relates to an enhancement nitride semiconductor device,

The present invention relates to a nitride semiconductor device manufactured by in-situ lithography and a redeposition process, and a method of manufacturing the same.

The nitride semiconductor is a broadband bandgap compound semiconductor and is capable of emitting light up to a visible range and broadly to the ultraviolet range. Blue-violet laser diodes and blue light-emitting diodes are used in a wide range of fields ranging from optical pickup devices, traffic lights, public displays, liquid crystal backlights, and lighting.

Nitride semiconductors are attracting attention due to their high critical electric field, low on resistance, high temperature and high frequency operation characteristics compared to silicon and are being studied as materials for next generation semiconductor devices.

BACKGROUND ART [0002] Metal-oxide semiconductor field-effect-transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) are generally used for high output power devices. In addition, devices such as a high electron mobility transistor (HEMT), a heterojunction field-effect transistor (HFET), and a MOSFET are studied as a gallium nitride (GaN) . HEMTs are used for high frequency communication devices and the like by using high mobility of electrons.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET). Referring to FIG. 1, a general HFET includes a substrate 1, a first GaN layer 2 formed on the substrate, an AlGaN layer 3 formed on the first GaN layer, 2 GaN layer 4, a gate electrode 5, a source electrode 6 and a drain electrode 7 formed on the second GaN layer.

Such an HFET device is excellent in voltage and current characteristics and has been tried to be used as a high output power device. However, it has a disadvantage in that it has a normally-on mode unlike other devices such as a MOSFET and an IGBT. In the case of the normally-on element, the complexity is increased in making up the circuit, and it is difficult to make it. For this reason, plasma treatment, p-GaN growth, and recess gate have been studied to increase the threshold voltage.

The recess gate method, which is the most common method of increasing the threshold voltage, is a method of etching the AlGaN layer under the gate to lower the concentration of 2DEG (2 Dimensional Electron Gas) flowing in the region. Generally, a MISHFET (Metal Insulator Semiconductor HFET) device for applying an insulating film after a recessing process is applied because a structural change due to plasma energy occurs through a recess process and leakage current increases to a gate region.

When the insulating film is applied after the recessing process, the chamber is moved and transferred. In this case, the etched recessed region is exposed to the atmosphere. When the recess region is exposed to the atmosphere, electrons in the atmosphere react with plasma energy to exist in the etching region, thereby reducing the effect of the insulating film coating.

As a method for overcoming this problem, a method of treating an acid series solution such as HF and a method of performing an additional plasma treatment have been studied. However, in the case of the acid-based solution treatment, if the treatment is performed for a short time, the characteristics of the device are improved. However, if the treatment time is exceeded, the device structure is affected and the characteristics are deteriorated. Further, in the case of the plasma treatment, a phenomenon which is not stable in the subsequent heat treatment step and high temperature operation occurs.

Embodiments of the present invention are directed to a method of manufacturing an enhancement nitride semiconductor device that overcomes the problems of the existing recess gate etching process and the insulation film application process that are exposed to the atmosphere, and an enhancement nitride semiconductor device There is a purpose.

Embodiments of the present invention are directed to an enhancement nitride semiconductor device that improves leakage current characteristics while implementing a normally off mode within an etch device without an additional process using an in-situ recess and a redeposition process. A method of manufacturing a device, and an enhancement nitride semiconductor device therefor.

A method of fabricating an enhancement nitride semiconductor device according to an embodiment includes forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a source electrode and a drain electrode on the barrier layer, Defining a recess region on the barrier layer between the source electrode and the drain electrode and etching the barrier layer or etching the barrier layer and a portion of the upper portion of the buffer layer to form the recess region Forming a gate insulating film on the recessed region in an in-situ manner; and forming a gate electrode on the gate insulating film.

The forming of the recessed region may include etching the recessed region to a region where the two-dimensional electron gas channel formed on the buffer layer is formed using at least one etching gas.

Further, in the step of forming the recessed region, the recessed region is formed by using an inductively coupled plasma apparatus.

The forming of the gate insulating layer may include forming the gate insulating layer using the inductively coupled plasma equipment. In the step of forming the gate insulating film, boron chloride gas may be used to form the gate insulating film made of boron nitride on the recessed region.

A method of fabricating an enhancement nitride semiconductor device according to another embodiment includes forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a cap layer on the barrier layer using aluminum gallium nitride, Forming a source electrode and a drain electrode on the cap layer; defining a recess region on the cap layer between the source electrode and the drain electrode; etching the barrier layer and the cap layer; Etching the barrier layer and the cap layer to form the recessed region; forming a gate insulating film on the recessed region in-situ; forming a gate electrode on the gate insulating film; And a step of forming the second electrode.

The enhancement nitride semiconductor device according to the embodiments of the present invention can be manufactured by the manufacturing method according to the above embodiments.

The embodiments of the present invention improve the stability and leakage current characteristics of the enhancement nitride semiconductor device and improve the problems of the conventional recess gate etching process and insulating film application process exposed in the atmosphere.

Embodiments of the present invention prevent recessed etched surfaces from contacting the atmosphere by depositing a recessed gate process and boron nitride with high electrical insulation by ICP (Inductive Coupled Plasma) etch equipment, So that the manufacturing process can be simplified and the time can be shortened.

Embodiments of the present invention not only prevent the substrate from being exposed to the atmosphere by allowing the coating after etching to proceed directly in a chamber but also use a boron nitride which is a material having excellent electrical insulation as a gate insulating film, , Thereby improving the stability of the device and device manufacturing process.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary diagram illustrating the general structure of a heterojunction field effect transistor (HFET);
FIGS. 2 and 3 illustrate structures of an enhancement nitride semiconductor device according to embodiments of the present invention; FIGS.
4 is a flow diagram schematically illustrating a method of fabricating an enhancement nitride semiconductor device according to one embodiment;
FIGS. 5A to 5F are illustrations for explaining the operation of manufacturing a nitride semiconductor according to an embodiment; FIGS. And
6A to 6D are views showing various types of recessed regions in the embodiments of the present invention.

Referring to FIG. 2, an enhancement nitride semiconductor device according to an embodiment includes a buffer layer, a barrier layer, and a gate electrode, a source electrode, and a drain electrode.

The buffer layer 10 is formed on the substrate 1 and made of nitride. The barrier layer 20 is formed on the buffer layer 10 and is composed of nitride and hetero-nitride which constitute the buffer layer 10. A gate electrode (40) is formed over the recessed region (30). The recess region 30 is formed by etching a part of the upper portion of the barrier layer 20 or the barrier layer 20 and the buffer layer 10 by various kinds of etching equipment, for example, ICP (Inductive Coupled Plasma) etching equipment .

A gate insulating film layer 41 is formed on the lower portion of the gate electrode 40, that is, on the recess region 30. Here, the gate insulating film layer 41 is formed by the equipment in which the recess region 30 is etched. The source electrode 50 and the drain electrode 60 are each in contact with the barrier layer 20.

The substrate 1 may be an insulating substrate such as a sapphire substrate or the like. The substrate 1 may be formed of one of a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and a silicon (Si) substrate. The substrate 1 may be removed after fabrication of the nitride semiconductor device. In this case, the structure of the final device may be a structure in which the substrate 1 is not provided.

The buffer layer 10 is a undoped GaN layer (undoped GaN) or a high resistance GaN layer doped with one of Carbon, Iron (Fe), Magnesium (Mg), and combinations thereof. The thickness of the buffer layer 10 may be 0.5 to 10 micrometers (μm), preferably 0.6 to 3 μm. The impurity concentration doped in the buffer layer 10 has a 1e17 / cm ³ to about 1e20 / cm ^3. Preferably, so as to have a concentration of 1e18 / cm ³ to about 1e19 / cm ^3. A two dimensional electron gas (2DEG) is formed on the upper portion of the buffer layer 10, that is, below the portion where the buffer layer 10 and the barrier layer 20 abut each other.

The buffer layer 10 may be formed by various methods. A metal organic chemical vapor deposition (MOCVD), a molecular beam epitaxy (MBE), a hydride vapor phase epitaxy (HVPE), a plasma enhanced chemical vapor deposition (PECVD), Sputtering, and Atomic Layer Deposition (ALD). However, considering the crystallinity of the buffer layer 10, the buffer layer 10 is generally fabricated by metal-organic chemical vapor deposition. TMGa as a raw material of Ga, and NH ₃ as a raw material of N are synthesized at a high temperature in a reactor to perform epitaxial growth.

Although not shown, the buffer layer 10 may include a low-resistance layer between the buffer layer 10 and the substrate 1. The low-resistance layer is generally made of an n-type gallium nitride (n-GaN). The thickness of the low resistance layer is 0.01 to 10 micrometers ([mu] m). Preferably, the low resistance layer is grown to a thickness of 0.1 to 2 μm. The low resistance layer may also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, etc., as well as the buffer layer.

Although not shown, an AlGaN layer of Al _x Ga _{1 - x} N (0 _{? X} ? 1) may be further formed between the buffer layer 10 and the substrate 1.

The barrier layer 20 is made of aluminum gallium nitride (AlGaN), that is, Al _x Ga _{1 - x} N (0 _{? X} ? 1). The thickness of the barrier layer 20 is 0 to 100 nanometers (nm). Preferably 0 to 20 nm. The Al composition of AlGaN is about 1 to 100%, preferably about 10 to 50%. The barrier layer 20 may also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, or the like, in the same manner as the buffer layer 10.

For example, as shown in FIGS. 5A and 5B, the GaN buffer layer 10 on which the 2DEG is formed is grown on the substrate 1 in the range of 0.5 to 10 μm, preferably 0.6 to 3 μm. Then, the AlGaN barrier layer The nitride semiconductor layer 20 is grown to a thickness of 0 to 100 nm, preferably 0 to 20 nm, to produce a nitride semiconductor device according to an embodiment.

Referring to FIG. 3, the nitride semiconductor device according to another embodiment includes a buffer layer 10 formed on a substrate 1 and made of nitride, a buffer layer 10 formed on the buffer layer 10, A cap layer 70 formed on the barrier layer, a source electrode 50 and a drain electrode 60 which are in contact with the cap layer 70, respectively, and a barrier layer 20 formed of a nitride and a hetero- A gate insulating film layer 41 formed on the recess region 30 formed between the gate electrode 50 and the drain electrode 60 and a gate electrode 40 contacting the gate insulating film layer 41 do. Here, as described in one embodiment, the etching of the recess region and the formation of the gate insulating film layer are performed by the same etching equipment.

Like the barrier layer 20, the cap layer 70 is made of aluminum gallium nitride (AlGaN), that is, Al _x Ga _{1 - x} N (0 _{? X} ? 1). The Al composition may be 0 to 100%. The thickness is 0 to 10 nanometers, preferably 0 to 5 nm.

In this case, the recessed region 30 is formed by etching the cap layer 70 and the barrier layer 20, or by etching a part of the cap layer 70, the barrier layer 20 and the buffer layer 10 . The recess region 30 is formed by etching a part of the cap layer 70, the barrier layer 20 and the buffer layer 10 by various kinds of etching equipment, for example, ICP (Inductive Coupled Plasma) etching equipment.

For example, as shown in FIGS. 5A and 5B, the GaN buffer layer 10 on which the 2DEG is formed is grown on the substrate 1 in the range of 0.5 to 10 μm, preferably 0.6 to 3 μm. Then, the AlGaN barrier layer (20) is grown to a thickness of 0 to 100 nm, preferably 0 to 10 nm. Then, the AlGaN cap layer 70 is grown to 0 to 10 nm, preferably 0 to 5 nm, to fabricate the nitride semiconductor device according to another embodiment.

After the epitaxial growth, the isolation process is performed to define the inter-device region, and the source electrode and the drain electrode are deposited.

That is, after the epitaxial growth, the source electrode 50 is formed on the barrier layer 20 or the cap layer 70, as shown in FIG. 5C. The source electrode 50 is formed in a portion where the gate electrode 40 is not formed, and is made of metal.

The source electrode 50 is formed by ohmic contact. For example, the source electrode 50 uses a Ti / Al-based structure, which may be used after heat treatment or without heat treatment. For example, the source electrode 50 may be patterned by a lift-off process by depositing Ti / Al / Ti / Au with a thickness of 30/100/20/200 nm using an electron beam evaporator .

After the epitaxial growth, the drain electrode 60 is formed on the barrier layer 20 or the cap layer 70, as shown in Fig. 5C. The drain electrode 60 is formed in a portion where the gate electrode 40 is not formed, and is made of metal.

The drain electrode 60 is formed by ohmic contact. For example, the drain electrode 60 uses a Ti / Al-based structure, which may be used after heat treatment or without heat treatment.

After the source electrode 50 and the drain electrode 60 are contacted, the recess region 30 is defined and the recess process is performed as shown in FIG. 5D.

The recessing process etches the barrier layer or etches the cap layer and the barrier layer using a chlorine-based etch gas, for example Cl ₂ and BCl ₃ based gas. In addition, the recess process can etch to the upper or lower layer, that is, the buffer layer, of the 2DEG channel using an etching gas. The gate electrode 40 is deposited over the recessed region 30 and the width of the region is equal to the recessed region or in the region of the source electrode 50 or the drain electrode 60 in the range of 0 to 5 micrometers μm). The gate electrode 40 is preferably made of an electrode having a high work function such as Ni, Ir, Pd, or Pt.

At this time, as shown in FIG. 5E, boron nitride (BN) used as a gate dielectric is deposited using only BCl ₃ gas with low RF power and high ICP power. That is, the gate insulating film may be formed of at least one of silicon oxide (SiO ₂ ), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), and silicon nitride (SiN). In the present invention, the recess region is etched using an ICP apparatus, and a gate insulating film layer is formed using a part of the etching gas. Therefore, boron nitride can be deposited as a gate insulating film.

The boron nitride (BN) is a laminate structure having hexagonal faces similar to graphite, and the bond between BN is an SP ² covalent bond, and therefore, it is an insulator and has very tight bonding properties. In addition, the interlayer has a slip property in a gentle layer by van der Waals bonding. The boron nitride has characteristics such as high thermal conductivity, high temperature stability, thermal shock resistance, high temperature insulation, and chemical stability.

Therefore, the gate insulating film layer 41 prevents leakage current of the gate electrode. Here, as shown in FIG. 5F, a gate electrode is formed on the gate insulating film layer 41. The nitride semiconductor device may have a MIS (Metal-Insulator-Semiconductor) structure.

6A to 6D are views showing various forms of the recess region. 6A to 6D, the recess region 30 may be formed in a rectangular shape (FIG. 6A), a trench shape (FIG. 6B), a V- groove shape (FIG. 6C), semicircular shape (FIG. 6D), and the like. The gate insulating film layer 41 may further include an oxide film layer 41a formed on the barrier layer 20 or the cap layer 70. [ As the oxide film, at least one of silicon oxide, hafnium oxide, aluminum oxide, and silicon nitride may be used.

Referring to FIG. 4, a method of fabricating an enhancement nitride semiconductor device according to an embodiment includes forming a buffer layer on a substrate (S10), forming a barrier layer on the buffer layer (S20) (S30) forming a source electrode and a drain electrode on the substrate, defining a recess region on the barrier layer between the source electrode and the drain electrode, etching a part of the buffer layer and the barrier layer, Forming a gate insulating film on the recess region in-situ; and forming a gate electrode on the gate insulating film (S60). .

The buffer layer is a undoped GaN layer (undoped GaN) or a high resistance GaN layer doped with one of carbon, iron (Fe), magnesium (Mg), and combinations thereof. The thickness of the buffer layer is preferably 0.5 to 10 μm, and more preferably 0.6 to 3 μm. The impurity concentration doped in the buffer layer is a 1e17 / cm ³ to about 1e20 / cm ^3. Preferably, so as to have a concentration of 1e18 / cm ³ to about 1e19 / cm ^3. A two-dimensional electron gas (2DEG) is formed on the upper portion of the buffer layer, that is, below the portion where the buffer layer and the barrier layer abut each other.

The buffer layer may be formed by various methods. For example, based on at least one of metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, sputtering, and atomic layer deposition. However, considering the crystallinity of the buffer layer, the buffer layer is generally fabricated by metal-organic chemical vapor deposition. TMGa as a raw material for Ga, NH ₃ as a raw material for N is synthesized at a high temperature in a reactor to perform epitaxial growth (S10).

The barrier layer is made of aluminum gallium nitride (AlGaN), that is, Al _x Ga _{1 - x} N (0 _{? X} ? 1). The thickness of the barrier layer is 0 to 100 nm, preferably 0 to 20 nm. The Al composition of AlGaN is grown to about 1 to 100%, preferably about 10 to 50% (S20). The barrier layer, like the buffer layer, may also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, and the like.

After the epitaxial growth, an isolation process is performed to define an inter-device region and a source electrode and a drain electrode are deposited (S30).

In the step of forming the recess region (S40), the recess region is formed by etching to a region where the two-dimensional electron gas channel formed above the buffer layer is formed by using at least one etching gas.

Referring to FIG. 4 again, a method of fabricating an enhancement nitride semiconductor device according to another embodiment includes forming a buffer layer on a substrate (S10), forming a barrier layer on the buffer layer (S20) (S21) forming a cap layer using aluminum gallium nitride on the barrier layer, forming a source electrode and a drain electrode on the cap layer, and forming a cap layer on the cap layer between the source electrode and the drain electrode. (S40) of forming a recess region by etching a portion of the buffer layer, the barrier layer and the cap layer, and forming a gate insulating film on the recess region in-situ (S50); and forming a gate electrode on the gate insulating film (S60).

Like the barrier layer, the cap layer is made of aluminum gallium nitride (AlGaN), that is, Al _x Ga _1-x N (0 _{? X} ? 1). The Al composition may be 0 to 100%. The thickness is 0 to 10 nm, preferably 0 to 5 nm. The cap layer can also be formed by metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition and the like, as well as the buffer layer and barrier layer.

After the epitaxial growth, an isolation process is performed to define an inter-device region and a source electrode and a drain electrode are deposited (S30).

In this case, the step of forming the recessed region (S40) forms a recessed region by etching the cap layer, the barrier layer and a part of the buffer layer. The recess region is formed by etching a part of a cap layer, a barrier layer, and a buffer layer by various types of etching equipment, for example, an ICP (Inductive Coupled Plasma) etching equipment.

In the step S40 of forming the recessed region, the recessed region is formed using an ICP (Inductively Coupled Plasma) apparatus. The recessing process etches the barrier layer or etches the cap layer and the barrier layer using a chlorine-based etch gas, for example Cl ₂ and BCl ₃ based gas. In addition, the recessing process can etch a 2DEG channel or a lower layer, that is, a buffer layer, using an etching gas (S40).

Forming a gate insulation film (S50), can by using boron chloride (BCl ₃₎ gas to form a gate insulating film in the boron nitride over the recessed region. Boron nitride (BN) used as a gate dielectric is deposited using only BCl ₃ gas at low RF power and high ICP power (S 50). That is, the gate insulating film may be formed of at least one of silicon oxide (SiO ₂ ), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), and silicon nitride (SiN). In the present invention, since the recess region is etched using the ICP equipment and the gate insulating film layer is formed using a part of the etching gas, the in-situ gate insulating film is formed immediately after the recess formation by using the etching apparatus. . Therefore, boron nitride can be deposited as a gate insulating film.

A gate electrode is formed on the gate insulating film layer (S60). The nitride semiconductor device may have an MIS structure. The width of the region of the gate electrode may be the same as the recess region or may be extended by 0 to 5 占 퐉 in the region of the source electrode or the drain electrode. The gate electrode is preferably made of an electrode having a high work function such as Ni, Ir, Pd, or Pt.

INDUSTRIAL APPLICABILITY As described above, the enhancement nitride semiconductor device and the manufacturing method thereof according to the embodiments of the present invention improve the problems of the conventional recess gate etching process and the insulating film applying process that are exposed to the atmosphere, Thereby improving the stability of the device and the leakage current characteristic. Embodiments of the present invention are directed to depositing a recess gate process and boron nitride with high electrical insulation by means of ICP etch equipment to prevent the recess etched surface from contact with the atmosphere and to avoid cleaning and patterning again The manufacturing process can be simplified and the time can be shortened. Embodiments of the present invention can reduce the leakage current by using boron nitride, which is a material having excellent electrical insulation, as a gate insulating film, as well as preventing exposure to the atmosphere by allowing coating after etching to proceed directly in a chamber, And the stability of the device manufacturing process.

1: substrate 10: buffer layer
20: barrier layer 30: recessed region
40: gate electrode 41: gate insulating film layer
50: source electrode 60: drain electrode
70: cap layer

Claims (15)

Forming a buffer layer on the substrate;
Forming a barrier layer over the buffer layer;
Forming a source electrode and a drain electrode on the barrier layer;
Defining a recess region on the barrier layer between the source electrode and the drain electrode, etching the barrier layer, or etching a portion of the upper portion of the buffer layer and the barrier layer to form the recess region;
Forming a gate insulating film on the recessed region in-situ; And
And forming a gate electrode on the gate insulating film. The method according to claim 1,
Wherein forming the recessed region comprises:
Wherein the recess region is formed by etching to a region where a two-dimensional electron gas channel formed above the buffer layer is formed by using at least one etching gas to form the recess region. 3. The method of claim 2,
Wherein forming the recessed region comprises:
Wherein the recessed region is formed by using an inductively coupled plasma device. The method of claim 3,
Wherein forming the gate insulating film comprises:
Wherein the gate insulating film is formed using the inductively coupled plasma device. The method of claim 3,
Wherein forming the gate insulating film comprises:
Wherein said boron chloride gas is used to form said gate insulating film made of boron nitride on said recessed region. 6. The method according to any one of claims 1 to 5,
Wherein forming the source electrode and the drain electrode comprises:
Wherein the source electrode or the drain electrode is formed by ohmic contact. 6. The method according to any one of claims 1 to 5,
Wherein the buffer layer and the barrier layer are made of a single-
Wherein the at least one layer is formed based on at least one of metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, plasma chemical vapor deposition, sputtering, and atomic layer deposition. 6. The method according to any one of claims 1 to 5,
And forming a cap layer on the barrier layer using aluminum gallium nitride. ≪ RTI ID = 0.0 > 11. < / RTI > A buffer layer formed on the substrate and made of nitride;
A barrier layer formed on the buffer layer and composed of the nitride and the heteronitride forming the buffer layer;
A source electrode and a drain electrode respectively contacting the barrier layer;
A gate insulating layer formed on the barrier layer or the recess region formed by etching the barrier layer and a part of the upper portion of the buffer layer and made of boron nitride; And
And a gate electrode contacting the gate insulating film layer,
Wherein the gate insulating film layer is formed in an in-situ shape after the recessed region is formed by etching. 10. The method of claim 9,
The recess region and the gate insulating film layer may be formed,
Is formed by the same etching equipment. 11. The method according to claim 9 or 10,
Wherein:
An insulating substrate, a gallium nitride substrate, a silicon carbide substrate, and a silicon substrate. 11. The method according to claim 9 or 10,
The buffer layer may be formed,
Gallium nitride, and a thickness of 0.5 to 10 占 퐉. 11. The method according to claim 9 or 10,
Wherein the barrier layer comprises
Aluminum gallium nitride and having a thickness of more than 0 nanometers and less than 100 nanometers. 11. The method according to claim 9 or 10,
Wherein the recessed region comprises:
Trench shape, V-groove shape, semicircular shape, and stepped shape. 11. The method according to claim 9 or 10,
And a cap layer formed on the barrier layer and made of gallium nitride or aluminum gallium nitride.

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