JP5379391B2 - Semiconductor device comprising gallium nitride compound semiconductor and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for high-breakdown-voltage/high-current and low-loss power by dramatically reducing ohmic contact resistance with a semiconductor operating layer of an electrode in a semiconductor device made of a gallium-nitride compound semiconductor. <P>SOLUTION: A semiconductor device is provided with a semiconductor operating layer and at least one electrode formed on the semiconductor operating layer. The semiconductor operating layer is made of a gallium-nitride compound semiconductor having a hetero-junction structure provided with at least an electron traveling layer 15 and an electron supply layer 18 on a substrate 14. The electrode is formed at a recess part 20 reaching the electron traveling layer 15 through the electron supply layer 18. The recess part 20 is configured such that its longitudinal direction is formed along in a direction of a current flowing in the semiconductor operating layer having the electron traveling layer 15 and the electron supply layer 18. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device made of a gallium nitride (GaN) -based compound semiconductor and a manufacturing method thereof, and more particularly, a semiconductor device made of a gallium nitride-based compound semiconductor capable of reducing ohmic contact resistance with the semiconductor at the electrode and The present invention relates to a method of manufacturing a field effect transistor made of a gallium nitride compound semiconductor.

  GaN-based compound semiconductors such as GaN, InGaN, AlGaN, and AlInGaN have a larger band gap energy than semiconductor materials such as Si and GaAs. Electronic devices using this semiconductor material have a high dielectric breakdown voltage and high electron resistance. In recent years, it has come to be used as a power device for controlling high voltage and large current because of its excellent physical properties such as mobility and high heat-resistant temperature.

High electron mobility transistors (HEMTs), which are one of FET (field effect transistors) using nitride-based (GaN) compound semiconductors, are placed on a substrate such as silicon or sapphire in order from the bottom to the top. On the other hand, a buffer layer made of a GaN-based semiconductor, an electron transit layer made of undoped GaN, and an electron supply layer made of undoped Al _a Ga _1-a N (0 <a <1) thinner than the electron transit layer are stacked. A hetero-junction structure. A source electrode, a gate electrode, and a drain electrode are disposed on the electron supply layer. Here, in such a field effect transistor, in order to reduce the contact resistance with the electron supply layer of the source electrode and the drain electrode, an n-GaN contact region doped with a high concentration of n-type impurities is provided. Conventionally known to those skilled in the art.

However, in such a field effect transistor using HEMT, when the source electrode and the drain electrode form an ohmic contact resistance (resistance value: R) between the electron supply layer or the current traveling layer, the current flowing through the transistor is reduced. Power loss (I ² R) proportional to the square of the value (current value: I) is generated, and in a power control device that controls a large current, this ohmic contact resistance is further reduced. It was strongly desired.

  Therefore, as a first example of the prior art, as shown in FIG. 6, a first III-V nitride semiconductor layer having a two-dimensional electron gas layer formed on a substrate, and a first III A second group III-V nitride semiconductor layer formed on the group V nitride semiconductor layer and having a band gap larger than that of the first group III-V nitride semiconductor; An ohmic electrode formed through the group V nitride semiconductor layer and reaching a region below the two-dimensional electron gas layer in the first group III-V nitride semiconductor layer; and a first group III-V nitride There is known a semiconductor device including an impurity doped layer formed by introducing an impurity having conductivity in a portion in contact with an ohmic electrode in an oxide semiconductor layer and a second group III-V nitride semiconductor layer (For example, refer to Patent Document 1).

Further, as a second example of the prior art, as shown in FIG. 7, the aluminum gallium nitride layer includes a gallium nitride layer laminated on a substrate and an aluminum gallium nitride layer laminated on the gallium nitride layer. A gallium nitride-based transistor having a plurality of opening grooves formed in a part or the whole of the layer, including at least two of the plurality of opening grooves, and having an ohmic electrode that electrically connects the filled opening grooves Has been proposed (see Patent Document 2).
JP 2007-329350 A JP 2007-227409 A

  However, in the first example of the prior art described above, since the contact area of the ohmic electrode with the two-dimensional electron gas layer (electron transit layer) is small and the contact area cannot be increased, the ohmic contact resistance is sufficiently increased. It could not be reduced.

  In the second example of the prior art described above, since the plurality of V-shaped opening grooves intersect with the direction of current flow between the source electrode and the drain electrode, aluminum gallium nitride which is an electron transit layer Since a large amount of current flowing on the upper surface side of the layer passes through the metal interface between the ohmic contact portion and the aluminum gallium nitride layer many times, it is difficult to reduce the substantial resistance value of the ohmic contact.

  The present invention has been made to solve the above-described problems of the prior art, and by dramatically reducing the ohmic contact resistance between the electrode and the semiconductor operation layer in the semiconductor element made of a gallium nitride compound semiconductor, An object is to provide a power transistor having a high withstand voltage and a large current and low loss.

  For this reason, the present invention provides a semiconductor operation layer made of a gallium nitride compound semiconductor having a heterojunction structure having at least an electron transit layer and an electron supply layer on a substrate, and at least one formed on the semiconductor operation layer. In the semiconductor device comprising an electrode, the electrode is formed in a recess portion that reaches the electron transit layer through the electron supply layer, and the recess portion has a longitudinal direction of the recess portion that is the semiconductor operation layer. The present invention provides a semiconductor device made of a gallium nitride compound semiconductor, characterized by being formed along the direction of a flowing current.

  The present invention also relates to a semiconductor operation layer made of a gallium nitride compound semiconductor having a heterojunction structure having at least an electron transit layer and an electron supply layer on a substrate, and a source electrode and a drain formed on the semiconductor operation layer. In the semiconductor device according to the field effect transistor including an electrode and a gate electrode, the source electrode and the drain electrode are formed in a recess portion that reaches the electron transit layer through the electron supply layer, and the recess portion includes Provided is a semiconductor device characterized in that a longitudinal direction of a recess is formed along a direction of a current flowing between the source electrode and the drain electrode.

  Here, the recess portion in the semiconductor element is formed by a plurality of recess structures arranged in parallel and formed in a comb shape, and is in ohmic contact with the electron transit layer. And the bottom part of the said recess part is located in the said electron transit layer, or is located in the interface of the said electron transit layer and the said electron supply layer.

  The electron transit layer is undoped GaN, and the electron supply layer is undoped or n-type AlGaN.

  The present invention further includes an electric field having a source electrode, a drain electrode, and a gate electrode formed of a gallium nitride compound semiconductor and formed on a heterojunction structure having at least an electron transit layer and an electron supply layer on a substrate. In the method of manufacturing an effect transistor, (a) a step of forming an electron transit layer on the substrate via a buffer layer, (b) a step of forming an electron supply layer on the electron transit layer, (c) Forming a gate electrode in a predetermined region on the electron supply layer; and (d) in the formation region of the source electrode and the drain electrode, the source electrode and the drain electrode pass through the electron supply layer and the electrons. Forming a recessed portion reaching the traveling layer; and (e) the source electrode and the drain electrode are formed in the recessed portion in the electron supply layer. Forming the ohmic contact, wherein the recess portion is formed along a direction of a current flowing between the source electrode and the drain electrode in the longitudinal direction of the recess portion. A method of manufacturing a field effect transistor is provided.

Here, the step (a) includes (a-1) a step of forming an AlN layer on the Si substrate, and (a-2) a step of forming a buffer layer on the AlN layer;
Including each step. The step (d) includes (d-1) a step of forming a mask layer on the electron transit layer, and (d-2) in the formation region of the recess portion of the source electrode and the drain electrode. And removing the mask layer.

  As described above, in the semiconductor device according to the present invention, in the electrode formed on the semiconductor operation layer made of the gallium nitride compound semiconductor having the heterojunction structure, the recess portion that reaches the electron transit layer through the electron supply layer. This recess portion is formed along the direction of the current flowing through the semiconductor operation layer and has an ohmic contact with the electron transit layer, so that an extremely low ohmic resistance is realized as compared with the prior art. .

  Here, the recess portion is formed by a plurality of recess structures arranged in parallel and formed in a comb shape, and is in ohmic contact with the electron transit layer, so that a contact area between the electrode and the electron transit layer is increased and an ohmic resistance is provided. This is a further reduction of this. For this reason, the bottom of the recess is positioned in the electron transit layer or at the interface between the electron transit layer and the electron supply layer.

  Hereinafter, the field effect transistor according to the semiconductor device will be described in detail with reference to the drawings. 1 and 2 show a first embodiment of the field effect transistor. In the first embodiment, the bottoms of the recesses 20 of the drain electrode 11 and the source electrode 13 penetrate the electron supply layer 18 and reach the electron transit layer 15.

Here, the electron transit layer 15 is undoped GaN, and the electron supply layer 18 is undoped or n-type AlGaN. The member of the semiconductor substrate 14 is silicon (Si ) or sapphire, but other members may be used.

FIG. 1A is a schematic view of the field effect transistor according to the first embodiment viewed from the top surface direction. Moreover, FIG.1 (b) shows the "AA '" cross section of Fig.1 (a).
FIG. 2 is a cross-sectional view of the field effect transistor according to the first embodiment. FIG. 2A is a cross-sectional view taken along the line “BB ′” of FIG. These respectively show “CC ′” cross sections of FIG.

  In FIG. 1A, a drain electrode 11 is arranged on the right side, a gate electrode 12 is arranged in the center, and a source electrode 13 is arranged on the left side. Here, when a voltage exceeding a predetermined threshold is applied to the gate electrode 12, a current flows from the right drain electrode 11 side to the left source electrode 13 side (that is, electrons flow to the left source electrode 13. To the right drain electrode 11 side).

  2 (a) and 2 (b), the field effect transistor has an electron transit layer 15 formed on a semiconductor substrate 14 having a buffer layer (14-2 and 14-3 in FIG. 5) on its upper surface. It has a heterojunction structure in which the electron supply layer 18 is laminated on the layer 15. A gate electrode 12, a drain electrode 11, and a source electrode 13 are formed on the heterojunction structure, and a plurality of recess portions 20 are formed at the bottoms of the drain electrode 11 and the source electrode 13. In such a field effect transistor, the electrons generated in the electron supply layer 18 are distributed in a region having a thickness of about 10 nm in the vicinity of the interface with the electron supply layer 18 side in the electron transit layer 15. 16 is formed. For this reason, the bottom part of the drain electrode 11 and the source electrode 13 is brought into contact with the region where the two-dimensional electron gas 16 is distributed in the surface layer of the electron transit layer 15 to obtain a low resistance ohmic contact. Can do it.

  In the first embodiment, the drain electrode 11 and the source electrode 13 have a recess 20 that penetrates the electron supply layer 18 and reaches the inner surface of the electron transit layer 115. As shown in FIG. 1A, the longitudinal direction of the recess 20 is arranged along the direction of the current flowing between the drain electrode 11 and the source electrode 13 so as to be in ohmic contact with the electron transit layer 15 directly. Yes.

  Since the recess 20 is formed by a plurality of comb-shaped recess structures arranged in parallel as shown in FIGS. 1A and 1B, the drain electrode 11 and the source electrode 13 are formed of electrons. Since the contact area of the ohmic contact with the traveling layer 15 is remarkably increased, and the area of ohmic contact with the drain electrode 11 and the source electrode 13 is along the direction of the current flowing between the electrodes 11 and 13. Thus, the ohmic resistance value between the electrodes 11 and 13 and the GaN semiconductor is greatly reduced.

  3 to 4 show a second embodiment of a field effect transistor according to the present semiconductor device. In the second embodiment, the bottoms of the recesses 20 of the drain electrode 11 and the source electrode 13 are located at the interface between the electron supply layer 18 and the electron transit layer 15.

FIG. 3A is a schematic view of the field effect transistor according to the second embodiment viewed from the top surface direction. FIG. 3B shows a cross section “AA ′” in FIG. 3.
4 shows a cross-sectional view of the field effect transistor according to the second embodiment, FIG. 4A shows the “BB ′” cross-section of FIG. 3, and FIG. 3 shows a “CC ′” cross section.

  In FIG. 3A, the drain electrode 11 is arranged on the right side, the gate electrode 12 is arranged in the center, and the source electrode 13 is arranged on the left side. Here, when a voltage exceeding a predetermined threshold is applied to the gate electrode 12, a current flows from the right drain electrode 11 side to the left source electrode 13 side.

  4A and 4B, in the field effect transistor, an electron transit layer 15 is formed on a semiconductor substrate 14 having a buffer layer (reference numeral 14-3 in FIG. 5) on the upper surface. It has a heterojunction structure in which the electron supply layer 18 is laminated. A gate electrode 12, a drain electrode 11, and a source electrode 13 are formed on the heterojunction structure, and recess portions 20 having a plurality of recess structures are formed at the bottoms of the drain electrode 11 and the source electrode 13. . In the second embodiment, the bottoms of the recesses 20 of the drain electrode 11 and the source electrode 13 are located at the interface between the electron supply layer 18 and the electron transit layer 15. The bottom of the source electrode 13 is in ohmic contact.

  Also in the second embodiment described above, the bottom portions of the drain electrode 11 and the source electrode 13 form the recess portion 20, and the longitudinal direction of the recess portion 20 is the drain electrode 11 as shown in FIG. Are arranged in the direction of the current flowing between the source electrode 13 and the ohmic contact with the electron transit layer 15 directly.

  The recess portion 20 is formed by a plurality of recess structures formed in a comb shape arranged in parallel as shown in FIGS. 3A and 3B, so that the drain electrode 11 and the source electrode 13, the contact area of the ohmic contact with the electron transit layer 15 increases dramatically, and the area where the ohmic contact with the drain electrode 11 and the source electrode 13 is in the direction of the current flowing between the electrodes 11 and 13. Therefore, the ohmic resistance value between the electrodes 11 and 13 and the GaN semiconductor is greatly reduced.

The contact resistance of the ohmic contact of the drain electrode 11 and the source electrode 13 in the field effect transistor using the GaN compound semiconductor according to the present invention is approximately 2.9 to 3.6 × 10 ⁻⁶ as an actual measurement value in an experiment under a predetermined condition. (Ωcm ² ), which is a contact resistance of an ohmic contact between a drain electrode and a source electrode and a GaN compound semiconductor substrate in a field effect transistor according to the related art that does not have a recess, and is 7.3 to 14.7 × 10 ⁻ Compared with ⁶ (Ωcm ² ), a reduction of about 60 to 75% was realized.

Next, a method for manufacturing a field effect transistor according to the present invention will be described.
FIG. 5 is a diagram for explaining a method of manufacturing the field effect transistor. FIG. 5A shows a state in which the semiconductor substrate 14 including the buffer layer (14-3) and the electron transit layer 15 and the electron supply layer 18 are formed on the semiconductor substrate 14. Hereinafter, the manufacturing method up to the state shown in FIG.

First, a substrate (14-1) made of silicon carbide (SiC), sapphire, or the like is set in an MOCVD apparatus to perform, for example, metal organic chemical vapor deposition (MOCVD), and hydrogen gas with a concentration of 100% is supplied. Used as a carrier gas, trimethylgallium (TMGa), trimethylaluminum (TMAl), and NH ₃ were introduced at flow rates of 58 μmol / min, 100 μmol / min, and 12 l / min, respectively, and the growth temperature was 1050 ° C. On the substrate (14-1), an AlN layer (14-2), a buffer layer (14-3), and a lower semiconductor layer (14-4) made of undoped GaN are sequentially formed by epitaxial growth.

Next, TMGa and NH ₃ are introduced at a flow rate of 19 μmol / min and 12 l / min, respectively, and an electron transit layer 15 made of undoped GaN is epitaxially grown on the lower semiconductor layer (14-4) at a growth temperature of 1050 ° C. Let Next, TMAl, TMGa, and NH ₃ are introduced at a flow rate of 125 μmol / min, 19 μmol / min, and 12 l / min, respectively, and an undoped −25% Al composition is formed on the electron transit layer 15. The electron supply layer 18 made of AlGaN is epitaxially grown, whereby the semiconductor operation layers 15 and 18 are formed.

  Here, the buffer layer 14-3 is formed by stacking, for example, eight or more GaN / AlN composite layers having a thickness of 200 nm / 20 nm. The thicknesses of the AlN layer (14-2), the lower semiconductor layer (14-4), the electron transit layer 15, and the electron supply layer 18 are 100 nm, 50 nm, 100 nm, and 20 nm, respectively.

  Next, a method for forming the recesses 20 of the source electrode 13 and the drain electrode 11, that is, the recess 20 that reaches the electron transit layer 15 through the electron supply layer 18, which is a feature of the field effect transistor of the present invention, will be described. .

FIG. 5B shows an example where the bottom of the recess 20 is located at the boundary surface between the electron transit layer 15 and the electron supply layer 18. As shown in FIG. 5B, in the region where the recess portion 20 of the source electrode 13 and the drain electrode 11 is formed, it is made of SiO ₂ on the electron supply layer 18 using the plasma enhanced chemical vapor deposition (PCVD) method. The mask layer 21 is formed with a thickness of 200 nm, and patterning is performed using photolithography and GHF ₃ gas to form the opening 22.

Next, using the mask layer 21 as a mask, the electron supply layer 18 is removed by etching using Cl ₂ gas, which is an etching gas, to form a groove for forming the recessed portion 20.

  Then, the etching mask 21 is removed with hydrofluoric acid, and the drain electrode 11 and the source electrode 13 are formed using a lift-off method. Each of these electrodes 11 and 13 has a Ti / Al structure with a thickness of 25 nm / 300 nm, and the metal film can be formed by sputtering or vacuum evaporation. Then, after the electrodes 11 and 13 are formed, annealing is performed at 600 ° C. for 10 minutes.

  As a result, as shown in FIG. 4A, the recess 20 is disposed along the direction of the current flowing in the longitudinal direction between the drain electrodes 11 (or the source electrodes 13), and the surface of the electron transit layer 15 ( The ohmic contact is made at the interface with the electron supply layer 18.

  FIG. 5C shows an example in which the bottom of the recess 20 is positioned in the electron transit layer 15 through the electron supply layer 18.

As shown in FIG. 5C, the source electrode 13 and the drain electrode 11 are made of SiO ₂ on the electron supply layer 18 using a plasma enhanced chemical vapor deposition (PCVD) method in a region where the recess 20 is formed. The mask layer 21 is formed with a thickness of 200 nm, and patterning is performed using photolithography and GHF ₃ gas to form the opening 22. Then, using the mask layer 21 as a mask, a part of the electron transit layer 15 and the electron supply layer 18 are removed by etching using Cl ₂ gas as an etching gas to form a recess 20 that reaches the electron transit layer 15. The groove is made. Since the formation method of the electrodes 11 and 13 is the same as the above-mentioned method, duplication description here is abbreviate | omitted.

  Thereby, as shown in FIG. 2A, the bottoms of the recesses 20 of the electrodes 11 and 13 are arranged along the direction of the current flowing in the longitudinal direction between the drain electrodes 11 (or the source electrodes 13). The ohmic contact is made inside the electron transit layer 15.

  As described above in detail, in the field effect transistor according to the present semiconductor element, the source electrode 13 and the drain electrode 11 have the recess 20 that reaches the electron transit layer 15 through the electron supply layer 18, and this recess 20 is formed along the direction of the current flowing in the longitudinal direction between the source electrode 13 and the drain electrode 11 and is in ohmic contact with the semiconductor operation layers 15 and 18.

  Thereby, the electrodes (source electrode 13 and drain electrode 11) of the field effect transistor according to the present semiconductor element exhibit an ohmic contact having a very low resistance value between the semiconductor operation layers 15 and 18 as compared with the prior art. Made it possible.

  As described above, the semiconductor device according to the present invention is not only a field effect transistor having a heterojunction structure made of a gallium nitride compound semiconductor but also other semiconductor devices such as a diode, HEMT, MOSFET (Metal Oxide Semiconductor FET). It can be applied to transistors such as. In the embodiment, the horizontal field effect transistor has been described. However, the present invention can be applied to a semiconductor element having a vertical structure or a so-called pseudo vertical structure.

  The present invention relates to a semiconductor device using a gallium nitride (GaN) -based compound semiconductor and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the semiconductor device that can reduce ohmic contact resistance between the electrode and a semiconductor operation layer. And has industrial applicability.

FIG. 1A shows a first embodiment of a field effect transistor according to the present semiconductor element, and FIG. 1A shows a schematic view of the field effect transistor according to the first embodiment as viewed from above. ) Shows a cross section “AA ′” in FIG. FIG. 2A is a sectional view of the field effect transistor according to the first embodiment shown in FIG. 1, FIG. 2A is a “BB ′” section of FIG. 1A, and FIG. FIG. 1 (a) shows a “CC ′” cross section. FIG. 3A shows a second embodiment of the field effect transistor according to the present semiconductor element, and FIG. 3A shows a schematic view seen from the upper surface direction of the field effect transistor according to the second embodiment. FIG. 3B shows the “AA ′” cross section of FIG. FIG. 4A is a cross-sectional view of the field effect transistor according to the first embodiment shown in FIG. 3, FIG. 4A is a “BB ′” cross section of FIG. 3A, and FIG. FIG. 3A shows a “CC ′” cross section of FIG. It is a figure for demonstrating the manufacturing method of this field effect transistor.

  FIG. 5A shows a state in which the semiconductor substrate 14 and the electron transit layer 15 and the electron supply layer 18 are formed on the semiconductor substrate 14.

  FIG. 5B shows an example (example of the second embodiment shown in FIG. 3) in which the bottom of the recess 20 is located at the boundary surface between the electron transit layer 15 and the electron supply layer 18.

FIG. 5C shows an example (example of the first embodiment shown in FIG. 1) in which the bottom of the recess 20 is positioned in the electron transit layer 15 through the electron supply layer 18.
The 1st example of the prior art relevant to this field effect transistor is shown. The 2nd example of the prior art relevant to this field effect transistor is shown.

Explanation of symbols

11: Drain electrode 12: Gate electrode 13: Source electrode 14: Semiconductor substrate 15: Electron traveling layer (carrier traveling layer)
18: Electron supply layer (carrier supply layer)
20: Recess part (multiple recess structures)
21: Mask layer 22: Mask layer opening (electrode formation region having recess)

Claims (13)

A semiconductor comprising a semiconductor operating layer made of a gallium nitride compound semiconductor having a heterojunction structure having at least an electron transit layer and an electron supply layer on a substrate, and at least one electrode formed on the semiconductor operating layer In the element
The electrode is formed on a recess that reaches the electron transit layer through the electron supply layer , the recess and the electron supply layer, and is in ohmic contact with the electron transit layer,
The recess portion is formed of a plurality of recess structures arranged in parallel and spaced apart from each other, and the longitudinal direction of the recess structure is formed along the direction of current flowing through the semiconductor operation layer. A semiconductor device comprising a gallium nitride compound semiconductor. The semiconductor element according to claim 1, wherein the electrode is formed in direct contact with the surface of the electron supply layer . The semiconductor element is a field effect transistor including a source electrode, a drain electrode and a gate electrode formed on the semiconductor operation layer ,
The electrode, the semiconductor device according to claim 1 or 2, characterized in that said a source electrode and the drain electrode.   4. The semiconductor device according to claim 1, wherein a bottom portion of the recess portion is located in the electron transit layer.   4. The semiconductor device according to claim 1, wherein a bottom portion of the recess is located at a boundary surface between the electron transit layer and the electron supply layer. 6. The semiconductor device according to claim 4, wherein the electron transit layer is undoped GaN, and the electron supply layer is undoped or n-type AlGaN. Method for manufacturing field effect transistor having source electrode, drain electrode and gate electrode formed on heterojunction structure formed of gallium nitride compound semiconductor and having at least electron transit layer and electron supply layer on substrate (A) forming an electron transit layer on the substrate via a buffer layer;
(B) forming an electron supply layer on the electron transit layer;
(C) forming a gate electrode in a predetermined region on the electron supply layer;
(D) in the formation region of the source electrode and the drain electrode, and forming a recessed portion before SL through the electron supply layer reaches the electron transit layer,
(E) The source electrode and the drain electrode are formed on the recess portion that reaches the electron transit layer through the electron supply layer , the recess portion and the electron supply layer, and the source electrode and the drain electrode are formed includes a step of Ru is ohmic contact with the electron transit layer in the recessed portion, the steps of,
The recess portion is formed of a plurality of recess structures arranged in parallel and spaced apart from each other, and a longitudinal direction of the recess structure is along a direction of a current flowing between the source electrode and the drain electrode. A method of manufacturing a field effect transistor, characterized by being formed. The method of manufacturing a field effect transistor according to claim 7, wherein the electrode is formed in direct contact with the surface of the electron supply layer . The step (a)
Forming an AlN layer on the (a-1) board,
(A-2) forming a buffer layer on the AlN layer;
The method of manufacturing a field effect transistor according to claim 7, comprising the steps of: The step (d)
(D-1) forming a mask layer on the electron transit layer;
(D-2) removing the mask layer in the recessed portion formation region of the source electrode and the drain electrode;
The method of manufacturing a field effect transistor according to claim 7, comprising the steps of: Bottom of the recess portion, a method of manufacturing a field effect transistor according to any one of claims 7 to 9, characterized in that located on the electron transit layer. 10. The method of manufacturing a field effect transistor according to claim 7 , wherein a bottom portion of the recess portion is located at a boundary surface between the electron transit layer and the electron supply layer. 11. 10. The method for manufacturing a field effect transistor according to claim 7 , wherein the electron transit layer is undoped GaN, and the electron supply layer is undoped or n-type AlGaN.

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