KR101291148B1 - N-polar Nitride semiconductor device and method for manufacturing thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an N-polar nitride-based semiconductor device capable of satisfying both ohmic and leakage current characteristics, and a method of manufacturing the same, wherein an N-polar nitride-based epi layer is formed on a substrate, and the nitride-based epi An etch control layer is formed on the layer, and an n-type nitride layer including an n-type dopant is formed on the etch-control layer. Then, the etch control layer and the n-type nitride layer are formed with respect to a predetermined ohmic region. To form a source electrode and a drain electrode in the region from which the etch control layer and the n-type nitride layer are removed, remove the n-type nitride layer other than the lower part of the source electrode and the drain electrode, and then heat-process the source electrode. And forming an ohmic junction on the drain electrode, and forming a gate electrode on the etch control layer.

Description

N-polar nitride-based semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride based semiconductor device and a method for manufacturing the same, and more particularly, to an N-polar nitride based semiconductor device capable of satisfying both ohmic and leakage current characteristics, and a method for manufacturing the same.

Semiconductor devices made of III-nitride materials (hereinafter referred to as " nitride based semiconductor devices ") are known to have very large dielectric breakdown fields of 2.2 MV / cm or more. In addition, since III-nitride heterojunction structures can carry very large currents, nitride-based semiconductor devices are excellent in power applications. In general, nitride-based semiconductor devices based on III-nitride materials have been developed for high power-high frequency applications such as emitters used in base stations of cellular phones. Nitride-based semiconductor devices fabricated for these types of applications are based on common device structures capable of obtaining high electron mobility, which structures include heterojunction field effect transistors (HFETs), High Electron Mobility Transistors (HEMTs) or Doped Modulated Field Effect Transistors (Modulation doped FETs (MODFETs), and the like. Nitride-based semiconductor devices of this type are generally capable of withstanding high voltages of about 100V while operating in a high frequency region of 2 to 100 kHz.

These types of nitride-based semiconductor devices may be modified for many applications, but have a two-dimensional electron cloud (2-DEG) layer that has very low resistive losses and allows for very high current density transport. It is common to operate using piezoelectric polarization fields to produce. In these conventional nitride-based semiconductor devices, 2DEG is formed at the interface of AlGaN / GaN.

In the case of a nitride semiconductor device, a source electrode, a drain electrode, and a gate electrode are formed on an epitaxial layer such as AlGaN / GaN. The source electrode and the drain electrode may be formed by an ohmic junction. At this time, the ohmic resistance of the source-drain electrode is important. If the ohmic resistance is high, the on-resistance of the device is reduced.

The ohmic junction may be formed by depositing a plurality of ohmic metals including Ti and Al through a heat treatment process.

However, according to the conventional method, in order to form ohmic, a high temperature heat treatment process is required, and these high temperature heat treatment processes increase the trap site of the device and cause the leakage current of the device to increase.

In particular, in the case of an N-polar nitride-based semiconductor device, an electron cloud layer (2DEG) is generated in the GaN layer, which is advantageous in that direct control by the gate is easy, whereas the barrier between the GaN layer and the gate electrode is low, resulting in gate leakage. It is easy to generate current and has a high ohmic contact resistance.

Accordingly, the present invention has been proposed to solve the conventional problems, and more particularly, to provide an N-polar nitride-based semiconductor device having an improved ohmic junction characteristic capable of simultaneously satisfying ohmic characteristics and leakage current characteristics, and a manufacturing method thereof. I would like to.

The present invention provides a means for solving the above problems, forming an N-polar nitride-based epi layer on the substrate; Forming an etch control layer on the N-polar nitride-based epi layer; Forming an n-type nitride layer including an n-type dopant on the etch control layer; Removing the etch control layer and the n-type nitride layer with respect to a preset ohmic region; Forming a source electrode and a drain electrode in the region from which the etch control layer and the n-type nitride layer are removed; Etching the exposed n-type nitride layer; Forming an ohmic junction on the source electrode and the drain electrode through a heat treatment; And forming a gate electrode on the visual control layer.

In the method of manufacturing an N-polar nitride-based semiconductor device according to the present invention, the step of forming the N-polar nitride-based epi layer, forming a transition layer on the substrate; Forming an AlGaN buffer layer on the transition layer; And forming a GaN layer on the AlGaN buffer layer to form a two-dimensional electron cloud (2DEG) layer at an interface with the AlGaN buffer layer.

In the method of manufacturing an N-polar nitride-based semiconductor device according to the present invention, the n-type nitride layer is characterized in that the GaN layer doped with n-type.

In the method of manufacturing an N-polar nitride-based semiconductor device according to the present invention, the etch control layer is characterized in that formed of AlGaN.

In the method of manufacturing an N-polar nitride-based semiconductor device according to the present invention, the etching of the n-type nitride layer may include dry etching using an F-containing gas including at least one of SF6, CF4, CHF ₃ , and C2F8. By selectively etching the n-type nitride layer by the.

In addition, the present invention is another means for solving the above problems, a substrate; An N-polar nitride-based epi layer formed on the substrate; An etch control layer made of AlGaN on top of the N-polar nitride-based epi layer; An n-type nitride layer including an n-type dopant formed at an ohmic formation position on the etch control layer; A source electrode and a drain electrode partially removed from the n-type nitride layer at the ohmic formation position and an etch control layer below the portion, and formed in the removed region; And it provides an N-polar nitride-based semiconductor device comprising a gate electrode formed on the etch control layer.

In the N-polar nitride-based semiconductor device according to the present invention, the nitride-based epi layer, the transition layer formed on the substrate; An AlGaN buffer layer formed on the transition layer; And a GaN layer formed on the AlGaN layer to generate a two-dimensional electron cloud (2DEG) layer at an interface with the AlGaN layer.

In the N-polar nitride-based semiconductor device according to the present invention, the n-type nitride layer is a GaN layer doped with n-type.

In the present invention, in the manufacture of an N-polar nitride-based semiconductor device in which an electron cloud layer is formed in a GaN layer, by using a high concentration of n-type GaN, the ohmic contact resistance is reduced and unnecessary thermal stress is achieved by lowering the heat treatment temperature. As a result, the increase in the trap site through the movement of the defects can be suppressed, thereby reducing the leakage current.

In addition, the present invention improves the uniformity of the etching rate by using a high selectivity ratio of GaN and AlGaN in performing an etching process for forming a high concentration n-type GaN layer under the source and drain electrodes. Precise etching control can be performed.

1 is a flowchart illustrating a method of manufacturing an N-polar nitride semiconductor device according to the present invention.
2 is a view illustrating a process of forming an N-polar nitride epitaxial layer, an etching control layer, and an n-type nitride layer in the method of manufacturing an N-polar nitride semiconductor device according to the present invention.
3 is a view for explaining a patterning process for forming an ohmic region in the method of manufacturing an N-polar nitride semiconductor device according to the present invention.
4 is a view illustrating a state in which an n-type nitride layer and an etching control layer for forming an ohmic region are partially removed in the method of manufacturing an N-polar nitride semiconductor device according to the present invention.
5 is a view showing a state in which a source electrode and a drain electrode are formed in an ohmic region in the method of manufacturing an N-polar nitride semiconductor element according to the present invention.
6 is a view showing a state in which an n-type nitride layer other than the ohmic region is removed in the method of manufacturing an N-polar nitride semiconductor element according to the present invention.
7 is a view for explaining the overall structure of the N-polar nitride semiconductor element according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, in the following description, only parts necessary for understanding the operation according to the embodiment of the present invention will be described, it should be noted that the description of other parts will be omitted so as not to distract from the gist of the present invention.

Also, the terms or words used in the specification and claims described below should not be construed as being limited to the ordinary or dictionary meanings, and the inventors should use the concept of terms to explain their own invention in the best way. On the basis of the principle that can be appropriately defined should be interpreted as meanings and concepts corresponding to the technical spirit of the present invention. Therefore, the embodiments described in the present specification and the configuration shown in the drawings are only one preferred embodiment of the present invention, and do not represent all of the technical idea of the present invention. It should be understood that there may be equivalents and variations.

1 is a flowchart illustrating a method of manufacturing an N-polar nitride semiconductor device according to the present invention. 2 to 7 are diagrams for explaining each process in the method of manufacturing a nitride semiconductor device according to the present invention. Hereinafter, a method of manufacturing a nitride semiconductor device according to the present invention will be described with reference to FIGS. 1 to 7.

First, referring to FIGS. 1 and 2, in the method of manufacturing the N-polar nitride semiconductor device according to the present invention, the substrate 10 is first prepared in step S110.

The substrate 10 may be formed of a material suitable for growing a nitride semiconductor single crystal. The substrate 10 includes sapphire (Al ₂ O ₃ ), silicon (Si), zinc oxide (ZnO), gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), aluminum nitride (AlN), magnesium oxide It may be made of an element or a compound such as (MgO). In the case of the sapphire, a sapphire substrate having a c plane ({0001} plane), an R plane ({1-102}), an M plane ({1-100}), and an A plane ({11-20}) may be used. have. In addition, in the case of a silicon substrate, a silicon substrate having a {111} plane or the like may be used.

Subsequently, an N-polar nitride based epitaxial layer is formed on the substrate 10 (S120). The epi layer may be formed by growing a nitride-based material in multiple layers. Specifically, in order to enable growth of a nitride-based material on the substrate 10, a transition layer 20 is formed, and an AlGaN buffer layer 30 is formed on the transition layer 20. Thereafter, a GaN layer 50 in which a two-dimensional electron cloud (2DEG) layer 40 is formed at an interface portion with the AlGaN buffer layer 30 is formed on the AlGaN buffer layer 30.

The transition layer 20 is a layer for allowing the growth of the nitride layer on the substrate 10, and may be made of different materials and structures according to the material of the substrate 10. The AlGaN buffer layer 30 may have a composition of Al _X Ga _1-X N (0.1 <x <1).

Subsequently, in the method of manufacturing the N-polar nitride semiconductor device according to the present invention, an etching control layer 60 is formed on the epitaxial layer (S130). The etch control layer 60 is a layer for preventing etching to the lower GaN layer 50 when etching the n-type nitride layer to be formed thereon for improving ohmic bonding characteristics. It may be made of, and may have a composition of Al _y Ga _1-y N (0 <y <0.5, y <x).

In the method of manufacturing an N-polar nitride semiconductor device according to the present invention, a high concentration n-type nitride layer 70 including an n-type dopant is formed on the etching control layer 60 (S140). ). The n-type nitride layer 70 may be formed of, for example, GaN doped with n-type.

In addition, in the method of manufacturing an N-polar nitride semiconductor device according to the present invention, in order to form source and drain electrodes, the n-type nitride layer 70 and the etching control layer 60 at the position where the ohmic region is to be formed are formed. Remove (S150).

FIG. 3 is a view illustrating a patterning process for forming an ohmic region in the method of manufacturing an N-polar nitride semiconductor device according to the present invention. In step S150, as shown in FIG. The photoresist pattern 80 is formed on the phosphorus n-type nitride layer 70 so that only the ohmic formation position is exposed. Then, through the etching process, the n-type nitride layer 70 and the etch control layer 60 under the region that are not protected by the photoresist pattern 80, that is, the ohmic formation position are removed. The reason for removing the etch control layer 60 is to solve the problem that the ohmic contact resistance is increased or the heat treatment temperature is increased by AlGaN of the etch control layer 60. In this case, a portion of the GaN layer 50 under the etch control layer 60 may be etched together. Thereafter, the photoresist pattern 80 is removed.

In the present embodiment, the removal of the n-type nitride layer 70 and the etching control layer 60 of the ohmic formation region is performed through a dry etching method using an inductively coupled plasma (ICP) etching apparatus. sccm, Cl2 32 sccm, ICP power 500W, RF power 50W, chamber pressure 10 mTorr can be made.

At this time, the etching selectivity between the n-type nitride layer 70 and the etching control layer 60, that is, GaN and AlGaN is the same level.

FIG. 4 is a view illustrating a state in which an n-type nitride layer and an etching control layer for forming an ohmic region are partially removed in the method of manufacturing an N-polar nitride semiconductor device according to the present invention. It can be seen that the GaN layer 50 is exposed by being formed.

Subsequently, in the method of manufacturing the N-polar nitride semiconductor device according to the present invention, as shown in FIG. 5, in the region where the n-type nitride layer 70 and the etching control layer 80 are removed, an ohmic metal By depositing the source electrode and the drain electrode 90 is formed (S160).

The source electrode and the drain electrode 90 are formed at a predetermined distance from each other, and are in direct contact with the GaN layer 50 in which the electron cloud (2DEG) layer 40 is generated. The source electrode and the drain electrode 90 may be formed by stacking ohmic metals in the order of Ti / Al / M / Au, and then removing metals other than the ohmic region through a lift-off process. have. Where M may be one of Ni, Ti, Pt, Mo, Ta.

In this embodiment, the source electrode and the drain electrode 90 were formed by stacking Ti / Al / Ni / Au in the order of 30/100/30/100 nm, respectively.

Subsequently, before forming the ohmic junction through heat treatment, the n-type nitride layer 70 existing outside the regions of the source electrode and the drain electrode 90 is removed (S170). In this case, a dry etching method is used to remove the n-type nitride layer 70, and a gas containing F is used as the gas for etching. Here, a gas containing F, there may be mentioned a SF6, CF4, CHF _3, C2F8. Dry etching using the F-containing gas serves to slow the etching of AlGaN in the etch control layer 60 under the n-type nitride layer 70 by generating the Al-F reactant. As a result, selective etching of the n-type nitride layer 70 is possible.

In the present embodiment, for example, dry etching was performed through ICP etching equipment, in particular, 25: 1 using ICP power 200W, RF power 30W, BCl3 20 sccm, SF6 5 sccm, chamber pressure 37.5 mTorr Only the n-type nitride layer 70 (n-type GaN) was selectively etched at an etching selectivity of.

As such, after removing the n-type nitride layer 70 other than the region of the source electrode and the drain electrode 90, an ohmic junction is formed on the source electrode and the drain electrode 90 through heat treatment (S180). According to this, the contact resistance is improved by the high concentration n-type GaN around the source electrode and the drain electrode 90, and the heat treatment temperature for forming the ohmic junction can be reduced. That is, in the method of manufacturing the nitride semiconductor device according to the present invention, the heat treatment for forming the ohmic junction of the source electrode and the drain electrode 70 is possible at a lower temperature than conventional. For example, in the present embodiment, ohmic was formed through rapid heat treatment in a 850 ° C. and 30 sec nitrogen atmosphere.

Thus, by forming the ohmic junction through the low temperature heat treatment temperature, it is possible to suppress the occurrence of defects due to the heat treatment and to obtain a leakage current reduction effect.

Finally, in the method of manufacturing the N-polar nitride semiconductor device according to the present invention, after the ohmic formation of the source electrode and the drain electrode 90 is completed, as shown in FIG. 7, the etching control layer 60 is formed. The gate electrode 100 is formed on the top (S190). The gate electrode 100 is positioned between the source electrode and the drain electrode 90. In this case, the gate electrode 100 may be formed of Ti, Pt, Cr, Pt / Au, Ni / Au, Ti / W, or platinum silicide, and may be formed of other metal materials. For example, the gate electrode 80 may be formed by stacking metals of 40 nm Ni and 200 nm Au in order.

7 is a view showing the overall structure of the N-polar nitride semiconductor device according to the present invention.

Referring to Figure 7, the structure of the N-polar nitride semiconductor device manufactured by the manufacturing method according to the present invention will be described.

In the nitride semiconductor device according to the present invention, an etching control comprising a substrate 10, an N-polar nitride epitaxial layer formed on the substrate 10, and an AlGaN formed on the nitride epitaxial layer. An n-type nitride layer 70 including a layer 60, an n-type dopant formed at an ohmic formation position on the etch control layer 60, an n-type nitride layer 70 at the ohmic formation position and a lower portion thereof A portion of the etch control layer 60 is partially removed, a source electrode and a drain electrode 90 formed in the removed region, and a gate electrode 100 formed in the gate region above the etch control layer 60. do.

The substrate 10 may be made of a material suitable for growing a nitride semiconductor single crystal. The substrate 10 includes sapphire (Al ₂ O ₃ ), silicon (Si), zinc oxide (ZnO), gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), aluminum nitride (AlN), magnesium oxide It may be made of an element or a compound such as (MgO).

The N-polar nitride-based epi layer is formed on the transition layer 20 formed on the substrate 10, the AlGaN buffer layer 30 formed on the transition layer 20, and on the AlGaN buffer layer 30. And a GaN layer 50 in which an electron cloud (2DEG) layer 40 is formed at an interface with the AlGaN buffer layer 30.

In the above, the transition layer 20 is a layer for allowing the growth of the nitride layer on the substrate 10, and may be made of different materials and structures according to the material of the substrate 10. The AlGaN buffer layer 30 may have a composition of Al _x Ga _1-x N (0.1 <x <1).

When the etch control layer 60 is etched on the n-type nitride layer 70 to be formed thereon to improve ohmic bonding properties, the etch control layer 60 prevents the etch control layer from being etched up to the GaN layer 50 of the lower epitaxial layer. For the layer, the GaN layer may be made of AlGaN capable of increasing the etching selectivity with respect to GaN, and may have a composition of Al _y Ga _1-y N (0 <y <0.5, y <x).

The n-type nitride layer 70 is a high-concentration GaN layer including an n-type dopant, and is formed in an ohmic formation position on the etch control layer 60 through the recess etching, that is, the source and drain electrodes 90. It is formed only at the bottom. The n-type nitride layer 70 may be formed of, for example, a GaN layer having a concentration of 3 × 10 ¹⁸ / cm 3.

The source and drain electrodes 90 partially remove the n-type nitride layer 70 at the ohmic formation position and the etch control layer 60 thereunder, and are formed in the removed region. In direct contact with the resulting GaN layer 50, an ohmic junction is formed through heat treatment.

The source and drain electrodes 90 may be formed by stacking two or more ohmic metals and then performing a heat treatment process. At this time, the ohmic metal may be formed by laminating in order of Ti / Al / M / Au. Where M may be one of Ni, Ti, Pt, Mo, Ta.

In this embodiment, Ti / Al / Ni / Au were laminated in order of thickness of 30/100/30/100 nm, respectively, and then ohmic was formed by rapid heat treatment at 800 ° C. and 30 sec nitrogen atmosphere.

According to this, the generation | occurrence | production of the defect by the high temperature heat processing of 900 degreeC or more can be suppressed, and the leakage current reduction effect can be acquired.

The gate electrode 100 is formed between the source and drain electrodes 90 on the etch control layer 60. It may be formed of Ti, Pt, Cr, Pt / Au, Ni / Au, Ti / W, or Platinum Silicide, and may be formed of other metal materials. In this embodiment, the gate electrode 100 was formed by stacking Ni / Au in a thickness of 40/200 nm in order.

The N-polar nitride-based semiconductor device having the above-described structure can form ohmic to the source electrode and the drain electrode 90 through a relatively low temperature heat treatment, and as a result, increases in defects and leakage currents due to high temperature heat treatment can be achieved. The ohmic characteristics can be improved by reducing the ohmic contact resistance.

As described above, the present invention has been described, but the embodiments of the present invention disclosed in the specification and drawings are only presented as specific examples for clarity and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

10: substrate
20: transition layer
30: AlGaN buffer layer
40: 2DEG layer
50: GaN layer
60: etching control layer
70: n-type nitride layer
90: source electrode and drain electrode
100: gate electrode

Claims (8)

Forming an N-polar nitride-based epi layer on the substrate, the GaN layer having a two-dimensional electron cloud layer formed thereon;
Forming an etch control layer on the N-polar nitride-based epi layer;
Forming an n-type nitride layer including an n-type dopant on the etch control layer;
Exposing a portion of the GaN layer by removing the n-type nitride layer and the etching control layer with respect to a predetermined ohmic region;
Forming a source electrode and a drain electrode in a region where the n-type nitride layer and the etch control layer are removed to contact the GaN layer;
Etching the remaining n-type nitride layer except the lower portion of the source electrode and the drain electrode;
Forming an ohmic junction on the source electrode and the drain electrode through a heat treatment; And
Forming a gate electrode on the etch control layer;
The n-type nitride layer is
A method of manufacturing an N-polar nitride-based semiconductor device, characterized in that it is a GaN layer doped with n-type. The method of claim 1, wherein the forming of the N-polar nitride-based epi layer
Forming a transition layer on the substrate;
Forming an AlGaN buffer layer on the transition layer; And
Forming a GaN layer on the AlGaN buffer layer in which a two-dimensional electron cloud (2DEG) layer is formed at an interface with the AlGaN buffer layer;
Method for producing an N-polar nitride-based semiconductor device comprising a. The method of claim 1, wherein exposing the GaN layer portion
And removing a portion of the n-type nitride layer, an etch control layer, and a GaN layer to expose a portion of the GaN layer with respect to a predetermined ohmic region. The method of claim 3, wherein the etch control layer is
A method of manufacturing an N-polar nitride-based semiconductor device, characterized in that it is formed of AlGaN. The method of claim 3, wherein the etching of the n-type nitride layer
A method for producing an N-polar nitride-based semiconductor device, characterized in that the n-type nitride layer is selectively etched by dry etching using an F-containing gas containing at least one of SF6, CF4, CHF ₃ and C2F8. Board;
An N-polar nitride-based epi layer formed on the substrate and forming a GaN layer thereon on which a two-dimensional electron cloud layer is formed;
An etch control layer formed on the N-polar nitride-based epi layer and made of AlGaN;
An n-type nitride layer including an n-type dopant formed at an ohmic formation position on the etch control layer;
A source electrode and a drain electrode formed to partially contact the exposed GaN layer by exposing a GaN layer by partially removing the n-type nitride layer and an etch control layer below the ohmic formation position; And
A gate electrode formed on the etch control layer;
The n-type nitride layer is
A nitride semiconductor device, characterized in that it is a GaN layer doped with an n-type. The method of claim 6, wherein the N-polar nitride-based epi layer is
A transition layer formed on the substrate;
An AlGaN buffer layer formed on the transition layer; And
A GaN layer formed on the AlGaN layer to generate a two-dimensional electron cloud (2DEG) layer at an interface with the AlGaN layer;
N-polar nitride-based semiconductor device comprising a. delete

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