CN105679679A - Preparation method of novel GaN-based grooved gate MISFET - Google Patents
Preparation method of novel GaN-based grooved gate MISFET Download PDFInfo
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- CN105679679A CN105679679A CN201610168348.0A CN201610168348A CN105679679A CN 105679679 A CN105679679 A CN 105679679A CN 201610168348 A CN201610168348 A CN 201610168348A CN 105679679 A CN105679679 A CN 105679679A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 43
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 14
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 8
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- 230000015572 biosynthetic process Effects 0.000 claims description 7
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- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 6
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
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- 238000001312 dry etching Methods 0.000 claims description 4
- 238000002156 mixing Methods 0.000 claims description 4
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 2
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- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims description 2
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- 229910052594 sapphire Inorganic materials 0.000 claims description 2
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- 238000005260 corrosion Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
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- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910017083 AlN Inorganic materials 0.000 description 1
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- 239000011259 mixed solution Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor preparation technology, and particularly relates to a preparation method of a GaN-based grooved gate MISFET. The preparation method comprises the following steps: firstly an AlGaN/GaN heterojunction material required for groove preparation, depositing a dielectric layer on the surface of the material as a mask layer, using a lithography developing technology and wet etching to remove the dielectric layer in a gate area to realize imaging of the mask layer, using the inverse process of GaN material growth response to remove AlGaN in the gate area and obtain a groove, carrying out in-place deposition on a high-quality AlN thin layer, then preparing and depositing a gate dielectric layer to overlay a source electrode, a drain electrode and a gate electrode, and finally forming the grooved gate MISFET of an AlN/gate dielectric layer stacked structure. The preparation method is simple in technology, the damage for the gate area when the groove is etched by using a traditional dry method or wet method can be well solved, a high-quality MIS interface can be formed so as to promote the device performance of the grooved gate MISFET, the gate leakage current and on resistance are reduced, and the stability of threshold voltage is improved.
Description
Technical field
The present invention relates to the technical field of semiconductor device, more particularly, to the preparation method of a kind of novel GaN base notched gates MISFET.
Background technology
Gallium nitride (GaN) material has that energy gap is big, breakdown field strength is high, electronics saturation drift velocity is big, thermal conductivity advantages of higher, is very suitable for making high-power, high frequency, high temperature power electronic devices. In applied power electronics field, in order to meet fail safe, field-effect transistor (FET) device must realize normally-off (also known as enhancement mode) work, and needs to be at least 4-5V at some occasion threshold voltage. And for conventional AlGaN/GaN HFET (HFET), existence due to interface high concentration, the two-dimensional electron gas (2DEG) of high mobility, even if when additional grid voltage is zero, device is also at opening (normally on device). In order to solve these problems, the isolated-gate field effect transistor (IGFET) (MISFET) adopting MIS structure is an effective technology path.
GaN base notched gates MISFET device, under the premise retaining access area 2DEG concentration (not sacrificing break-over of device characteristic), reduces the 2DEG below grid when removing zero-bias even completely, and MIS structure grid can be adopted to achieve high threshold voltage. But, traditional groove is prepared by adopting inductively coupled plasma (ICP) or reactive ion etching (RIE) equipment that the AlGaN potential barrier below grid is performed etching. Owing to the lattice of channel region can be caused damage by the use of plasma, and then affect the reliability and stability at MIS interface. Additionally, the selective etching ratio of AlGaN and GaN material is less, the therefore more difficult self-stopping technology realizing etching, process repeatability is poor. The lifting of these 2 channel mobilities limiting this mixed type MISFET, thus adding the conducting resistance of device.
Numeral wet etching utilizes repeatedly oxidation and chemical solution corrosion can obtain the normally-off notched gates MISFET device that technique is controlled, and can effectively remove plasma damage. But recess edge is not neat, area of grid has cone-shaped AlGaN residual, the surface of GaN channel layer also can observe substantial amounts of etching hole.Adopt selection area epitaxy technology to prepare groove and can also remove the plasma damage of area of grid, improve MIS interfacial characteristics, but epitaxy technique is more complicated. It is therefore desirable to seek a kind of selective area growth interface guard method, to overcome the shortcoming in traditional handicraft, thus obtaining higher mobility and threshold voltage. Owing to the extension of GaN base material is to realize under its synthesis rate quasi-balanced state slightly larger than decomposition rate, therefore, chemical gas-phase deposition system only has nitrogen, when the mixing gas of hydrogen or nitrogen and hydrogen is without growth source, the decomposition rate of GaN base material can be made slightly larger than synthesis rate by growth regulation parameter, thus the AlGaN epitaxial layer of area of grid successively being decomposed along the inverse process of growth response under the auxiliary of mask, it is thus achieved that groove.
Summary of the invention
The present invention overcomes at least one defect described in above-mentioned prior art, the preparation method that a kind of novel GaN base notched gates MISFET is provided, damage when can solve conventional dry or wet etching groove well, area of grid caused, can form high-quality MIS interface to promote the device performance of notched gates MISFET.
For solving above-mentioned technical problem, the technical solution used in the present invention is: the preparation method of a kind of novel GaN base notched gates MISFET, wherein, utilize the inverse process of GaN material growth response to be removed by area of grid AlGaN and obtain groove, and promote MIS interface quality by depositing Al N thin layer in place; Specifically comprise the steps of
S1, at Grown stress-buffer layer;
S2, on stress-buffer layer grow GaN epitaxial layer;
S3, in GaN epitaxial layer (3), grow AlGaN potential barrier;
S4, in AlGaN potential barrier deposit one layer of SiO2, as mask layer;
S5, method by photoetching and wet etching, remove the mask layer of area of grid;
S6, remove area of grid AlGaN potential barrier;
S7, growing AIN thin layer in place;
S8, deposition of gate insulating medium layer;
S9, dry etching complete device isolation, etch source electrode and drain ohmic contact region simultaneously;
S10, on source electrode and drain region are deposited with source electrode and drain ohmic contact metal;
S11, on groove dielectric layer area of grid evaporation gate metal.
Concrete, in described step S6, utilize the inverse process of GaN material growth response to be removed by area of grid AlGaN and obtain groove; In described step S7, depositing Al N thin layer in place promotes MIS interface quality.
Described substrate is any one in Si substrate, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrate.
Described stress-buffer layer is any one of AlN, AlGaN, GaN or combines; Stress buffer layer thickness is 10nm ~ 100 μm.
Described GaN epitaxial layer is the high resistant GaN epitaxial layer of the GaN epitaxial layer of involuntary doping or doping, and the doped chemical of described doping resistive formation is carbon or ferrum; GaN epitaxial layer thickness is 100nm ~ 100 μm.
Described epitaxial layer is AlGaN potential barrier, and AlGaN layer thickness is 5-50nm, and al composition varying concentrations.
Described AlGaN potential barrier material can also be a kind of or arbitrarily several combination in AlInN, InGaN, AlInGaN, AlN.
In described AlGaN potential barrier, and can also inserting AlN thin layer between GaN layer, thickness is 0-10nm.
Described epitaxial layer is high-quality AlN layer, and thickness is 0-10nm;Described insulating medium layer is Al2O3、HfO2、SiO2Or SiN etc., thickness is 1-100nm; Form AlN/ dielectric layer stacked structure.
Described source electrode and drain material are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; Grid material is Ni/Au alloy, Pt/Al alloy, Pd/Au alloy or TiN/Ti/Au alloy;
The growing method of the AlGaN epitaxial layer in the stress-buffer layer in described step S1, the GaN epitaxial layer in step S2, step S3 and the AlN in step S7 is Metalorganic Chemical Vapor Deposition, the contour quality film formation method of molecular beam epitaxy; In described step S4, the growing method of mask layer is plasma enhanced chemical vapor deposition method, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method; The recess etch method of described step S6 is to utilize the mixing gas of nitrogen, hydrogen or nitrogen and hydrogen to make AlGaN epitaxial layer successively decompose in metal organic chemical vapor deposition system.
Alternatively, it is also possible to utilize following method step to express the present invention.
Area of grid AlGaN is removed and obtains groove by the inverse process utilizing GaN material growth response, and promotes MIS interface quality by depositing Al N thin layer in place. Specifically comprise the steps of
1. provide and need the AlGaN/GaN heterojunction material carrying out groove grids etching;
2., at described deposited on materials one dielectric layer, form mask layer;
3. on described mask layer, utilize photoetching development technology, manifest area of grid;
4. use chemical solution to remove the mask material of area of grid, retain the mask material in other regions, it is achieved mask layer is graphical;
5. under the auxiliary of described mask pattern, it is achieved recess etch.
6. under the auxiliary of described mask pattern, at grooved area one layer of AlN thin layer of growth in place.
Further, in described step 1, described substrate is the epitaxial layer substrate with heterogeneity.
In described step 2, dielectric layer is to be formed by plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD) or magnetron sputtering. Described dielectric layer is SiO2Or SiN.
In described step 3, described photoresist is positivity or negative photoresist.
In described step 4, it is hydrofluoric acid aqueous solution or the mixed solution of Fluohydric acid. and ammonium fluoride that described dielectric layer removes the chemical solution used.
In described step 5, described recess etch is Metalorganic Chemical Vapor Deposition or molecular beam epitaxy. Reacting gas is H2、N2, or H2With N2Mixing gas.
In described step 6, the in place of described AlN thin layer is grown to Metalorganic Chemical Vapor Deposition or molecular beam epitaxy.
Compared with prior art, provide the benefit that: the preparation method that the present invention provides a kind of novel GaN base notched gates MISFET, groove is obtained, it is possible to damage when solving conventional dry or wet etching groove well, area of grid caused owing to utilizing the inverse process of GaN material growth response to be removed by area of grid AlGaN. The method need not use chemical solvent, it is possible to avoids corrosion hole and the wet etching residue in notched gates region. Additionally, the device performance of MIS interface quality and notched gates MISFET can be improved further by formation high-quality AlN thin layer in place.
Accompanying drawing explanation
Fig. 1-11 is the device manufacture method process schematic representation of the embodiment of the present invention 1.
Figure 12 is the device architecture schematic diagram of the embodiment of the present invention 2.
Figure 13 is the device architecture schematic diagram of the embodiment of the present invention 3.
Figure 14 is the device architecture schematic diagram of the embodiment of the present invention 4.
Figure 15 is the device architecture schematic diagram of the embodiment of the present invention 5.
Detailed description of the invention
Accompanying drawing being merely cited for property explanation, it is impossible to be interpreted as the restriction to this patent; In order to the present embodiment is better described, some parts of accompanying drawing have omission, zoom in or out, and do not represent the size of actual product; To those skilled in the art, in accompanying drawing, some known features and explanation thereof are likely to omission and will be understood by. Being merely cited for property of position relationship explanation described in accompanying drawing, it is impossible to be interpreted as the restriction to this patent.
Embodiment 1
It is the device architecture schematic diagram of the present embodiment as shown in figure 11, its structure includes substrate (1) from lower to upper successively, stress-buffer layer (2), GaN epitaxial layer (3), AlGaN potential barrier (4), reactive ion etching forms groove, growing AIN thin layer (5) in place, gate insulator dielectric layer (6), two ends form source electrode (7) and drain electrode (8), the upper deposition of gate (9) of the insulating barrier (6) at recess channel place.
The manufacture method of the device field-effect transistor of above-mentioned GaN base notched gates MISFET as Figure 1-Figure 11, comprises the following steps:
S1, utilize mocvd method, at Si substrate (1) upper growth one ply stress cushion (2), as shown in Figure 1;
S2, utilize mocvd method, stress-buffer layer (2) grows GaN epitaxial layer (3), as shown in Figure 2;
S3, utilize mocvd method, GaN epitaxial layer (3) grows AlGaN potential barrier (4), as shown in Figure 3;
S4, by one layer of SiO of plasma enhanced chemical vapor deposition2, as mask layer (10), as shown in Figure 4;
S5, select region etch by photoetching method, remove the mask layer (10) of area of grid, as shown in Figure 5;
S6, utilize mocvd method, form groove grids by the inverse process of GaN material growth response, as shown in Figure 6;
S7, utilize mocvd method, the high-quality AlN thin layer (5) of growth in place a layer, as shown in Figure 7;
S8, removal mask layer (10), utilize Atomic layer deposition method, forms AlN/Al2O3Dielectric layer (6) stacked structure, as shown in Figure 8;
S9, utilize ICP to complete device isolation, etch source electrode and drain ohmic contact region, as shown in Figure 9 simultaneously;
S10, on source electrode and drain region are deposited with, Ti/Al/Ni/Au alloy is as the metal ohmic contact of source electrode (7) and drain (8), as shown in Figure 10;
S11, on the insulating barrier in groove grids region be deposited with Ni/Au alloy as grid (9) metal, as shown in figure 11.
So far, the preparation process of whole device is completed. Figure 11 is the device architecture schematic diagram of embodiment 1.
Embodiment 2
Being the device architecture schematic diagram of the present embodiment as shown in figure 12, itself and embodiment 1 structure differ only in: embodiment 2 further groove grid is to be obtained by epitaxial growth back reaction etching, but does not have the high-quality AlN thin layer of growth in place.
Embodiment 3
Being the device architecture schematic diagram of the present embodiment as shown in figure 13, itself and embodiment 1 structure differ only in: in embodiment 1, whole area of grid AlGaN potential barrier is etched and removes and form groove. Conducting channel produces between AlN/ dielectric layer and GaN epitaxial layer. And in this embodiment, certain thickness AlGaN potential barrier can be retained by controlling etch period, owing to raceway groove has higher two-dimensional electron gas at heterojunction boundary, channel mobility and output electric current can be improved.
Embodiment 4
Being the device architecture schematic diagram of the present embodiment as shown in figure 14, it differs only in embodiment 1 and example 3 structure: in this embodiment, can pass through to control etch period and whole AlGaN potential barrier be removed and over etching certain thickness in GaN epitaxial layer. Conducting channel produces between AlN/ dielectric layer and GaN epitaxial layer.
Embodiment 5
Being the device architecture schematic diagram of the present embodiment as shown in figure 15, itself and embodiment 1 are distinctive in that: embodiment 1 is horizontal conducting type MISFET, and embodiment 4 is longitudinal conducting type device. Specifically, the GaN epitaxial layer of embodiment 4 is n-type doped epitaxial layer, and backing material is low-resistance silicon, GaN heavy doping self-supported substrate etc.
Embodiment 6
The present embodiment and embodiment 1 structure differ only in: after the present embodiment obtains groove grids by epitaxial growth back reaction etching, growth high-quality SiN thin layer in place, thickness is 0-10nm.
Furthermore, it is necessary to illustrate, the accompanying drawing of above example, merely to the purpose of signal, so there is no be necessarily drawn to scale.
Obviously, the above embodiment of the present invention is only for clearly demonstrating example of the present invention, and is not the restriction to embodiments of the present invention. For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description. Here without also cannot all of embodiment be given exhaustive. All any amendment, equivalent replacement and improvement etc. made within the spirit and principles in the present invention, should be included within the protection domain of the claims in the present invention.
Claims (10)
1. the preparation method of a novel GaN base notched gates MISFET, it is characterised in that utilize the inverse process of GaN material growth response to be removed by area of grid AlGaN and obtain groove, and promote MIS interface quality by depositing Al N thin layer in place; Specifically comprise the steps of
S1, at the upper growth stress cushion (2) of substrate (1);
S2, growth GaN epitaxial layer (3) on stress-buffer layer;
S3, in GaN epitaxial layer (3), grow AlGaN potential barrier (4);
S4, in AlGaN potential barrier deposit one layer of SiO2, as mask layer (10);
S5, method by photoetching and wet etching, remove the mask layer (10) of area of grid;
S6, remove area of grid AlGaN potential barrier (4);
S7, growing AIN thin layer in place (5);
S8, deposition of gate insulating medium layer (6);
S9, dry etching complete device isolation, etch source electrode and drain ohmic contact region simultaneously;
S10, on source electrode and drain region are deposited with source electrode (7) and (8) metal ohmic contact that drains;
S11, on groove dielectric layer area of grid evaporation grid (9) metal.
2. the preparation method of a kind of novel GaN base notched gates MISFET according to claim 1, it is characterised in that: in described step S6, utilize the inverse process of GaN material growth response to be removed by area of grid AlGaN and obtain groove; In described step S7, depositing Al N thin layer in place promotes MIS interface quality.
3. the preparation method of a kind of novel GaN base notched gates MISFET according to claim 1, it is characterised in that: described substrate (1) is Si substrate, any one in Sapphire Substrate, silicon carbide substrates, GaN self-supported substrate.
4. the preparation method of a kind of novel GaN base notched gates MISFET according to claim 1, it is characterised in that: described stress-buffer layer (2) is AlN, AlGaN, GaN any one or combination;Stress buffer layer thickness is 10nm ~ 100 μm.
5. the preparation method of a kind of novel GaN base notched gates MISFET according to claim 1, it is characterized in that: GaN epitaxial layer that described GaN epitaxial layer (3) is involuntary doping or the high resistant GaN epitaxial layer of doping, the doped chemical of described doping resistive formation is carbon or ferrum; GaN epitaxial layer thickness is 100nm ~ 100 μm.
6. the preparation method of a kind of novel GaN base notched gates MISFET according to claim 1, it is characterised in that: described epitaxial layer is AlGaN potential barrier (4), and AlGaN layer thickness is 5-50nm, and al composition varying concentrations.
7. the preparation method of a kind of novel GaN base notched gates MISFET according to claim 1, it is characterised in that: described AlGaN potential barrier material can also be a kind of or arbitrarily several combination in AlInN, InGaN, AlInGaN, AlN.
8. the preparation method of a kind of novel GaN base notched gates MISFET according to claim 1, it is characterised in that: in described AlGaN potential barrier (4), and can also inserting AlN thin layer between GaN layer, thickness is 0-10nm.
9. the preparation method of a kind of novel GaN base notched gates MISFET according to claim 1, it is characterised in that: described epitaxial layer (5) is high-quality AlN layer, and thickness is 0-10nm; Described insulating medium layer (6) is Al2O3、HfO2、SiO2Or SiN etc., thickness is 1-100nm; Form AlN/ dielectric layer stacked structure.
10. the preparation method of a kind of novel GaN base notched gates MISFET according to claim 1, it is characterised in that: described source electrode (7) and drain electrode (8) material are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; Grid (9) material is Ni/Au alloy, Pt/Al alloy, Pd/Au alloy or TiN/Ti/Au alloy;
AlGaN epitaxial layer (4) in stress-buffer layer (2) in described step S1, the GaN epitaxial layer (3) in step S2, step S3 and the AlN(5 in step S7) growing method be Metalorganic Chemical Vapor Deposition, the contour quality film formation method of molecular beam epitaxy; In described step S4, the growing method of mask layer (10) is plasma enhanced chemical vapor deposition method, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method; The recess etch method of described step S6 is to utilize the mixing gas of nitrogen, hydrogen or nitrogen and hydrogen to make AlGaN epitaxial layer successively decompose in metal organic chemical vapor deposition system.
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