CN207966998U - A kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage - Google Patents
A kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage Download PDFInfo
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- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000407 epitaxy Methods 0.000 claims abstract description 16
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 34
- 229910001020 Au alloy Inorganic materials 0.000 description 11
- 230000012010 growth Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 229910000990 Ni alloy Inorganic materials 0.000 description 6
- 229910001069 Ti alloy Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000005036 potential barrier Methods 0.000 description 5
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- 229910001128 Sn alloy Inorganic materials 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910001252 Pd alloy Inorganic materials 0.000 description 2
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
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- 239000003518 caustics Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
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- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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Abstract
The utility model is related to the technical fields of semiconductor, more particularly, to a kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage.A kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage, wherein, include successively from lower to upper substrate, stress-buffer layer, GaN epitaxial layer, AlN epitaxial layers, AlGaN epitaxial layers, secondary epitaxy layer, secondary epitaxy forms groove, gate dielectric layer, both ends form source electrode and drain electrode, grid are covered on the insulating layer at recess channel.The conduction property that the utility model can effectively improve threshold voltage, grid region mobility, reduce channel resistance, improve GaN MOSFET elements.
Description
Technical field
The utility model is related to the technical fields of semiconductor, more particularly, to a kind of high conduction property of high threshold voltage
Normally-off GaN base MOSFET structure.
Background technology
Representative of the GaN material as third generation semiconductor material with wide forbidden band, the big, breakdown field strength with energy gap
High, saturated electron drift velocity is big and the superior performances such as thermal conductivity is high.GaN base device for power switching usually utilizes AlGaN/
The two-dimensional electron gas work of high concentration, high mobility at GaN heterostructure interfaces, so that device is had, conducting resistance is small, switch is fast
Fast advantage is spent, is very suitable for making high-power, high frequency, high temperature power electronic devices.
In applied power electronics field, in order to ensure that the fail safe of circuit system, FET device must realize normally-off work
Make.And for conventional AlGaN/GaN HFET, due to AlGaN/GaN heterojunction boundaries high concentration, the 2DEG of high mobility
In the presence of, even if in the case where it is zero to add grid voltage outside, device is also at open state, therefore, conventional AlGaN/GaN
HFET belongs to normally on device.How to realize that normally-off HFET is always most study in GaN base power electronic devices field
One difficult point.
Realize that one of the method for normally-off device is notched gates method at present.This method is by being thinned or completely removing grid region
AlGaN layer reduces grid region two-dimensional electron gas, while retaining the two-dimensional electron gas of access area, realizing normally-off device.
The threshold voltage of device can be increased by completely removing grid region AlGaN layer, but also bring that grid region mobility is low, conducting resistance simultaneously
Greatly, the problems such as interface state density is high.Grid region AlGaN layer, which is thinned, can alleviate this problem, however depositing due to thin layer AlGaN
There are certain density two-dimensional electron gas in grid region so that device threshold voltage is smaller.In addition, traditional thin potential barrier layer device
Grid region AlGaN layer is removed using the methods of etching, this method can not achieve the controllable precise of thin barrier layer thickness, and can not keep away
Lattice damage can be introduced in grid region with exempting from.In order to solve this problem, we prepare groove using the method for selective area growth
The device of grid structure is, it can be achieved that the features such as grid region is not damaged, thin barrier layer controllable precise.In general, notched gates method is carried out
Optimization realizes that the high threshold voltage good normally-off switching device that simultaneously turns on performance is one that GaN power electronic devices faces
Significant challenge.
Invention content
The utility model is at least one defect overcome described in the above-mentioned prior art, provides a kind of high threshold voltage height and leads
The normally-off GaN base MOSFET structure of general character energy, can guarantee the conduction property of device while threshold voltage can be improved.
The utility model on the AlGaN/AlN/GaN substrates of an extension high quality, then constituency secondary epitaxy formed it is recessed
Slot gate structure, prepares trench gate type MOSFET device.The Al of an extension top layer AlGaN layer and secondary epitaxy AlGaN potential barrier
Component and thickness can be accurately controlled by growth parameter(s).The utility model can realize low Al components, it is thicker degree speciality it is primary
The barrier layer of extension AlGaN layer and secondary epitaxy high Al contents.It is in particular in the recessed grating structure device to be formed, grid
Area retains a undamaged floor, low Al components, the AlGaN layer of larger thickness, and access area is the heterogeneous of high Al contents barrier layer
Structure.Compared to complete throating grid structure MOSFET element and traditional thin potential barrier device, the device of the utility model structure can have
Effect reduces grid region two-dimensional electron gas, inhibits interface scattering, to increase device threshold voltage, improve grid region carrier mobility
Rate(Reduce opening resistor), and improve grid region interfacial characteristics, improve device stability.
The technical solution of the utility model is:A kind of normally-off GaN base MOSFET knots of the high conduction property of high threshold voltage
Structure, wherein include from lower to upper substrate successively, stress-buffer layer, GaN epitaxial layer, AlN epitaxial layers, AlGaN epitaxial layers are secondary
Epitaxial layer, secondary epitaxy form groove, gate dielectric layer, and both ends form source electrode and drain electrode, covered on the insulating layer at recess channel
There is grid.
Further, the groove is U-shaped or trapezoidal-structure.
The substrate is any one of Si substrates, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrates.
The stress-buffer layer is any of AlN, AlGaN, GaN or combination;Stress buffer layer thickness be 100 nm ~
20 μm。
The one secondary growth GaN epitaxial layer be unintentional doping GaN epitaxial layer or doping high resistant GaN epitaxial layer,
The doped chemical of the doping resistive formation is carbon or iron;GaN epitaxial layer thickness is 100 nm ~ 20 μm.
The epitaxial layer is the AlN layers of high quality;AlN layer thickness is 0-5 nm.
The epitaxial layer is the AlGaN layer of high quality;AlGaN layer thickness is 1-10 nm, and aluminium concentration of component is alterable;
The secondary epitaxy layer is AlGaN/GaN heterojunction structures, and AlGaN layer thickness is 5-50 nm, and aluminium concentration of component
Alterable, GaN layer thickness is 0-500 nm.
The AlGaN potential barrier material can also be one kind or arbitrary several in AlInN, InGaN, AlInGaN, AlN
The combination of kind;
An AlN thin layers, thickness 1- can also be inserted into the secondary epitaxy layer, between AlGaN potential barrier and GaN layer
10 nm;
The gate dielectric layer is Al2O3、Si3N4、MgO、SiO2、HfO2Equal insulating medium layers, thickness are 1-100 nm;
Source electrode and drain electrode material is Ti/Al/Ni/Au alloys, Ti/Al/Ti/Au alloys, Ti/Al/Mo/Au alloys or Ti/
Al/Ti/TiN alloys;Grid material is Ni/Au alloys, Pt/Al alloys, Pd/Au alloys or TiN/Ti/Al/Ti/TiN alloys.
The source electrode and drain electrode material includes but not limited to Ti/Al/Ni/Au alloys, Ti/Al/Ti/Au alloys, Ti/Al/Mo/Au conjunctions
Gold or Ti/Al/Ti/TiN alloys, other can realize that the various metal or alloy of Ohmic contact can be used as source electrode and drain electrode material
Material;Grid material includes but not limited to Ni/Au alloys, Pt/Al alloys, Pd/Au alloys or TiN/Ti/Al/Ti/TiN alloys,
He can realize that the various metal or alloy of high threshold voltage can be used as grid material.
The preparation method of the normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage, wherein including following step
Suddenly:
S1, on a si substrate growth stress buffer layer;
S2, GaN epitaxial layer is grown on stress-buffer layer;
S3, the growing AIN epitaxial layer in GaN epitaxial layer;
S4, AlGaN epitaxial layers are grown on AlN epitaxial layers;
S5, one layer of SiO is deposited on AlGaN epitaxial layers2, as mask layer;
S6, the method by corroding or etching retain the mask layer formed on area of grid;
S7, the method by etching retain the AlN layer AlGaN layers formed on area of grid;
S8, selective area growth secondary epitaxy layer form fluted body area of grid;
Mask layer on S9, removal area of grid;
S10, dry etching complete device isolation;
S11, deposition gate dielectric layer, while etching source electrode and drain electrode ohmic contact regions;
S12, upper source electrode and drain electrode metal ohmic contact is deposited in source electrode and drain electrode region;
S13, gate metal is deposited in area of grid on groove dielectric layer.
Stress-buffer layer in the step S1 and the GaN epitaxial layer in step S2 and the secondary epitaxy layer in step S8
Growing method is the high quality film formation methods such as Metalorganic Chemical Vapor Deposition, molecular beam epitaxy;In the step S3
The growing method of epitaxial layer AlN thin layers and step S4 epitaxial layers AlGaN thin layers is Metalorganic Chemical Vapor Deposition, molecule
The high quality film formation method such as beam epitaxy methods;The growing method of mask layer is heavy for plasma enhanced chemical vapor in the step S5
Area method, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method;The growing method of the step S11 is that metal is organic
The film build methods such as chemical vapour deposition technique, molecular beam epitaxy and atomic layer deposition method, magnetron sputtering method.
Compared with prior art, advantageous effect is:The utility model improves the performance of device, especially to conducting resistance
Reduction and the raising of threshold voltage be very significant.The utility model device technology repeatability and reliability are high, reduce
The Al components and thickness of grid region AlGaN so that threshold voltage effectively improves.Diauxic growth high Al contents and suitable depth
AlGaN layer improves the on state characteristic of device.The utility model provide one kind can realize high threshold voltage, low on-resistance,
Normally-off GaN MOSFET elements of High Output Current density and preparation method thereof.
Description of the drawings
Fig. 1-12 is the device manufacture method process schematic representation of the utility model embodiment 1.
Figure 13 is the device architecture schematic diagram of the utility model embodiment 2.
Specific implementation mode
The attached figures are only used for illustrative purposes and cannot be understood as limitating the patent;It is attached in order to more preferably illustrate the present embodiment
Scheme certain components to have omission, zoom in or out, does not represent the size of actual product;To those skilled in the art,
The omitting of some known structures and their instructions in the attached drawings are understandable.Being given for example only property of position relationship described in attached drawing
Illustrate, should not be understood as the limitation to this patent.
Embodiment 1
It is the device architecture schematic diagram of the present embodiment as shown in figure 11, structure includes substrate 1, stress successively from lower to upper
Buffer layer 2, GaN epitaxial layer 3, AlN epitaxial layers 4, AlGaN epitaxial layers 5, secondary epitaxy layer 6, secondary epitaxy form groove, and grid are situated between
Matter layer 7, both ends form source electrode 8 and drain electrode 9, grid 10 are covered on the dielectric layer 7 at recess channel.
The normally-off GaN base MOSFET preparation methods of the above-mentioned high conduction property of high threshold voltage are as shown in Figure 1-Figure 11, packet
Include following steps:
S1, using mocvd method, a ply stress buffer layer 2 is grown on Si substrates 1, such as Fig. 1
It is shown;
S2, mocvd method, the growth GaN epitaxial layer 3 on stress-buffer layer 2, such as Fig. 2 institutes are utilized
Show;
S3, using mocvd method, one layer of 4 He of AlN epitaxial layers is grown in GaN epitaxial layer 3
AlGaN epitaxial layers 5, as shown in Figure 3;
S4, one layer of SiO is deposited by Atomic layer deposition method2, as mask layer 11, as shown in Figure 4;
S5, it is etched by photolithography method selection region, retains the mask layer 11 on area of grid, as shown in Figure 5;
S6, it is etched by photolithography method selection region, retains the AlN layers 4 and AlGaN layer 5 on area of grid, such as Fig. 6
It is shown;
S7, using mocvd method, selective area growth is secondary on the substrate for having mask layer 11
Extension GaN/AlGaN layers 6 form groove grids, as shown in Figure 7;
S8, using caustic solution, remove the mask layer 11 on area of grid, as shown in Figure 8;
S9, device isolation is completed using ICP, as shown in Figure 9;
S10, using Atomic layer deposition method, grow the gate dielectric layer 7 of one layer of insulation, while etching source electrode and drain electrode Europe
Nurse contact area, as shown in Figure 10;
S11, upper Ti/Al/Ni/Au alloys are deposited as source electrode 8 and the Ohmic contact of drain electrode 9 gold in source electrode and drain electrode region
Belong to, as shown in figure 11;
S12, Ni/Au alloys are deposited on the insulating layer in groove grids region as 10 metal of grid, as shown in figure 12.
So far, that is, the preparation process of entire device is completed.Figure 12 is the device architecture schematic diagram of embodiment 1.
Embodiment 2
It is the device architecture schematic diagram of the present embodiment as shown in figure 13, is differed only in 1 structure of embodiment:Embodiment
It is etched by photolithography method selection region in 1, retains the AlN layers 4 and AlGaN layer 5 on area of grid, and in embodiment 2 not
AlN layers 4 and AlGaN layer 5 are performed etching, AlN layers 4 and AlGaN layer 5 are retained.On this substrate, selective area growth is secondary outer
Prolong AlGaN layer 6, forms groove grids.
Obviously, above-described embodiment of the utility model is only intended to clearly illustrate the utility model example, and
It is not the restriction to the embodiment of the utility model.For those of ordinary skill in the art, in above description
On the basis of can also make other variations or changes in different ways.There is no need and unable to give all embodiments
It is exhaustive.All any modification, equivalent and improvement made within the spirit and principle of the present invention etc., should be included in
Within the protection domain of the utility model claims.
Claims (7)
1. a kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage, which is characterized in that from lower to upper successively
Including substrate(1), stress-buffer layer(2), GaN epitaxial layer(3), AlN epitaxial layers(4), AlGaN epitaxial layers(5), secondary epitaxy layer
(6), secondary epitaxy formation groove, gate dielectric layer(7), both ends form source electrode(8)And drain electrode(9), the insulating layer at recess channel
On be covered with grid(10).
2. a kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage according to claim 1, special
Sign is:The groove is U-shaped or trapezoidal-structure.
3. a kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage according to claim 1, special
Sign is:The substrate(1)For any one of Si substrates, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrates.
4. a kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage according to claim 1, special
Sign is:The stress-buffer layer(2)Thickness is 100 nm ~ 20 μm.
5. a kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage according to claim 1, special
Sign is:The GaN epitaxial layer(3)It is unintentional for the GaN epitaxial layer of unintentional doping or the high resistant GaN epitaxial layer of doping
The GaN epitaxial layer of doping or the doped chemical of the high resistant GaN epitaxial layer of doping are carbon or iron;GaN epitaxial layer thickness is 100
nm~20μm。
6. a kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage according to claim 1, special
Sign is:The AlN epitaxial layers(4)Thickness be 0-5 nm.
7. a kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage according to claim 1, special
Sign is:The AlGaN epitaxial layers(5)Thickness be 1-10 nm;The secondary epitaxy layer(6)It is heterogeneous for AlGaN/GaN
Structure, AlGaN layer thickness are 5-50 nm, and GaN layer thickness is 0-500 nm.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107768252A (en) * | 2017-11-03 | 2018-03-06 | 中山大学 | A kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage and preparation method thereof |
CN116130513A (en) * | 2023-04-17 | 2023-05-16 | 南京第三代半导体技术创新中心有限公司 | Silicon carbide trench gate MOSFET based on heterojunction and manufacturing method thereof |
-
2017
- 2017-11-03 CN CN201721450554.7U patent/CN207966998U/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107768252A (en) * | 2017-11-03 | 2018-03-06 | 中山大学 | A kind of normally-off GaN base MOSFET structure of the high conduction property of high threshold voltage and preparation method thereof |
CN116130513A (en) * | 2023-04-17 | 2023-05-16 | 南京第三代半导体技术创新中心有限公司 | Silicon carbide trench gate MOSFET based on heterojunction and manufacturing method thereof |
CN116130513B (en) * | 2023-04-17 | 2023-06-13 | 南京第三代半导体技术创新中心有限公司 | Silicon carbide trench gate MOSFET based on heterojunction and manufacturing method thereof |
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Effective date of registration: 20211116 Address after: Room 507-2, building 3, 111 Xiangke Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai 201210 Patentee after: Shanghai xinyuanji Semiconductor Technology Co., Ltd Address before: 510275 No. 135 West Xingang Road, Guangdong, Guangzhou Patentee before: Sun Yat-sen University |