CN107706241A - A kind of normally-off GaNMOSFET structures at high quality MOS interfaces and preparation method thereof - Google Patents
A kind of normally-off GaNMOSFET structures at high quality MOS interfaces and preparation method thereof Download PDFInfo
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- CN107706241A CN107706241A CN201711049287.7A CN201711049287A CN107706241A CN 107706241 A CN107706241 A CN 107706241A CN 201711049287 A CN201711049287 A CN 201711049287A CN 107706241 A CN107706241 A CN 107706241A
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The present invention relates to the technical field of semiconductor devices, more particularly, to the normally-off GaN MOSFET structures at a kind of high quality MOS interfaces and preparation method thereof.During the present invention utilizes secondary epitaxy high growth temperature, one layer of fine and close dielectric layer that mask layer is formed with GaN interfaces, GaN material surface dangling bonds have effectively been passivated, the further formation of Ga O keys is reduced during subsequent technique, so as to improve the performance of device.The epitaxial layer includes the GaN epitaxial layer substrate of an epitaxial growth and undoped GaN epitaxial layer, the potential barrier of heterogenous junction layer of the growth of selection region secondary epitaxy.The self-assembling formation when notched gates grow access area material by secondary epitaxy.Gate insulator dielectric layer is covered on recess channel, the side wall of secondary epitaxy layer and surface, forms source, drain region by the both ends of etching insulating layer, then form Ohm contact electrode by metal evaporation.The Groove gate MOS devices that the present invention is prepared for having high quality interface using selection region epitaxy technology, it will be apparent that improve the threshold voltage stability of device.
Description
Technical field
The present invention relates to the technical field of semiconductor devices, more particularly, to a kind of normally-off at high quality MOS interfaces
GaN MOSFET structures and preparation method thereof.
Background technology
As third generation semi-conducting material, GaN not only possesses wider forbidden band, higher thermal conductivity and higher critical hit
The advantages that wearing field strength, and the two-dimensional electron gas formed at its heterogeneous interface has higher concentration and larger saturated electrons
Migration velocity.Compared with Si materials, the material of the type has in terms of the power electronic devices of high power, high switching speed is made
There is bigger advantage, have a extensive future.
Because the spontaneous polarization effect in AlGaN/GaN hetero-junctions and piezoelectric polarization effect generate the 2DEG of high concentration,
So that the device of the type has the characteristics that conducting resistance is low, current density is high, belong to normally on device.Realize the type device
The normal pass of part is, it is necessary to additionally apply minus gate voltage.But have more in power electronics and radio frequency amplification sector, normally-off device
It is widely applied.The circuit formed with normally-off device can be powered using single supply, and this feature simplifies circuit, be increased
The reliability of circuit is added.
At present, realize that the method that GaN base device often closes mainly there are two classes.One is cascade method（cascode）, but the party
The high temperature tolerance characteristic of method receives the restriction of Si devices, and device is more complicated, and process costs are larger；Another kind of is to pass through device
Technique or epitaxial growth regulation and control hetero-junctions in 2DEG, so as to realize the normal pass of device, wherein wrap thin AlGaN potential barrier method,
Recess etch method etc..But thinned AlGaN potential barrier significantly increases the resistance of access area, grid of the recess etch method in device
The introduced damage in pole surface and access area, these all can have obvious deterioration to the stability and reliability of device.In GaN
In base MOS device, surface defect state, GaN interfaces near raceway groove with inside the interfacial state at gate dielectric layer and dielectric layer
Defect state, be likely to produce substantial amounts of trap, these traps can produce Leakage Current passage, cause device zero gate bias it
Under can not complete switch off.When these trap states are occupied by an electron, Coulomb scattering caused by charged trap can cause grid groove
Electron mobility reduction, so as to deteriorate the conduction property of device.When applying different switch biass to grid, electrons
Discharged or captured by trap states, cause the drift of threshold voltage.Therefore, the mos gate interface for preparing high quality is that solution device can
By the important thinking of sex chromosome mosaicism.
In order to improve the gate interface quality of slot grid structure GaN device, Many researchers application selection region extension（He
Z, Li J, Wen Y, et al. Comparison of Two Types of Recessed-Gate Normally-Off
AlGaN/GaN Heterostructure Field Effect Transistors[J]. Japanese Journal of
Applied Physics, 2012, 51(5):4103.）.Our previous work is found, with being done under the same terms using conventional
GaN MOSFET are compared on sapphire prepared by method etching, and very great Cheng occurs in the interfacial state of selection region extension Grooved-gate MOSFET’s
The reduction of degree, the performance of device greatly improve.
The content of the invention
The present invention is overcomes at least one defect described in above-mentioned prior art, there is provided a kind of high quality MOS interfaces it is normal
Pass type GaN MOSFET structures and preparation method thereof, this method technique is simple, stability is high.Using this method so that the boundary of device
After the Quality advance of face, the flat-band voltage of its C-V curve, which returns stagnant window, significantly to be reduced.
The technical scheme is that：The present invention prepares above-mentioned device using selection region epitaxy, and selective growth connects
Enter energy self-assembling formation groove structure and area of grid is in graphical SiO2Etching technics can be effectively prevented under the protection of mask
The damage at GaN interfaces below groove grid.In addition, utilize the high temperature in secondary epitaxy growth course（In the present embodiment, growth is non-to mix
Miscellaneous GaN layer temperature is 1075 DEG C, and potential barrier of heterogenous junction layer temperature is 1095 DEG C）Mask layer and GaN interface can be made to form one
Layer compact medium layer, has effectively been passivated GaN material surface dangling bonds, and reduce entering for Ga-O keys during subsequent technique
One step is formed.This will reduce the scattered power at interface, improve 2DEG mobility.
A kind of normally-off GaN MOSFET structures at high quality MOS interfaces, wherein, it is included in the epitaxial growth of substrate last time
One layer of GaN epitaxial layer substrate, one layer of mask material is deposited on GaN epitaxial layer substrate and forms patterned mask, utilizes two
The undoped GaN epitaxial layer of secondary epitaxial growth, potential barrier of heterogenous junction layer, remove pattern mask and self-assembling formation groove, deposit one layer
Gate insulation dielectric layer, the dielectric layer are covered on recess channel, the side wall of secondary epitaxy layer and surface, pass through metal evaporation shape
Into source electrode and drain electrode and grid.
Further, the material of described substrate can be SiC, sapphire or Si, but not limited to this scope.
Described GaN epitaxial layer substrate includes stress-buffer layer, GaN layer, and stress-buffer layer can be AlN, AlGaN, GaN
Any or combination, its thickness between 100 nm to 10 μm, GaN layer can be C or Fe adulterate the resistive formation to be formed or
The epitaxial layer of unintentional doping, its thickness is between 100 nm to 10 μm.
Described mask material can use SiO2, SiNx, Al2O3、AlN、HfO2、MgO、Sc2O3, its thickness is between 1nm
To 100nm.
Between 10 nm between 500nm, described potential barrier of heterogenous junction layer can be described undoped GaN layer thickness
The combination of any one or more material in AlGaN, AlInN, AlInGaN, AlN, InGaN, but not limited to this scope, its thickness
It is thick to one layer of 1nm to 10nm between 50nm, is also grown between undoped GaN epitaxial layer and potential barrier of heterogenous junction layer between 5nm
AlN layers.
The material of described gate insulator dielectric layer can be SiO2, Al2O3, Sc2O3, SiNx, AlN, HfO2, MgO,
Any one material in Ga2O3, HfSiON, AlHfOx, or the stacked combination of many of material, thickness is between 1nm to 100nm
Between.
Described source electrode, drain material can be that by the metal or alloy of Ohmic contact, such as Ti/Al/Ti/Au
Alloy, Ti/Al/Mo/Au alloys, Ti/Al/Ni/Au alloys etc.；The material of the grid can be Ni/Au alloys, Pd/Au conjunctions
One kind among gold, Pt/Al alloys.
A kind of preparation method of the normally-off GaN MOSFET structures at high quality MOS interfaces, wherein：Comprise the following steps：
S1, Si substrates grow GaN epitaxial layer substrate；
S2, SiO2 mask medium layers are formed in GaN epitaxial layer；
S3, using photoetching technique, the SiO2 mask medium layers above selective retention area of grid；
S4, SiO2 mask medium layers both sides carry out secondary epitaxy, in high temperature environments the undoped GaN layer of growth selection with
And potential barrier of heterogenous junction layer, so as to form groove structure described above；
S5, by above area of grid SiO2 mask medium layers remove；
S6, gate insulator dielectric layer is deposited on exposed recess channel and on hetero-junctions；
S7, in source electrode and drain region carry out metal evaporation；
S8, by stripping technology, form the figure of source electrode and drain electrode；
The enterprising row metal evaporation of S9, the gate insulator dielectric layer in groove grids region；
S10, by stripping technology, form the figure of gate electrode.
The undoped GaN layer in GaN epitaxial layer and S4, potential barrier of heterogenous junction layer in the S1 can be used outside molecular beam
Prolong method or Metalorganic Chemical Vapor Deposition growth；The S6 can use inductive coupling type plasma etching technology；It is described
SiO2 mask medium layers in S2 and the growing method of the gate dielectric layer in S7 can use atomic layer deposition method, magnetron sputtering
Method, plasma enhanced chemical vapor deposition method or physical vaporous deposition etc..
In the S8, it is necessary to carry out short annealing in the environment full of nitrogen after the evaporation completion of source electrode and drain electrode,
So as to form the sufficiently low Ohmic contact of resistance；The S9 need not carry out annealing process.
Compared with prior art, beneficial effect is：With the device prepared by this method, flat rubber belting in its MOS interface C-V curve
It is 0.12V that voltage, which returns stagnant window, and GaN MOS interfaces flat rubber belting electricity on the sapphire that under the same conditions prepared by conventional dry etching
Push back stagnant window and reach 0.85V（V=6V, f=100kHz）, Comparatively speaking, the device prepared by this method shows more excellent
Threshold voltage stability, this phenomenon illustrate that selection region epitaxial bath grid MOS diode has more preferable MOS interface qualities.
Brief description of the drawings
Fig. 1-8 is the device preparation method process schematic representation of the embodiment of the present invention 1.
Fig. 9 is the GaN MOSFET prepared under device and the same terms prepared by the present invention using dry etching C-V
Flat-band voltage returns stagnant window comparison diagram in curve.
Embodiment
Accompanying drawing being given for example only property explanation, it is impossible to be interpreted as the limitation to this patent；It is attached in order to more preferably illustrate the present embodiment
Scheme some parts to have omission, zoom in or out, do not represent the size of actual product；To those skilled in the art,
Some known features and its explanation may be omitted and will be understood by accompanying drawing.Being given for example only property of position relationship described in accompanying drawing
Explanation, it is impossible to be interpreted as the limitation to this patent.
Embodiment 1
The device architecture of the present embodiment 1 by substrate 1, GaN layer substrate 2, undoped GaN layer 3, potential barrier of heterogenous junction layer 4, be covered in it is recessed
Gate dielectric layer 5, groove grids 8 on groove, the source electrode 6 positioned at grid both sides and drain electrode 7 are formed, as shown in Figure 8.
The normally-off GaN MOSFET at the high quality MOS interfaces prepare scheme as shown in Figures 1 to 8, and step is as follows：
S1, using Metalorganic Chemical Vapor Deposition, in Si substrate growth stresses cushion 11, GaN layer 12, the two structure
Into GaN layer substrate 2, as shown in Figure 1；
S2, in GaN epitaxial layer, using plasma enhanced chemical vapor deposition method grow one layer of SiO2 mask medium layer 9,
As shown in Figure 2；
S3, using photoetching technique, the SiO2 mask medium layers 10 above selective retention area of grid, remove remainder, such as
Shown in Fig. 3；
S4, on the substrate for having SiO2 mask medium layers, using Metalorganic Chemical Vapor Deposition carry out selective area outside
Prolong, grow undoped GaN layer 3 and potential barrier of heterogenous junction layer 4 successively, so as to form groove, as shown in Figure 4；
S5, with acid solution wet method remove Fig. 4 among area of grid SiO2 mask medium layers 10, as shown in Figure 5；
S6, on the structure shown in Fig. 5, the atomic layer deposition method such as utilize（ALD）One layer of high-k dielectric layer 5 of growth is used as grid
Dielectric layer, as shown in Figure 6；
S7, etching grid insulating medium layer both ends, source region and drain region are formed, as shown in Figure 7；
S8, in source region and drain region the evaporation of Ohm contact electrode is carried out, after evaporation is completed, pass through stripping technology shape
Into source electrode 6 and drain electrode 7, metal material used is Ti/Al/Ni/Au laminations, as shown in Figure 8；
, it is necessary to short annealing be carried out in the environment full of nitrogen, so as to form resistance after S9, source electrode and drain electrode evaporation completion
Sufficiently low Ohmic contact；
The enterprising row metal evaporation of S10, the gate insulator dielectric layer in groove grids region, alloy material used is Ni/Au alloys,
Metal gate electrode 8 is then formed by stripping technology, as shown in Figure 8.
So far, that is, a kind of normally-off GaN MOSFET at high quality MOS interfaces preparation process is completed.
Fig. 9 is device prepared by the present invention and the GaN MOSFET prepared under the conditions of same process using dry etching C-
V curve comparison figures.（a）For the C-V characteristic curves of selection region epitaxial bath grid GaN MOS diodes.（b）It is blue precious for dry etching
The C-V characteristic curves of GaN MOS diodes on stone.
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not pair
The restriction of embodiments of the present invention.For those of ordinary skill in the field, may be used also on the basis of the above description
To make other changes in different forms.There is no necessity and possibility to exhaust all the enbodiments.It is all this
All any modification, equivalent and improvement made within the spirit and principle of invention etc., should be included in the claims in the present invention
Protection domain within.
Claims (10)
1. the normally-off GaN MOSFET structures at a kind of high quality MOS interfaces, it is characterised in that be included in substrate（1）It is last
One layer of GaN epitaxial layer substrate of epitaxial growth（2）, in GaN epitaxial layer substrate（2）One layer of mask material of upper deposition（9）And form figure
The mask of shape（10）, grow undoped GaN epitaxial layer using secondary epitaxy（3）, potential barrier of heterogenous junction layer（4）, remove graphical
Mask（10）And self-assembling formation groove, deposit one layer of gate insulation dielectric layer（5）, the dielectric layer is covered in recess channel, secondary outer
Prolong on the side wall and surface of layer, source electrode is formed by metal evaporation（6）And drain electrode（7）And grid（8）.
A kind of 2. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that：
Described substrate（1）Material can be SiC, sapphire or Si, but not limited to this scope.
A kind of 3. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that：
Described GaN epitaxial layer substrate（2）Including stress-buffer layer（11）, GaN layer（12）, stress-buffer layer can be AlN, AlGaN,
GaN any or combination, for its thickness between 100 nm to 10 μm, GaN layer can be that C or Fe adulterates the high resistant to be formed
Layer or the epitaxial layer of unintentional doping, its thickness is between 100 nm to 10 μm.
A kind of 4. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that：
Described mask material（9）SiO2, SiNx, Al can be used2O3、AlN、HfO2、MgO、Sc2O3, its thickness between 1nm extremely
100nm 。
A kind of 5. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that：
Described undoped GaN layer（3）Thickness between 10 nm between 500nm, described potential barrier of heterogenous junction layer（4）Can be
The combination of any one or more material in AlGaN, AlInN, AlInGaN, AlN, InGaN, but not limited to this scope, its thickness
Between 5nm between 50nm, in undoped GaN epitaxial layer（3）With potential barrier of heterogenous junction layer（4）Between also grow one layer of 1nm extremely
AlN layers thick 10nm.
A kind of 6. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that：
Described gate insulator dielectric layer（5）Material can be SiO2, Al2O3, Sc2O3, SiNx, AlN, HfO2, MgO, Ga2O3,
Any one material in HfSiON, AlHfOx, or the stacked combination of many of material, thickness is between 1nm between 100nm.
A kind of 7. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that：
Described source electrode（6）, drain electrode（7）Material can be that by the metal or alloy of Ohmic contact, such as Ti/Al/Ti/Au is closed
Gold, Ti/Al/Mo/Au alloys, Ti/Al/Ni/Au alloys etc.；The grid（8）Material can be Ni/Au alloys, Pd/Au close
One kind among gold, Pt/Al alloys.
8. the preparation method of the normally-off GaN MOSFET structures at the high quality MOS interfaces described in claim 1, its feature exist
In：Comprise the following steps：
S1, Si substrates grow GaN epitaxial layer substrate（2）；
S2, SiO2 mask medium layers are formed in GaN epitaxial layer（9）；
S3, using photoetching technique, the SiO2 mask medium layers above selective retention area of grid（10）；
S4, in the both sides of SiO2 mask medium layers carry out secondary epitaxy, the under the high temperature conditions undoped GaN layer of growth selection
（3）And potential barrier of heterogenous junction layer（4）, so as to form groove structure described above；
S5, by above area of grid SiO2 mask medium layers remove；
S6, gate insulator dielectric layer is deposited on exposed recess channel and on hetero-junctions（5）；
S7, in source electrode and drain region carry out metal evaporation；
S8, pass through stripping technology, formation source electrode（6）And drain electrode（7）The figure of electrode；
The enterprising row metal evaporation of S9, the gate insulator dielectric layer in groove grids region；
S10, pass through stripping technology, formation gate electrode（8）Figure.
9. the preparation method of the normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 8, its feature
It is：The undoped GaN layer in GaN epitaxial layer and S4, potential barrier of heterogenous junction layer in the S1 can use molecular beam epitaxy
Method or Metalorganic Chemical Vapor Deposition growth；The S6 can use inductive coupling type plasma etching technology；The S2
In SiO2 mask medium layers and the gate dielectric layer in S7 growing method can use atomic layer deposition method, magnetron sputtering method,
Plasma enhanced chemical vapor deposition method or physical vaporous deposition etc..
10. the preparation method of the normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 8, it is special
Sign is：In the S8, source electrode（6）And drain electrode（7）Evaporation complete after, it is necessary to be carried out in the environment full of nitrogen quick
Annealing, so as to form the sufficiently low Ohmic contact of resistance；The S9 need not carry out annealing process.
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