CN113628963B - III-nitride enhanced HEMT device and manufacturing method thereof - Google Patents

III-nitride enhanced HEMT device and manufacturing method thereof Download PDF

Info

Publication number
CN113628963B
CN113628963B CN202110898168.9A CN202110898168A CN113628963B CN 113628963 B CN113628963 B CN 113628963B CN 202110898168 A CN202110898168 A CN 202110898168A CN 113628963 B CN113628963 B CN 113628963B
Authority
CN
China
Prior art keywords
layer
region
nitride
drain
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110898168.9A
Other languages
Chinese (zh)
Other versions
CN113628963A (en
Inventor
宁殿华
蒋胜
柳永胜
程新
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Yingjiatong Semiconductor Co ltd
Original Assignee
Suzhou Yingjiatong Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Yingjiatong Semiconductor Co ltd filed Critical Suzhou Yingjiatong Semiconductor Co ltd
Priority to CN202110898168.9A priority Critical patent/CN113628963B/en
Publication of CN113628963A publication Critical patent/CN113628963A/en
Application granted granted Critical
Publication of CN113628963B publication Critical patent/CN113628963B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention discloses a III-nitride enhanced HEMT device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate; epitaxially growing a channel layer on a substrate; forming a mask in the gate region on the channel layer; epitaxially growing a barrier layer on the channel layer outside the mask based on the selective region growth process; removing the mask; etching the III-nitride heterojunction to form a source electrode region and a drain electrode region; forming a source and a drain in the source region and the drain region, respectively; epitaxially growing an insulating dielectric layer on the gate region; and forming a grid electrode on the insulating medium layer. According to the invention, based on a selective area growth process, a barrier layer is preferentially grown outside a grid area, and then an insulating medium layer and a grid are formed, so that a disconnected two-dimensional electron gas channel is formed at one time; the invention does not need etching or ion implantation treatment on the surface of the grid electrode or the barrier layer in the traditional process, and effectively avoids etching damage or lattice damage caused by the traditional process.

Description

III-nitride enhanced HEMT device and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and a manufacturing method thereof.
Background
Gallium nitride (GaN) -based High Electron Mobility Transistor (HEMT) has been widely used in the field of power electronic devices such as high temperature, high frequency, high voltage, high power, etc. because gallium nitride material has the advantages of large forbidden bandwidth, large breakdown field strength, high carrier saturation mobility, etc. The AlGaN/GaN heterostructure has strong spontaneous polarization and piezoelectric polarization effects, and can generate high-concentration carriers at an interface, namely two-dimensional electron gas (2 DEG), and the channel modulation mechanism of the high-electron mobility transistor formed based on the AlGaN/GaN heterostructure belongs to depletion mode. However, from the viewpoint of safe operation and low power consumption of the application, an enhanced (E-mode) power transistor is more favored by circuit designers, and the use of an enhanced power transistor can avoid the use of a negative voltage power supply to simplify the design of the gate driving circuit.
Currently, several mainstream technologies for fabricating gallium nitride enhancement devices include gate recess, fluoride ion implantation, p-type gallium nitride gate, and the like. The gate groove technology needs an etching process, and damage caused by the etching process can cause the increase of gate leakage and uneven threshold voltage; the fluorine ion implantation technology has the problem of poor stability of threshold voltage under high field and high temperature stress; the p-type gallium nitride grid electrode technology needs to grow an additional layer of p-type gallium nitride epitaxy, the technology cost is high, the growth uniformity of the p-type gallium nitride and magnesium (Mg) activation are difficult to achieve, the p-type gallium nitride outside the grid electrode area needs to be removed through etching, the process also brings etching damage to the transistor interface characteristic, meanwhile, the voltage withstand of the p-type gallium nitride grid electrode is low and is usually smaller than +7V, and the difficulty of circuit design is increased.
Selective-area growth (SAG) technology has been used for growing p-type gallium nitride, and enhancement-type transistors fabricated by this technology have been reported in succession, wherein silicon oxide is used as a hard mask by a Metal-organic chemical vapor deposition (MOCVD) system to selectively grow p-type gallium nitride in the gate region of an algan/gan heterostructure. The method has the advantages that the etching step in the conventional technical route for manufacturing the enhanced transistor by using p-type gallium nitride is not needed, the etching damage to the surface of aluminum gallium nitride is avoided, and the current collapse effect caused by surface defects can be effectively reduced. In addition, there are reports of growing AlGaN using selective area growth techniques, but there are few applications of this to the fabrication of enhancement transistors.
Therefore, in view of the above technical problems, it is necessary to provide a group iii nitride enhancement HEMT device and a method for manufacturing the same.
Disclosure of Invention
In view of the above, the present invention aims to provide a group iii nitride enhancement HEMT device and a method for manufacturing the same.
In order to achieve the above object, an embodiment of the present invention provides the following technical solution:
a method of manufacturing a group iii nitride enhanced HEMT device, the method comprising:
providing a substrate;
epitaxially growing a channel layer on a substrate, wherein the channel layer is a III-nitride channel layer;
forming a mask in the gate region on the channel layer;
epitaxially growing a barrier layer on the channel layer outside the mask based on a selective region growth process, wherein the barrier layer is a III-nitride barrier layer, and the channel layer and the barrier layer form a III-nitride heterojunction;
removing the mask;
etching the III-nitride heterojunction to form a source electrode region and a drain electrode region;
forming a source and a drain in the source region and the drain region, respectively;
epitaxially growing an insulating dielectric layer on the gate region;
and forming a grid electrode on the insulating medium layer.
In one embodiment, in the manufacturing method, the "forming a mask in the gate region on the channel layer" is specifically: forming a dielectric mask by epitaxially growing a dielectric material in a gate region on the channel layer, wherein the mask removal is specifically: removing the dielectric mask by adopting a dry etching process or a wet etching process; or alternatively, the first and second heat exchangers may be,
the "forming a mask in the gate region on the channel layer" is specifically: a metal mask is formed by depositing metal in the gate region on the channel layer, and the "mask removal" is specifically: removing the metal mask by adopting a stripping process;
wherein the dielectric mask is made of one or more of silicon nitride and silicon oxide;
the metal mask is made of one or a combination of more of titanium and nickel;
the thickness of the mask is 30-100 nm.
In one embodiment, the manufacturing method further comprises:
epitaxially growing an insulating medium layer on the grid region, the barrier layer and the source electrode and the drain electrode;
the insulating dielectric layer over the source and drain electrodes is etched to expose the source and drain electrodes.
In an embodiment, the substrate is any one of a silicon substrate, a sapphire substrate and a silicon carbide substrate; and/or the number of the groups of groups,
the insulating medium layer is one or a combination of more than one of a silicon nitride layer, a silicon oxide layer, an aluminum nitride layer and a gallium oxide layer, and the thickness of the insulating medium layer is 5-20 nm; and/or the number of the groups of groups,
the substrate is provided with a buffer layer, and the buffer layer is one or a combination of a plurality of gallium nitride buffer layers, aluminum nitride buffer layers and aluminum gallium nitride buffer layers; and/or the number of the groups of groups,
an isolation layer is formed in the channel layer and the barrier layer, and is an aluminum nitride isolation layer; and/or the number of the groups of groups,
the III-nitride heterojunction is an AlGaN/GaN heterojunction; and/or the number of the groups of groups,
the channel layer is a GaN channel layer, and the thickness is 50 nm-2 mu m; and/or the number of the groups of groups,
the barrier layer is Al x GaN 1-x The barrier layer has a thickness of 10nm to 30nm, wherein x=0.1 to 0.3.
In one embodiment, the manufacturing method further comprises:
epitaxially growing a plurality of passivation layers on the barrier layer; the method comprises the steps of,
a plurality of electrode field plates are formed on the passivation layer.
In one embodiment, the manufacturing method further comprises:
epitaxially growing a first passivation layer over the insulating dielectric layer;
etching the first passivation layer to expose the insulating dielectric layer of the gate region;
etching the first passivation layer and the insulating dielectric layer to expose the source electrode and the drain electrode;
forming a gate field plate electrically connected with the gate electrode on the first passivation layer;
epitaxially growing a second dielectric layer on the first passivation layer and the gate field plate;
etching the second passivation layer to expose the source electrode and the drain electrode;
forming a source field plate electrically connected with the source electrode and/or a drain field plate electrically connected with the drain electrode on the second passivation layer;
epitaxially growing a third dielectric layer on the second passivation layer and the source field plate and/or the drain field plate;
etching the third dielectric layer to expose all or part of the source field plate and/or the drain field plate;
the gate, the source, the drain, the gate field plate, the source field plate and/or the drain field plate are made of metal and/or metal compound, wherein the metal comprises one or more of gold, platinum, nickel, titanium, aluminum, palladium, tantalum and tungsten, and the metal compound comprises one or more of titanium nitride and tantalum nitride; and/or the number of the groups of groups,
the first passivation layer is one or a combination of a plurality of silicon nitride passivation layers, silicon oxide passivation layers and aluminum oxide passivation layers; and/or the number of the groups of groups,
the second passivation layer is one or a combination of more of a silicon nitride passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer; and/or the number of the groups of groups,
the third passivation layer is one or a combination of more of a silicon nitride passivation layer, a silicon oxide passivation layer and a polyimide passivation layer.
In an embodiment, in the manufacturing method, the first passivation layer and/or the second passivation layer and/or the third passivation layer are etched by a dry etching process and/or a wet etching process;
wherein, the dry etching process adopts plasma to etch, and the wet etching process adopts acid solution or alkaline solution to etch.
In one embodiment, the method of fabricating the group iii nitride heterojunction is specifically:
etching all or part of the barrier layer to form a source region and a drain region; or alternatively, the first and second heat exchangers may be,
and etching all the barrier layer and part of the channel layer to form a source region and a drain region.
In one embodiment, the manufacturing method further comprises:
performing passive region isolation in the III-nitride heterojunction at the side of the source electrode and/or the drain electrode by adopting an ion implantation process or an etching process to form an isolation region;
wherein, ions in the ion implantation process are O ions or F ions, and etching gas in the etching process is BCl 3 Or Cl 2 。
The technical scheme provided by the other embodiment of the invention is as follows:
the III-nitride enhanced HEMT device is manufactured by adopting the manufacturing method, and comprises:
a substrate;
a channel layer on the substrate, the channel layer being a group iii nitride channel layer;
a barrier layer on the channel layer outside the gate region, the barrier layer being a group iii nitride barrier layer, the channel layer and the barrier layer forming a group iii nitride heterojunction;
a source region and a drain region formed in the group iii nitride heterojunction;
a source and a drain in the source region and the drain region;
an insulating dielectric layer located in the gate region over the channel layer and over all or a portion of the barrier layer;
and a gate electrode on the insulating dielectric layer in the gate region.
The invention has the following beneficial effects:
according to the invention, based on a selective area growth process, a barrier layer is preferentially grown outside a grid area, and then an insulating medium layer and a grid are formed, so that a disconnected two-dimensional electron gas channel is formed at one time;
the invention does not need etching or ion implantation treatment on the surface of the grid electrode or the barrier layer in the traditional process, and effectively avoids etching damage or lattice damage caused by the traditional process.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a group iii nitride enhancement HEMT device according to an embodiment of the present invention;
fig. 2-9 are process flow diagrams of a method of fabricating a group iii nitride enhancement mode HEMT device in accordance with an embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
Referring to fig. 1, a group iii nitride enhancement mode HEMT device according to an embodiment of the present invention includes:
a substrate 10;
a buffer layer 20 on the substrate 10;
a channel layer 30 on the buffer layer 20, the channel layer 30 being a group iii nitride channel layer;
a barrier layer 40 on the channel layer 30 outside the gate region, the barrier layer 40 being a group iii nitride barrier layer, the channel layer and the barrier layer forming a group iii nitride heterojunction, a two-dimensional electron gas 2DEG being formed in the channel layer 30;
source and drain regions formed in the group iii nitride heterojunction, the source and drain regions in this embodiment being formed in all of the barrier layer 40 and part of the channel layer 30, and in other embodiments may be formed only in all or part of the barrier layer 40;
a source electrode 61 and a drain electrode 62 located in the source region and the drain region;
an insulating dielectric layer 70 located in the gate region over the channel layer 30 and over all of the barrier layer 40;
a gate electrode 63 on the insulating dielectric layer;
a first passivation layer 51 over the insulating dielectric layer 70;
the gate field plate 631 is located above the first passivation layer 51 and is electrically connected to the gate 63;
a second passivation layer 52 over the gate field plate 631 and the first passivation layer 51;
a source field plate 611 disposed above the second passivation layer 52 and electrically connected to the source electrode 61;
the third passivation layer 53 is positioned over the source field plate 611 and the second passivation layer 52.
The following describes a group iii nitride enhancement HEMT device and a method for manufacturing the same in this embodiment in detail with reference to the accompanying drawings.
Referring to fig. 2, first, a buffer layer 20 and a channel layer 30 are epitaxially grown on a substrate 10, and a mask 90 is formed in a gate region on the channel layer.
Wherein the substrate 10 is a silicon (Si) substrate, sapphire (Al) 2 O 3 ) Any one of a substrate, a silicon carbide (SiC) substrate, and the like; the buffer layer 20 is one or a combination of a plurality of GaN buffer layers, alN buffer layers, alGaN buffer layers and the like; the channel layer 30 is a group III nitride, in this example a GaN channel layer, and has a thickness of 50nm to 2 μm.
Preferably, an isolation layer (not shown) may be further grown on the channel layer 30, and the isolation layer may be a nitride isolation layer, such as an aluminum nitride isolation layer (AlN spacer).
In the invention, a dielectric mask is formed by epitaxially growing a dielectric material on the channel layer, and then the dielectric mask outside the grid region is removed by adopting a dry etching process or a wet etching process; a metal mask may also be formed by depositing metal on the channel layer and then removing the metal mask outside the gate region using a lift-off process.
The dielectric mask can be one or a combination of a plurality of dielectric materials such as silicon nitride, silicon oxide and the like; the metal mask can be one or a combination of a plurality of high-melting-point metals such as titanium, nickel and the like; the thickness of the mask is 30-100 nm.
Referring to fig. 3, a barrier layer 40, which is a group iii nitride barrier layer, is epitaxially grown on the channel layer 30 outside of the mask 90 based on a selective region growth process, the channel layer and the barrier layer forming a group iii nitride heterojunction.
The barrier layer 40 in this embodiment is Al x GaN 1-x The barrier layer has a thickness of 10nm to 30nm, wherein x=0.1 to 0.3. The channel layer 30 and the barrier layer 40 form an AlGaN/GaN heterojunction.
At this time, al grows in the region other than the mask 90 x GaN 1-x The barrier layer directly contacts the GaN channel layer, and the AlGaN/GaN heterojunction structure generates a two-dimensional electron gas 2DEG in the channel layer 30 due to spontaneous polarization and piezoelectric polarization effects, while the gate region (the insulating dielectric layer and the gate electrode which are formed later) is difficult to form or forms a small amount of irregularly shaped AlGaN, and a two-dimensional electron gas is not generated thereunder, and generally, an effect of naturally forming an enhancement type (E-mode) on a depletion type (D-mode) epitaxy is achieved. Compared with the traditional method for manufacturing the enhanced (E-mode) by using a grid groove, fluoride ion injection, a p-type gallium nitride grid and the like, the method avoids etching damage or lattice damage caused by a production process.
Referring to fig. 4, mask 90 is removed.
Different mask removing modes are different, and the removing modes can be dry low-damage etching, wet acid-base solution etching and the like. Compared with the traditional method for manufacturing E-mdoe by using a grid groove, fluoride ion injection, a p-type gallium nitride grid and the like, the method avoids etching damage or lattice damage caused by a production process.
Referring to fig. 5, a group iii nitride heterojunction is etched to form a source region 601 and a drain region 602.
The steps may be:
pre-etching part of the barrier layer 40 to a depth of 0-10 nm;
the rest of the barrier layer 40 and part of the channel layer 30 are ohmic etched to form a source region 601 and a drain region 602, and the ohmic etching depth is 0-30 nm below the interface of the channel layer and the barrier layer (AlGaN/GaN).
The ohmic etching and pre-etching in the embodiment are beneficial to reducing the annealing temperature of ohmic metal and the annealing time, and can enable the ohmic metal and the semiconductor layer to form ohmic contact better. Of course, in other embodiments, the ohmic etching or pre-etching step may not be performed, and correspondingly, a higher annealing temperature or a longer annealing time may be required.
As shown in fig. 6, a source electrode 61 and a drain electrode 62 are formed in a source region 601 and a drain region 602, respectively.
The source/drain metal material may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), tantalum (Ta), tungsten (W), molybdenum (Mo), or metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal forming mode can be evaporation or sputtering, photoresist and redundant metal can be removed in a stripping mode after the metal forming mode is adopted, and metal in the area except the source drain can be removed in a metal etching mode.
Referring to fig. 7, an insulating dielectric layer 70 is epitaxially grown on the gate region, barrier layer 40, and source 61 and drain 62.
The insulating dielectric layer can be silicon nitride (SiN) layer, silicon oxide (SiO) 2 ) Layer, alumina (Al) 2 O 3 ) Layer, aluminum nitride (AlN) layer, gallium oxide (Ga) 2 O 3 ) And the thickness of the composite dielectric layer is 5-20 nm.
Referring to fig. 8, a first passivation layer 51 is epitaxially grown over the insulating dielectric layer 70.
The material of the first passivation layer can be insulating media such as silicon nitride, silicon oxide, aluminum oxide and the like or composite media composed of different insulating media. The first passivation layer may be planarized by Chemical Mechanical Polishing (CMP) after it has been grown.
After the growth is completed, the first passivation layer 51 is etched to expose the insulating dielectric layer 70 of the gate region, and the first passivation layer 51 and the insulating dielectric layer 70 are etched to expose the source electrode 61 and the drain electrode 62.
The etching mode can be dry plasma etching or wet etching, or can be a combination mode of dry etching and wet etching.
It should be noted that, the dielectric layer near the surface of the insulating dielectric layer may be removed by wet etching or low damage etching, so as to reduce damage to the surface of the insulating dielectric layer in the gate region. And then removing the insulating dielectric layers in the source electrode window and the drain electrode window, wherein the removing mode can be dry plasma etching or wet etching by using an acidic or alkaline solution according to the material of the insulating dielectric layers.
Then, a gate electrode 63 is formed in the gate region on the insulating dielectric layer 70, and a gate field plate 631 electrically connected to the gate electrode 63 is formed over the first passivation layer 51.
The gate and the gate field plate may be made of high melting point metals such as platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), molybdenum (Mo), or metal compounds or alloys such as titanium nitride (TiN), tantalum nitride (TaN), tungsten titanium (WTi), etc. The grid electrode and the grid field plate can be formed by evaporation or sputtering, photoresist and redundant metal can be removed by adopting a stripping mode after the formation, and metal except the grid electrode area can be removed by adopting a metal etching mode. At this time, the gate electrode and the insulating dielectric layer and Semiconductor layer thereunder form a Metal-Insulator-Semiconductor (MIS) structure.
The gate electrode and the gate field plate in this embodiment are formed by a single evaporation or sputtering process, and in other embodiments may be formed by two steps.
Then, an ion implantation process or an etching process is used to perform passive region isolation in the group iii nitride heterojunction beside the source 61 and the drain 62, thereby forming an isolation region 80.
The passive region is isolated by adopting an ion implantation process to implant strong electronegativity O ions or F ions and the like, or by adopting an etching process, and the etching gas can be BCl 3 、Cl 2 Etc.
If the isolation mode adopts an etching process, the step can also be performed before the formation of the source drain metal, and at this time, the first passivation layer is not formed yet, so that the etching depth and the etching time can be reduced.
Then, a second dielectric layer 52 is epitaxially grown on the first passivation layer 51 and the gate field plate 631, and the second passivation layer 52 is etched to expose the source electrode 61 and the drain electrode 62.
The material of the second passivation layer can be insulating media such as silicon nitride, silicon oxide and the like or composite media composed of different insulating media. The second passivation layer may be planarized by Chemical Mechanical Polishing (CMP) after it has been grown.
Next, windows are formed in the source electrode region and the drain electrode region, and the window forming mode may be dry plasma etching, wet etching with an acidic solution, or a combination of dry etching and wet etching.
Then, a source field plate 611 electrically connected to the source electrode 61 is formed on the second passivation layer 52.
The source field plate material may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), tantalum (Ta), tungsten (W), or the like, and may include a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). The source field plate metal can be formed by evaporation or sputtering, photoresist and redundant metal can be removed by stripping after formation, and metal in the area except the source field plate and the drain can be removed by metal etching.
Finally, a third dielectric layer 53 is epitaxially grown on the second passivation layer 52 and the source field plate, and etched to expose the source field plate and the drain electrode.
The material of the third passivation layer can be insulating media such as silicon nitride, silicon oxide, polyimide (PI) or composite media composed of different insulating media. After the third passivation layer is grown, it may be planarized by Chemical Mechanical Polishing (CMP).
And forming windows in the source electrode region and the drain electrode region, wherein the window forming mode can be dry plasma etching or wet etching by selecting an acid solution according to the material of the dielectric layer, or can be a mode of combining dry etching and wet etching.
The resulting enhanced HEMT device structure is shown in fig. 9.
It should be understood that, in the above embodiments, the gate field plate and the source field plate are taken as examples, and the second passivation layer and the third passivation layer need to be continued to be extended on the first passivation layer, and in other embodiments, the gate field plate and the source field plate may not be provided, or a drain field plate may be added, which falls within the scope of protection of the present invention.
As can be seen from the technical scheme, the invention has the following advantages:
according to the invention, based on a selective area growth process, a barrier layer is preferentially grown outside a grid area, and then an insulating medium layer and a grid are formed, so that a disconnected two-dimensional electron gas channel is formed at one time;
the invention does not need etching or ion implantation treatment on the surface of the grid electrode or the barrier layer in the traditional process, and effectively avoids etching damage or lattice damage caused by the traditional process.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.

Claims (10)

1. A method of manufacturing a group iii nitride enhanced HEMT device, the method comprising:
providing a substrate;
epitaxially growing a channel layer on a substrate, wherein the channel layer is a III-nitride channel layer;
forming a mask in a gate region on the channel layer, specifically: forming a metal mask by depositing metal in the gate region on the channel layer;
epitaxially growing a barrier layer on the channel layer outside the mask based on a selective region growth process, wherein the barrier layer is a III-nitride barrier layer, and the channel layer and the barrier layer form a III-nitride heterojunction;
removing the mask, specifically: removing the metal mask by adopting a stripping process;
etching the III-nitride heterojunction to form a source electrode region and a drain electrode region;
forming a source and a drain in the source region and the drain region, respectively;
epitaxially growing an insulating dielectric layer on the gate region;
and forming a grid electrode on the insulating medium layer.
2. The method of manufacturing a group iii nitride enhancement HEMT device of claim 1, wherein the metal mask is made of one or a combination of titanium and nickel;
the thickness of the metal mask is 30-100 nm.
3. The method of manufacturing a group iii nitride enhancement HEMT device of claim 1, further comprising:
epitaxially growing an insulating medium layer on the grid region, the barrier layer and the source electrode and the drain electrode;
the insulating dielectric layer over the source and drain electrodes is etched to expose the source and drain electrodes.
4. The method of manufacturing a group iii nitride enhancement HEMT device according to claim 1, wherein the substrate is any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate; and/or the number of the groups of groups,
the insulating medium layer is one or a combination of more than one of a silicon nitride layer, a silicon oxide layer, an aluminum nitride layer and a gallium oxide layer, and the thickness of the insulating medium layer is 5-20 nm; and/or the number of the groups of groups,
the substrate is provided with a buffer layer, and the buffer layer is one or a combination of a plurality of gallium nitride buffer layers, aluminum nitride buffer layers and aluminum gallium nitride buffer layers; and/or the number of the groups of groups,
an isolation layer is formed in the channel layer and the barrier layer, and is an aluminum nitride isolation layer; and/or the number of the groups of groups,
the III-nitride heterojunction is an AlGaN/GaN heterojunction; and/or the number of the groups of groups,
the channel layer is a GaN channel layer, and the thickness of the channel layer is 50 nm-2 mu m; and/or the number of the groups of groups,
the barrier layer is Al x GaN 1-x The barrier layer has a thickness of 10nm to 30nm, wherein x=0.1 to 0.3.
5. The method of manufacturing a group iii nitride enhancement HEMT device of claim 1 or 3, further comprising:
epitaxially growing a plurality of passivation layers on the barrier layer; the method comprises the steps of,
a plurality of electrode field plates are formed on the passivation layer.
6. The method of manufacturing a group iii nitride enhancement HEMT device of claim 3, further comprising:
epitaxially growing a first passivation layer over the insulating dielectric layer;
etching the first passivation layer to expose the insulating dielectric layer of the gate region;
etching the first passivation layer and the insulating dielectric layer to expose the source electrode and the drain electrode;
forming a gate field plate electrically connected with the gate electrode on the first passivation layer;
epitaxially growing a second passivation layer on the first passivation layer and the gate field plate;
etching the second passivation layer to expose the source electrode and the drain electrode;
forming a source field plate electrically connected with the source electrode and/or a drain field plate electrically connected with the drain electrode on the second passivation layer;
epitaxially growing a third passivation layer on the second passivation layer and the source field plate and/or the drain field plate;
etching the third passivation layer to expose all or part of the source field plate and/or the drain field plate;
the gate, the source, the drain, the gate field plate, the source field plate and/or the drain field plate are made of metal and/or metal compound, wherein the metal comprises one or more of gold, platinum, nickel, titanium, aluminum, palladium, tantalum and tungsten, and the metal compound comprises one or more of titanium nitride and tantalum nitride; and/or the number of the groups of groups,
the first passivation layer is one or a combination of a plurality of silicon nitride passivation layers, silicon oxide passivation layers and aluminum oxide passivation layers; and/or the number of the groups of groups,
the second passivation layer is one or a combination of more of a silicon nitride passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer; and/or the number of the groups of groups,
the third passivation layer is one or a combination of more of a silicon nitride passivation layer, a silicon oxide passivation layer and a polyimide passivation layer.
7. The method for manufacturing the group iii nitride enhancement HEMT device according to claim 6, wherein in the method for manufacturing the group iii nitride enhancement HEMT device, the first passivation layer and/or the second passivation layer and/or the third passivation layer are etched by a dry etching process and/or a wet etching process;
wherein, the dry etching process adopts plasma to etch, and the wet etching process adopts acid solution or alkaline solution to etch.
8. The method of manufacturing a group iii nitride enhancement HEMT device according to claim 1, wherein the method of manufacturing, etching the group iii nitride heterojunction to form the source region and the drain region, comprises:
etching all or part of the barrier layer to form a source region and a drain region; or alternatively, the first and second heat exchangers may be,
and etching all the barrier layer and part of the channel layer to form a source region and a drain region.
9. The method of manufacturing a group iii nitride enhancement HEMT device of claim 1, further comprising:
performing passive region isolation in the III-nitride heterojunction at the side of the source electrode and/or the drain electrode by adopting an ion implantation process or an etching process to form an isolation region;
wherein, ions in the ion implantation process are O ions or F ions, and etching gas in the etching process is BCl 3 Or Cl 2 。
10. A group iii nitride enhanced HEMT device, wherein the group iii nitride enhanced HEMT device is manufactured by the manufacturing method of any one of claims 1-9, the group iii nitride enhanced HEMT device comprising:
a substrate;
a channel layer on the substrate, the channel layer being a group iii nitride channel layer;
a barrier layer on the channel layer outside the gate region, the barrier layer being a group iii nitride barrier layer, the channel layer and the barrier layer forming a group iii nitride heterojunction;
a source region and a drain region formed in the group iii nitride heterojunction;
a source and a drain in the source region and the drain region;
an insulating dielectric layer located in the gate region over the channel layer and over all or a portion of the barrier layer;
and a gate electrode on the insulating dielectric layer in the gate region.
CN202110898168.9A 2021-08-05 2021-08-05 III-nitride enhanced HEMT device and manufacturing method thereof Active CN113628963B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110898168.9A CN113628963B (en) 2021-08-05 2021-08-05 III-nitride enhanced HEMT device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110898168.9A CN113628963B (en) 2021-08-05 2021-08-05 III-nitride enhanced HEMT device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN113628963A CN113628963A (en) 2021-11-09
CN113628963B true CN113628963B (en) 2024-03-08

Family

ID=78383024

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110898168.9A Active CN113628963B (en) 2021-08-05 2021-08-05 III-nitride enhanced HEMT device and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN113628963B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104051522A (en) * 2014-07-02 2014-09-17 苏州晶湛半导体有限公司 Enhanced nitride semiconductor device and manufacturing method thereof
CN107706241A (en) * 2017-10-31 2018-02-16 中山大学 A kind of normally-off GaNMOSFET structures at high quality MOS interfaces and preparation method thereof
TWI680503B (en) * 2018-12-26 2019-12-21 杰力科技股份有限公司 Method of manufacturing gate structure for gallium nitride hemt
WO2020221222A1 (en) * 2019-04-30 2020-11-05 大连理工大学 High-threshold-voltage normally-off high-electron-mobility transistor and preparation method therefor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140335666A1 (en) * 2013-05-13 2014-11-13 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Growth of High-Performance III-Nitride Transistor Passivation Layer for GaN Electronics

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104051522A (en) * 2014-07-02 2014-09-17 苏州晶湛半导体有限公司 Enhanced nitride semiconductor device and manufacturing method thereof
CN107706241A (en) * 2017-10-31 2018-02-16 中山大学 A kind of normally-off GaNMOSFET structures at high quality MOS interfaces and preparation method thereof
TWI680503B (en) * 2018-12-26 2019-12-21 杰力科技股份有限公司 Method of manufacturing gate structure for gallium nitride hemt
WO2020221222A1 (en) * 2019-04-30 2020-11-05 大连理工大学 High-threshold-voltage normally-off high-electron-mobility transistor and preparation method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
崔兴涛."凹槽栅型GaN HEMT器件的研制"."凹槽栅型GaN HEMT器件的研制".2019,第22页3.1.2 器件表面钝化,第23页倒数第1段，第34页，图3-12. *

Also Published As

Publication number Publication date
CN113628963A (en) 2021-11-09

Similar Documents

Publication Publication Date Title
WO2019136864A1 (en) Group iii nitride-enhanced hemt based on composite potential barrier layer structure and manufacturing method thereof
WO2011043110A1 (en) Semiconductor device and method for manufacturing same
JP2013235873A (en) Semiconductor device and method of manufacturing the same
KR102080745B1 (en) Nitride semiconductor and method thereof
JP2011029506A (en) Semiconductor device
CN113380623A (en) Method for realizing enhanced HEMT (high Electron mobility transistor) through p-type passivation
JP2009164235A (en) Nitride semiconductor element and its manufacturing method
TW201436008A (en) Heterojunction transistor and method of fabricating the same
JP5546104B2 (en) GaN-based field effect transistor
JP2018060847A (en) Semiconductor device
CN113594036A (en) III-nitride enhanced HEMT device and manufacturing method thereof
CN113628964B (en) III-nitride enhanced HEMT device and manufacturing method thereof
CN114899227A (en) Enhanced gallium nitride-based transistor and preparation method thereof
CN116169169A (en) Enhanced GaN HEMTs with low gate leakage current and preparation method thereof
WO2023045046A1 (en) Gold-free ohmic contact electrode, semiconductor device, and radio-frequency device and manufacturing method therefor
JP7052503B2 (en) Transistor manufacturing method
CN113628962B (en) III-nitride enhanced HEMT device and manufacturing method thereof
JP5355927B2 (en) Semiconductor device and manufacturing method of semiconductor device
CN116387246A (en) p-GaN enhanced MIS-HEMT device and preparation method thereof
CN111755330A (en) Semiconductor structure and manufacturing method thereof
CN113628963B (en) III-nitride enhanced HEMT device and manufacturing method thereof
JP2008118082A (en) Nitride semiconductor device and method of manufacturing the same
JP2010165783A (en) Field effect transistor, and method of manufacturing the same
JP4869576B2 (en) Nitride semiconductor device and manufacturing method thereof
JP2008227432A (en) Nitride compound semiconductor element and its production process

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant