JP2010165783A - Field effect transistor, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve normally-off of an HFET formed of a nitride-based III-V compound semiconductor. <P>SOLUTION: On an Al<SB>0.2</SB>Ga<SB>0.8</SB>N barrier layer 4 laminated on a GaN channel layer 3, a gate electrode 7 is formed to fill the inside of a recess part 8 formed with random dimension and shape. When, in this way, an area where two-dimensional electron gas (2DEG) occurs is reduced and the overall 2DEG density is lowered, normally-off can be achieved. In this process, when a dislocation part (a crystal defect part) in the AlGaN barrier layer 4 is selectively subjected to wet etching, the recess part 8 with the random dimension and shape is formed without causing damage, and deterioration of channel mobility is suppressed to prevent increase in on-state resistance in a channel region. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a normally-off type field effect transistor made of a nitride III-V compound semiconductor and a method for manufacturing the same.

  Conventionally, in a field effect transistor (HFET) having an AlGaN / GaN heterostructure using a nitride III-V compound semiconductor, the C surface of the nitride III-V compound semiconductor having a wurtzite structure is used as the substrate surface. Therefore, electrons are induced by the piezo effect and spontaneous polarization, and a two-dimensional electron gas (2DEG) is formed at the AlGaN / GaN interface. As a result, even when the gate voltage is zero, when a voltage is applied between the source and the drain, a drain current flows. Therefore, it is called a normally-on type transistor.

  However, when considering application to a general circuit that does not use a negative power supply, a normally-off type transistor in which a drain current does not flow when the gate voltage is zero is more desirable. Therefore, several methods for normally-off HFETs using nitride III-V compound semiconductors have been tried.

One of them is a field effect transistor disclosed in Japanese Patent Laid-Open No. 2000-277724 (Patent Document 1). In the field effect transistor disclosed in Patent Document 1, on the (0001) plane of the sapphire substrate 1, a low-temperature GaN buffer layer, an undoped GaN layer, an n-Al _x Ga _1-x N electron supply layer, and an n ⁺ -Al _y Ga _1-y N contact layers are grown sequentially. Next, the ^{_{n + -Al y Ga 1-y}} N forming a source electrode and a drain electrode on the contact layer, the ^{_{n + -Al y Ga 1-y}} N contact layer immediately below the gate region is etched away above The gate region of the n-Al _x Ga _1-x N electron supply layer is exposed, and a gate electrode is formed in the gate region. At that time, the gate region of the n-Al _x Ga _1-x N electron supply layer is thinned, for example, by dry etching, thereby providing the n-Al _x Ga _1-x N electron supply in the undoped GaN layer. Normally OFF is achieved by adjusting the amount of 2DEG formed in the vicinity of the boundary with the layer.

  The other one is “To AlGaN / GaN formed on a nonpolar (11-20) surface disclosed in IEICE Technical Report ED2005-199-208, P35-P39 (Non-Patent Document 1). “Normally off operation of terror junction transistor”. In this Non-Patent Document 1, undoped GaN and AlGaN are grown on a sapphire R-plane substrate in this order by MOCVD (Metal-Organic Chemical Vapor Deposition), so that spontaneous polarization and piezo polarization can be achieved. It is disclosed that a non-polar a-plane AlGaN / GaN heterostructure of wurtzite structure can be formed, and a normally-off operation is obtained by forming an HFET using this a-plane AlGaN / GaN heterostructure. Has been.

  The other is a method using a MIS structure transistor which does not use an AlGaN / GaN heterostructure similar to the Si MOS transistor disclosed in IWN2006 Technical Digest WeED1-1 p144 (Non-Patent Document 2).

  However, the conventional nitride-based III-V compound semiconductor HFET normally has the following problems.

That is, the problem at the time of the normally-off is how,
(1) Is it possible to avoid an increase in on-resistance?
(2) Can high channel mobility be maintained?
It is in that point. From this point, verifying the conventional normally-off,
In the field effect transistor disclosed in Patent Document 1, since the 2DEG is present at the AlGaN / GaN interface in the source region and the drain region, an increase in on-resistance in the source region and the drain region can be avoided. However, the above-mentioned 2DEG in the channel region is decreased, and the damage to the n-AlGaN electron supply layer due to the dry etching reduces the channel mobility, so that the on-resistance increases in the channel region. is there.

  In addition, the HFET using the a-plane AlGaN / GaN heterostructure disclosed in Non-Patent Document 1 uses a non-polar surface (for example, a-plane or m-plane) of the wurtzite structure, so that AlGaAs / GaAs is used. As in the case of (2), it is necessary to dope the AlGaN layer in order to generate carriers. At that time, in order to reduce the contact resistance with the AlGaN layer in the source region or the drain region, it is necessary to increase the doping concentration of the AlGaN layer. However, when the doping concentration is increased too much, there is a problem that the gate leakage current increases.

  Further, in the case of the MIS structure transistor that does not use the AlGaN / GaN heterostructure disclosed in Non-Patent Document 2, the channel mobility is lower than that of the 2DEG formed at the AlGaN / GaN interface. There is a problem that cannot be reduced.

  Thus, in an HFET using a nitride III-V compound semiconductor, it is very difficult to achieve a normally-off state while maintaining a high channel mobility and suppressing an increase in on-resistance.

JP 2000-277724 A

IEICE Technical Report ED2005-199-208, P35-P39 IWN2006 Technical Digest WeED1-1 p144

  SUMMARY OF THE INVENTION An object of the present invention is to provide a normally-off type field effect transistor made of a nitride III-V compound semiconductor that maintains a high channel mobility and exhibits a low on-resistance, and a method for manufacturing the same.

In order to solve the above problems, the field effect transistor of the present invention is
A first nitride-based III-V compound semiconductor layer formed on a substrate;
The second nitride III-V is formed by being stacked on the first nitride III-V compound semiconductor layer and forms a heterojunction with the first nitride III-V compound semiconductor layer. A group compound semiconductor layer;
A source electrode and a drain electrode formed on the second nitride-based III-V compound semiconductor layer;
Of the first nitride III-V compound semiconductor layer and the second nitride III-V compound semiconductor layer, at least in the gate electrode formation region of the second nitride III-V compound semiconductor layer. A plurality of recesses having a random size and shape formed selectively in a region including at least a dislocation portion; and
And a gate electrode embedded in the plurality of recesses and projecting to the second nitride III-V compound semiconductor layer.

  According to the above configuration, the gate electrode is formed by being embedded in a plurality of concave portions having a random size and shape formed in the gate electrode formation region of the nitride-based III-V compound semiconductor layer. . Accordingly, the area of the two-dimensional electron gas generated in the heterojunction portion composed of the first and second nitride III-V compound semiconductor layers can be reduced, and the overall two-dimensional electron gas density is reduced. Normally off can be achieved.

  In that case, a plurality of recesses having random sizes and shapes formed in the gate electrode formation region of the nitride-based III-V compound semiconductor layer are selectively formed in a region including at least a dislocation portion by wet etching, for example. Has been. Therefore, unlike the case where it is formed by a method involving damage due to dry etching, it is possible to suppress an increase in on-resistance without accompanying a decrease in channel mobility.

In the field effect transistor of one embodiment,
An insulating layer is formed between the gate electrode and the nitride III-V compound semiconductor layer.

  When an insulating layer is not formed between the gate electrode and the nitride III-V compound semiconductor layer, the pinch-off voltage is about 0V, so that a voltage of about 0.5V is caused due to noise or the like. It may turn on when it is input to the gate electrode and is not suitable for use in a general circuit.

  According to this embodiment, an insulating layer is formed between the gate electrode and the nitride III-V compound semiconductor layer. Accordingly, since the pinch-off voltage can be set to about +2 V to +3 V, it does not turn on even when a voltage of about 0.5 V is input to the gate electrode due to noise or the like, and an electric field suitable for use in a general circuit. An effect transistor can be obtained.

In addition, the manufacturing method of the field effect transistor of the present invention includes
Forming a first nitride-based III-V compound semiconductor layer on a substrate;
A first nitride-based III-V compound semiconductor layer is formed on the first nitride-based III-V compound semiconductor layer to form a second nitride-based III-V compound semiconductor layer. Forming a heterojunction comprising a layer and the second nitride III-V compound semiconductor layer;
Forming a source electrode and a drain electrode on the second nitride-based III-V compound semiconductor layer;
Of the first nitride III-V compound semiconductor layer and the second nitride III-V compound semiconductor layer, at least a gate electrode of the second nitride III-V compound semiconductor layer Forming a plurality of recesses having random sizes and shapes by selectively etching a region including at least a dislocation portion in the formation region;
And a step of forming a gate electrode by being embedded in the plurality of recesses and protruding onto the second nitride III-V compound semiconductor layer.

  According to the above configuration, the gate electrode is formed by being embedded in a plurality of concave portions having a random size and shape formed in the gate electrode formation region of the nitride-based III-V compound semiconductor layer. . Accordingly, the area of the two-dimensional electron gas generated in the heterojunction portion composed of the first and second nitride III-V compound semiconductor layers can be reduced, and the overall two-dimensional electron gas density is reduced. Normally off can be achieved.

  Nitride III-V compound semiconductors have more crystal defects than other III-V compound semiconductors such as GaAs. Therefore, when thinning is performed by dry etching as described in Patent Document 1, channel mobility is lowered due to damage.

  In the above configuration, the plurality of recesses for forming the gate electrode formed in the gate electrode formation region of the nitride-based III-V compound semiconductor layer are formed by selectively etching the region including at least the dislocation portion. ing. Therefore, unlike the case where it is formed by a method involving damage due to dry etching, it is possible to suppress an increase in on-resistance without accompanying a decrease in channel mobility.

In the method of manufacturing a field effect transistor according to one embodiment,
A plurality of recesses obtained by selectively etching all of the dislocation portions as the total size of the plurality of recesses formed in the gate electrode formation region of the nitride-based III-V compound semiconductor layer It is different from the total size of.

  According to this embodiment, the plurality of recesses for forming the gate electrode formed in the gate electrode formation region of the nitride III-V compound semiconductor layer are selectively etched at least in the region including the dislocation portion. Is formed by. Therefore, to adjust the pinch-off voltage, it is necessary to change the total size of the recesses in accordance with the dislocation density. That is, when the dislocation density is small, for example, to obtain the required value of the total cross-sectional area at the top of the recess, the total cross-sectional area of the recess is obtained by selectively etching all of the dislocations. Larger than the total area of the recesses to be formed. On the other hand, when the dislocation density is high, the total cross-sectional area of the concave portion is made smaller than the total area of the concave portion obtained by selectively etching all of the dislocation portions. Thus, adjustment is performed so that pinch-off can be performed at 0V.

In the method of manufacturing a field effect transistor according to one embodiment,
The selective etching for the dislocation portion is performed by wet etching using an alkaline solution.

  According to this embodiment, selective etching for the dislocation portion is performed by wet etching using an alkaline solution. Therefore, the dislocation portion can be selectively etched easily only by heating.

In the method of manufacturing a field effect transistor according to one embodiment,
The alkaline solution is a solution containing potassium hydroxide or tetramethylammonium hydroxide.

  According to this embodiment, since the alkaline solution containing potassium hydroxide or tetramethylammonium hydroxide is used, the selective etching with respect to the dislocation portion can be effectively performed.

  As is clear from the above, according to the present invention, the gate electrode is embedded in a plurality of recesses having random sizes and shapes formed in the gate electrode formation region of the nitride-based III-V compound semiconductor layer. Since it is formed, the area of the two-dimensional electron gas generated at the heterojunction portion composed of the first and second nitride III-V compound semiconductor layers can be reduced, and the overall two-dimensional electron gas density is reduced. Normally off.

  In that case, the plurality of concave portions having random sizes and shapes formed in the gate electrode formation region of the nitride-based III-V compound semiconductor layer are selectively formed in a region including at least a dislocation portion by wet etching. ing. Therefore, unlike the case where it is formed by a method involving damage due to dry etching, it is possible to suppress an increase in on-resistance without accompanying a decrease in channel mobility.

It is a longitudinal cross-sectional view in the field effect transistor of this invention. It is a figure which shows the cross section in each manufacturing process of the field effect transistor shown in FIG. It is a figure which shows the cross section in each manufacturing process following FIG. It is a longitudinal cross-sectional view of the field effect transistor different from FIG.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a longitudinal sectional view of a field effect transistor according to the present embodiment. The field effect transistor in this embodiment uses a field effect transistor having an AlGaN / GaN heterostructure having high channel mobility, and is normally off with no etching damage under the gate region and low on-resistance of the channel region. This is a field effect transistor.

In FIG. 1, the field effect transistor according to the present embodiment has a GaN low temperature buffer layer 2, a GaN channel layer 3, and an Al _0.2 Ga _0.8 N barrier layer 4 stacked in this order on a sapphire substrate 1. A source electrode 5 and a drain electrode 6 are formed on the AlGaN barrier layer 4, and a gate electrode 7 is formed between the source electrode 5 and the drain electrode 6. That is, in the present embodiment, the first nitride III-V compound semiconductor layer is composed of the GaN channel layer 3, while the second nitride III-V compound semiconductor layer is Al _0.2 Ga _0.8. The N barrier layer 4 is used.

  Here, the gate electrode 7 is formed to have a predetermined thickness on the AlGaN barrier layer 4 and has a size formed in the gate region in the AlGaN barrier layer 4 and the surface layer portion of the GaN channel layer 3. It is also formed in the recess 8 whose shape is random (hereinafter referred to as having irregularity). In this case, the concave portion 8 having the irregularity is not formed by a method involving damage as in dry etching, but is formed by a method not involving damage such as wet etching. Therefore, there is no decrease in electron mobility in the channel region.

  Reference numeral 9 denotes a two-dimensional electron gas (2DEG) region formed at a boundary portion with the AlGaN barrier layer 4 functioning as an electron supply layer in the surface layer of the GaN channel layer 3.

  2 and 3 are cross-sectional views showing the manufacturing steps of the AlGaN / GaN heterostructure field effect transistor. A method for manufacturing the present AlGaN / GaN heterostructure field effect transistor will be described below with reference to FIGS.

First, as shown in FIG. 2A, on the sapphire substrate 1, the GaN low-temperature buffer layer 2 (growth temperature 550 ° C., film thickness 20 nm) and the GaN channel layer 3 (growth temperature 1150 ° C., film thickness 2 μm). Al _0.2 Ga _0.8 N barrier layer 4 (growth temperature 1150 ° C., film thickness 20 nm) is sequentially formed by epitaxial growth.

Next, as shown in FIG. 2B, about 20 nm of SiO ₂ is deposited as an etching mask 10 on the entire surface of the wafer formed as shown in FIG. SiN _x may be deposited instead of the SiO ₂ . Here, as a method for depositing SiO ₂ or SiN _x , any of thermal CVD (Chemical Vapor Deposition), plasma CVD, or sputtering may be used. Further, as shown in FIG. 2C, after the photomask 11 is formed on the SiO ₂ layer 10, the gate etching region is patterned.

Next, as shown in FIG. 2D, the gate etching region in the SiO ₂ layer 10 is etched with buffered hydrofluoric acid. After that, as shown in FIG. 3 (e), at least the AlGaN barrier layer 4 in the gate etching region is etched for 15 minutes with an etchant heated to 100 ° C. with a 10% tetramethylammonium hydroxide (TMAH) aqueous solution. I do. In this case, the etching is not performed by uniformly etching the entire etching region, but in particular by selectively etching a dislocation portion (crystal defect portion). After that, the SiO ₂ layer 10 is removed as shown in FIG.

  As shown in FIG. 3G, after the photomask 12 is formed on the AlGaN barrier layer 4, the source region and the drain region are patterned. Thereafter, as shown in FIG. 3 (h), a metal for ohmic electrodes is deposited, lifted off, and then ohmicized by heat treatment. Thus, the source electrode 5 and the drain electrode 6 are formed. At that time, the ohmic formation forms the source region 13 from the AlGaN barrier layer 4 immediately below the source electrode 5 to the 2DEG region 9 on the surface layer of the GaN channel layer 3, while the AlGaN barrier layer immediately below the drain electrode 6. A drain region 14 is formed from 4 to the 2DEG region 9 on the surface layer of the GaN channel layer 3.

  As the metal for the ohmic electrode, Hf / Al / Hf / Au and Ti / Al / Mo / Au can be used. In addition, although the heat treatment condition varies depending on the thickness of the metal, it is set to 800 ° C./1 min in the present embodiment.

  Thereafter, as shown in FIG. 3I, a photomask 15 is formed on the entire surface of the wafer including the source electrode 5 and the drain electrode 6, and then the gate region is patterned. Then, as shown in FIG. 3 (j), after depositing a metal for forming the gate electrode, it is lifted off, and the gate electrode embedded in the concave portion 8 having irregularity selectively formed in the dislocation portion. 7 is formed. In this case, Pt, Ni, Pd, WN, or the like can be used as the metal for forming the gate electrode, but WN is used in the present embodiment. Thus, an AlGaN / GaN heterostructure field effect transistor is completed.

  The thus manufactured AlGaN / GaN heterostructure field effect transistor exhibited a normally-off operation with a pinch-off voltage of 0V.

As described above, in the present embodiment, the gate electrode 7 is filled so as to fill the recess 8 formed irregularly in the Al _0.2 Ga _0.8 N barrier layer 4 laminated on the GaN channel layer 3. Is forming. Therefore, the depletion in the present embodiment is formed by the gate electrode 7 which is three-dimensionally formed in the recess 8 rather than the depletion layer formed by the gate electrode formed planarly only on the AlGaN barrier layer 4. The layer can be expanded more three-dimensionally, and the area where the 2DEG is generated at the boundary portion between the surface layer of the GaN channel layer 3 and the AlGaN barrier layer 4 can be reduced. As a result, the overall 2DEG density can be reduced to achieve normally-off.

  In that case, as in the case of the field effect transistor disclosed in Patent Document 1, the concave portion 8 having irregularity is formed as compared with the case where the gate electrode is formed in the AlGaN electron supply layer whose gate region is thinned in a plane. By forming the gate electrode 7 therein, the total cross-sectional area of the recess 8 in the surface layer of the AlGaN barrier layer 4 can be adjusted so that the pinch-off can be performed even when the gate voltage is 0V. Therefore, it is possible to achieve both the reduction of the 2DEG density and the maintenance of channel mobility.

  That is, in the present embodiment, the total cross-sectional area is used as an example of “size” in the claims.

  By the way, the nitride III-V compound semiconductor has more crystal defects than other III-V compound semiconductors such as GaAs. Further, in the thinning by dry etching as described in the above-mentioned Patent Document 1, the channel mobility is lowered due to damage. Therefore, in the present embodiment, by selectively wet-etching the crystal defects in the AlGaN barrier layer 4 and the GaN channel layer 3, the recesses 8 having irregularity are formed without causing damage, and the channel The decrease in mobility is suppressed to prevent an increase in on-resistance in the channel region.

  At that time, as described above, the total cross-sectional area of the recess 8 in the surface layer of the AlGaN barrier layer 4 is adjusted so that the pinch-off can be performed even when the gate voltage is 0V. If the magnitude of 8 is not changed, the pinch-off voltage cannot be adjusted. That is, when the dislocation density is small, the total cross-sectional area of the concave portion 8 is increased. On the other hand, when the dislocation density is large, the total cross-sectional area of the concave portion 8 is decreased and adjusted so that pinch-off can be performed at 0V. is there. Therefore, in the present embodiment, when the dislocation density is too small to obtain the necessary value of the total cross-sectional area in the concave portion 8, that is, the total of the concave portions obtained by selectively etching all of the dislocation portions. When the cross-sectional area is smaller than the total area of the target recess 8, the total cross-sectional area of the recess 8 is increased by adjusting the etching conditions such as the concentration, temperature or etching time of the TMAH aqueous solution. . On the other hand, when the dislocation density is too high, that is, when the total cross-sectional area of the recess obtained by selectively etching all of the dislocation portions is larger than the total area of the target recess 8, the recess 8 The total cross-sectional area is reduced. Therefore, in the present embodiment, the tip of the recess 8 reaches the surface layer portion of the GaN channel layer 3, but this is not always necessary, and it may be formed only in the AlGaN barrier layer 4. The point is that the recess 8 is formed so that the depletion layer formed by the gate electrode 7 covers the 2 DEG region 9 and can be pinched off at 0V.

  In this embodiment, the selective etching of the region including the dislocation portion with respect to the AlGaN barrier layer 4 is performed using the TMAH aqueous solution as an etchant. However, the present invention is not limited to this. An alkaline solution such as potassium hydroxide (KOH) may be used.

Second Embodiment FIG. 4 is a longitudinal sectional view of a field effect transistor according to the present embodiment. The field effect transistor in the present embodiment is a field effect transistor having an AlGaN / GaN heterostructure using a silicon substrate.

4, the field effect transistor according to the present embodiment includes an initial growth layer 22 made of AlN / AlGaN, a buffer layer 23 made of an AlN / GaN multilayer film, a GaN channel layer 24, and a silicon (Si) substrate 21. The Al _0.2 Ga _0.8 N barrier layer 25 is laminated in this order. A source electrode 26 and a drain electrode 27 are formed on the AlGaN barrier layer 25, and a gate electrode 28 is formed between the source electrode 26 and the drain electrode 27.

  As in the case of the first embodiment, the gate electrode 28 is formed on the AlGaN barrier layer 25 with a predetermined thickness, and the gate region in the AlGaN barrier layer 25 has irregularities. It is also formed in the formed recess 29. Reference numeral 30 denotes a two-dimensional electron gas (2DEG) region formed at a boundary portion with the AlGaN barrier layer 25 functioning as an electron supply layer in the surface layer of the GaN channel layer 24.

  The manufacturing process of the AlGaN / GaN heterostructure field effect transistor is substantially the same as that in the first embodiment. However, the buffer layer 23 composed of an AlN / GaN multilayer film is formed by alternately repeating a plurality of AlN layers and GaN layers. The present embodiment is greatly different from the first embodiment in the condition for etching the AlGaN barrier layer 25.

  Compared to the AlGaN layer on the sapphire substrate, the AlGaN layer on the silicon substrate has a dislocation density that is about one to two digits higher. Therefore, the total cross-sectional area of the recesses 29 in the surface layer of the AlGaN barrier layer 25 to be set must be smaller than when a sapphire substrate is used. Therefore, when forming the same recess as in the case of the first embodiment, the total cross-sectional area has a gentler etching condition in the present embodiment than in the case of the first embodiment. It is necessary to perform etching. In this embodiment, etching was performed for 10 minutes with an etchant in which a 5% TMAH aqueous solution was heated to 50 ° C.

  The AlGaN / GaN heterostructure field effect transistor formed as described above exhibited a normally-off operation with a pinch-off voltage of 0V.

Third Embodiment The field effect transistor according to the present embodiment is the same as the gate electrode and the nitride system in the AlGaN / GaN heterostructure field effect transistor according to the first embodiment or the second embodiment. This is an AlGaN / GaN heterostructure field effect transistor in which an insulator layer is formed between the III-V compound semiconductor layer.

  As in the case of the first embodiment and the second embodiment, in the state where no insulator is formed between the gate electrode and the nitride III-V compound semiconductor layer, the pinch-off voltage is Is about 0V. Therefore, it may turn on when a voltage of about 0.5 V is input to the gate electrode due to noise or the like, and is not suitable for use in a general circuit. Therefore, in order to set the pinch-off voltage to about + 2V to + 3V, it is preferable to form an insulator between the gate electrode and the nitride III-V compound semiconductor.

Therefore, in this embodiment, before forming the gate electrode, that is, for example, when applied to the first embodiment, a patterning process of the gate region in the photomask shown in FIG. A step of depositing a gate insulating film made of SiO ₂ having a thickness of 10 nm is provided between the step of forming the gate electrode shown in FIG. Thereafter, a gate electrode is deposited to manufacture a MIS field effect transistor having an AlGaN / GaN heterostructure. The process conditions other than the process of depositing the gate insulating film are the same as those in the first embodiment. The same applies to the case where the present embodiment is applied to the second embodiment.

  As described above, according to the present embodiment, the pinch-off voltage is increased to about +3 V by forming a gate insulating film between the gate electrode and the nitride III-V compound semiconductor layer. Therefore, a more desirable normally-off operation can be realized.

1 ... sapphire substrate,
2 ... GaN low temperature buffer layer,
3, 24 ... GaN channel layer,
4,25 ... Al _0.2 Ga _0.8 N barrier layer,
5, 26 ... source electrode,
6, 27 ... drain electrode,
7, 28 ... gate electrode,
8,29 ... concave,
9, 30 ... 2 DEG region,
10 ... Etching mask,
11, 12, 15 ... Photomask,
13 ... source region,
14 ... drain region,
21 ... Silicon substrate,
22 ... AlN / AlGaN initial growth layer,
23: AlN / GaN multilayer buffer layer.

Claims (6)

A first nitride-based III-V compound semiconductor layer formed on a substrate;
The second nitride III-V is formed by being stacked on the first nitride III-V compound semiconductor layer and forms a heterojunction with the first nitride III-V compound semiconductor layer. A group compound semiconductor layer;
A source electrode and a drain electrode formed on the second nitride-based III-V compound semiconductor layer;
Of the first nitride III-V compound semiconductor layer and the second nitride III-V compound semiconductor layer, at least in the gate electrode formation region of the second nitride III-V compound semiconductor layer. A plurality of recesses having a random size and shape formed selectively in a region including at least a dislocation portion; and
A field effect transistor comprising: a gate electrode embedded in the plurality of recesses and formed so as to protrude onto the second nitride III-V compound semiconductor layer. The field effect transistor according to claim 1,
A field effect transistor, wherein an insulating layer is formed between the gate electrode and the nitride III-V compound semiconductor layer. Forming a first nitride-based III-V compound semiconductor layer on a substrate;
A first nitride-based III-V compound semiconductor layer is formed on the first nitride-based III-V compound semiconductor layer to form a second nitride-based III-V compound semiconductor layer. Forming a heterojunction comprising a layer and the second nitride III-V compound semiconductor layer;
Forming a source electrode and a drain electrode on the second nitride-based III-V compound semiconductor layer;
Of the first nitride III-V compound semiconductor layer and the second nitride III-V compound semiconductor layer, at least a gate electrode of the second nitride III-V compound semiconductor layer Forming a plurality of recesses having random sizes and shapes by selectively etching a region including at least a dislocation portion in the formation region;
And a step of forming a gate electrode by being embedded in the plurality of recesses and protruding onto the second nitride III-V compound semiconductor layer. Production method. In the manufacturing method of the field effect transistor according to claim 3,
A plurality of recesses obtained by selectively etching all of the dislocation portions as the total size of the plurality of recesses formed in the gate electrode formation region of the nitride-based III-V compound semiconductor layer A method for producing a field-effect transistor, characterized in that the total value is different from the total value of the field effect transistors. In the manufacturing method of the field effect transistor according to claim 3 or claim 4,
The method of manufacturing a field effect transistor, wherein the selective etching for the region including at least the dislocation portion is performed by wet etching using an alkaline solution. In the manufacturing method of the field effect transistor according to claim 5,
The method for producing a field effect transistor, wherein the alkaline solution is a solution containing potassium hydroxide or tetramethylammonium hydroxide.

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