JP5495257B2 - Group III nitride field effect transistor and method of manufacturing the same - Google Patents

Description

  The present invention relates to a group III nitride field effect transistor and a manufacturing method thereof, and more particularly to a group III nitride field effect transistor using a nitride semiconductor and a manufacturing method thereof.

  Since nitride-based semiconductors have high values of breakdown field strength, thermal conductivity, and saturation electron velocity, group III nitride-based field effect transistors using nitride-based semiconductors are small and It is characterized by low on-resistance and excellent pressure resistance. Group III nitride field effect transistors having such characteristics are expected to be applied to high-efficiency power conversion devices and high-frequency power devices.

  The group III nitride field effect transistor is formed by laminating a GaN layer and an AlGaN layer. By laminating the GaN layer and the AlGaN layer in this manner, spontaneous polarization and piezo polarization occur between these two layers. Due to the polarization electric field generated due to these polarizations, a two-dimensional electron gas (2-DEG) is formed at the heterointerface, and a high-concentration sheet carrier is generated. As a result, a normally-on group III nitride field effect transistor having a low on-resistance and excellent pressure resistance can be manufactured.

  On the other hand, a normally-off group III nitride field effect transistor having a high threshold voltage is desired from the viewpoint of suppressing overcurrent and simplifying the circuit configuration. Patent Document 1 discloses a technique for imparting a normally-off operation to a group III nitride field effect transistor.

  In Patent Literature 1, a normally-off operation is obtained by recessing an electron transit layer and an electron supply layer and growing a p-type region in the recessed region.

JP 2009-071270 A

  In Patent Document 1, when a positive voltage is applied to the gate electrode, the inversion layer carrier is formed under the gate electrode, whereby the inversion layer carrier and the two-dimensional electron gas are connected to form a group III nitride. The physical field effect transistor is turned on.

  However, since the side wall of the recess region and the bottom of the gate electrode (that is, the contact surface between the gate electrode and the insulating layer) are perpendicular, the electric field from the gate electrode is not uniformly applied to the side wall of the recess region. The further away from the electrode, the weaker the electric field from the gate electrode. Therefore, there is a problem in that the number of inversion layer carriers decreases and the on-resistance increases as the distance from the gate electrode increases in the sidewall of the recess region.

  The present invention has been made in view of such a current situation, and an object thereof is to provide a group III nitride field effect transistor having a high electron mobility in a recess region and a low on-resistance, and a method for manufacturing the same. To do.

The group III nitride field effect transistor of the present invention includes a base semiconductor layer, a nitride semiconductor multilayer body in which a first nitride semiconductor layer and a second nitride semiconductor layer are sequentially stacked on the base semiconductor layer, A source electrode and a drain electrode that are in contact with the top surface of the nitride semiconductor multilayer body, and a portion of the first nitride semiconductor layer and the second nitride semiconductor layer in the nitride semiconductor multilayer body between the source electrode and the drain electrode are formed. A recess region that is not a region, a nitride semiconductor film formed on the recess region, an upper surface of the nitride semiconductor film, an inner wall surface of the recess region, and an insulating film formed on the upper surface of the second nitride semiconductor layer And a gate electrode formed on the insulating film, the second nitride semiconductor layer has a wider band gap than the first nitride semiconductor layer, and the upper surface of the nitride semiconductor film 1 nitride semiconductor layer Rather lower than the upper surface, the first nitride semiconductor layer is GaN, the nitride semiconductor film is characterized in that it consists of _{In x Ga 1-x N (} 0 <x ≦ 1). Here, the second nitride semiconductor layer preferably has a three-layer structure in which GaN / AlGaN / AlN are sequentially stacked from the source electrode and drain electrode sides.

The nitride semiconductor film is preferably made of a p-type nitride semiconductor or an i-type nitride semiconductor, and the hole concentration contained in the nitride semiconductor film is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

The thickness of the nitride compound semiconductor layer is preferably 30nm or more.

  The nitride semiconductor multilayer body preferably has a base nitride semiconductor layer on the surface of the first nitride semiconductor layer opposite to the surface in contact with the second nitride semiconductor layer.

  The recess region is preferably manufactured by a dry etching process, and the nitride semiconductor film is preferably formed on the inner surface of the recess region by using a regrowth method.

The method of manufacturing a group III nitride field effect transistor according to the present invention includes a step of forming a first nitride semiconductor layer and a second nitride semiconductor layer on a base semiconductor layer, and a part of the second nitride semiconductor layer. Forming a selective growth mask thereon, and removing the entire second nitride semiconductor layer and the upper portion of the first nitride semiconductor layer in the region where the selective growth mask is not formed, to form the first nitride semiconductor layer Forming a recess region by exposing a part of the substrate, forming a nitride semiconductor film on the recess region, removing a selective growth mask on the second nitride semiconductor layer, and nitride semiconductor the upper surface of the membrane, seen including a step of forming an inner wall surface, and an insulating film on the upper surface of the second nitride semiconductor layer of the recessed region, a first nitride semiconductor layer is GaN, the second nitride semiconductor layer first Forbidden band width than 1 nitride semiconductor layer A There nitride semiconductor layer, nitride semiconductor film is characterized in that it consists of _{In x Ga 1-x N (} 0 <x ≦ 1). The second nitride semiconductor layer preferably has a three-layer structure in which GaN / AlGaN / AlN are sequentially stacked from the source electrode and drain electrode sides.

  According to the present invention, it is possible to provide a group III nitride field effect transistor having a high electron mobility in a recess region and a low on-resistance, and a method for manufacturing the same.

It is typical sectional drawing which shows an example of the group III nitride field effect transistor of this invention. It is typical sectional drawing which shows the state after forming the nitride semiconductor laminated body on a board | substrate. It is typical sectional drawing which shows the state after forming the selective growth mask on the nitride semiconductor laminated body. FIG. 6 is a schematic cross-sectional view showing a state after forming a recess region in the nitride semiconductor multilayer body. FIG. 6 is a schematic cross-sectional view showing a state after a nitride semiconductor film is formed on the inner surface of the recess region. FIG. 6 is a schematic cross-sectional view showing a state after an insulating film is formed on the upper surface of the nitride semiconductor film, the inner wall surface of the recess region, and the upper surface of the second nitride semiconductor layer. It is typical sectional drawing which shows the state after forming a contact region in an insulating film. It is typical sectional drawing which shows the state after forming a source electrode and a drain electrode. 10 is a schematic cross-sectional view showing a part of the manufacturing process of the group III nitride field-effect transistor of Comparative Example 1. FIG. 6 is a schematic cross-sectional view showing a group III nitride field effect transistor of Comparative Example 1. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The configurations shown in the drawings and the following description are merely examples, and the scope of the present invention is not limited to those shown in the drawings and the following description. In the drawings of the present application, the same reference numerals represent the same or corresponding parts. In the drawings of the present application, the dimensional relationships such as length, width, and thickness are appropriately changed for clarity and simplification of the drawings and do not represent actual dimensional relationships.

(Embodiment 1)
<Group III nitride field effect transistor>
FIG. 1 is a schematic cross-sectional view of a group III nitride field effect transistor of the present embodiment. In the group III nitride field effect transistor of the present embodiment, a base semiconductor layer 2 is formed on a substrate 1 as shown in FIG. Then, the base nitride semiconductor layer 11, the first nitride semiconductor layer 12, and the second nitride semiconductor layers 13a and 13b are stacked in this order on the base semiconductor layer 2. The base nitride semiconductor layer 11, the first nitride semiconductor layer 12, and the second nitride semiconductor layers 13a and 13b are referred to as a nitride semiconductor stacked body 100, and the first nitride semiconductor layer 12 and the first nitride semiconductor layer 12 The interfaces with the two nitride semiconductor layers 13a and 13b are referred to as heterojunction interfaces 16a and 16b.

  Although FIG. 1 shows the case where the base semiconductor layer 2 and the base nitride semiconductor layer 11 are formed, the base semiconductor layer 2 and the base nitride semiconductor layer 11 are not formed even if the base semiconductor layer 2 and the base nitride semiconductor layer 11 are not formed. It does not depart from the scope.

  Here, since the forbidden band width of the second nitride semiconductor layers 13a and 13b is wider than the forbidden band width of the first nitride semiconductor layer 12, the first nitride semiconductor layer 12 and the second nitride semiconductor layer 13a At the heterojunction interface 16a, a two-dimensional electron gas 14a is generated on the first nitride semiconductor layer 12 side by positive polarization charges. Similarly, at the heterojunction interface 16b between the first nitride semiconductor layer 12 and the second nitride semiconductor layer 13b, a two-dimensional electron gas 14b is generated on the first nitride semiconductor layer 12 side due to positive polarization charges.

  Further, the source electrode 6 is provided so as to be in contact with the upper surface of the second nitride semiconductor layer 13a. On the other hand, the drain electrode 7 is provided in contact with the upper surface of the second nitride semiconductor layer 13b. Here, the source electrode 6 and the drain electrode 7 are in ohmic contact with the second nitride semiconductor layers 13a and 13b.

  A part of the nitride semiconductor stacked body 100 between the source electrode 6 and the drain electrode 7 has a region where the first nitride semiconductor layer 12 and the second nitride semiconductor layers 13a and 13b are not formed. This area is referred to as a recess area 20. A nitride semiconductor film 23 is formed on the first nitride semiconductor layer 12 in the recess region 20. Then, the insulating film 9 is formed on the upper surface of the nitride semiconductor film 23, the inner wall surface of the recess region 20, and the upper surfaces of the second nitride semiconductor layers 13a and 13b. Here, the interface between the nitride semiconductor film 23 and the insulating film 9 (that is, the bottom surface of the recess region 20) is referred to as a recess interface 20c. Then, the gate electrode 8 is formed on the insulating film 9 in the recess region 20.

  The group III nitride field effect transistor of the present embodiment is characterized in that the upper surface of the nitride semiconductor film 23 is positioned lower than the upper surface of the first nitride semiconductor layer 12. As described above, since the lower surface of the nitride semiconductor film 23 is lower than the upper surface of the first nitride semiconductor layer 12, a decrease in mobility in the recess region 20 is suppressed, so that a group III nitride field effect transistor is obtained. The on-resistance can be made difficult to increase. In the following, the operation of the group III nitride field effect transistor of the present embodiment will be described.

<Operation of Group III Nitride Field Effect Transistor>
The group III nitride field effect transistor of the present embodiment is a normally-off type field effect transistor. That is, in the group III nitride field effect transistor of the present embodiment, the two-dimensional electron gas 14 a on the source electrode 6 side and the two-dimensional electron gas 14 b on the drain electrode 7 side are separated by the recess region 20. For this reason, in a state where no voltage is applied to the gate electrode 8 or in a state where 0 V is applied, even if a voltage is applied between the source electrode 6 and the drain electrode 7, it is difficult for current to flow through the channel.

  On the other hand, when a positive voltage is applied to the gate electrode 8, electrons are accumulated in the first nitride semiconductor layer 12 in contact with the insulating film 9. The two-dimensional electron gas 14a on the source electrode 6 side and the two-dimensional electron gas 14b on the drain electrode 7 side are electrically connected by the electrons. When a voltage is applied to the source electrode 6 and the drain electrode 7 in this state, a current flows through the channel and an on operation occurs.

  The group III nitride field effect transistor of the present embodiment has a reduced resistance at the recess interface 20c when turned on, and can be turned on with low loss. This is due to an increase in mobility and an increase in inversion layer electron concentration at the recess interface 20c.

<Board>
In the present embodiment, the substrate 1 may be a conventionally known substrate as long as it is a substrate used for a field effect transistor. Examples of such a material for the substrate 1 include Si, GaN, SiC, AlN, GaAs, and ZnO.

<Underlying nitride semiconductor layer>
In the group III nitride field effect transistor of the present embodiment, the nitride semiconductor multilayer body 100 is on the surface of the first nitride semiconductor layer 12 opposite to the surface in contact with the second nitride semiconductor layers 13a and 13b. The base nitride semiconductor layer 11 is preferably included. That is, it is preferable to form the underlying nitride semiconductor layer 11 between the substrate 1 and the first nitride semiconductor layer 12. As such an underlying nitride semiconductor layer 11, it is preferable to use an undoped or doped nitride semiconductor such as GaN, AlGaN, InGaN, AlInN, AlGaInN, and Al _1-x Ga _x N having a higher barrier than GaN. More preferably (0 <x ≦ 1).

The underlying nitride semiconductor layer 11 may be doped with impurities so as to be a p-type nitride semiconductor or an i-type nitride semiconductor. Here, when AlGaN is used as the material used for the underlying nitride semiconductor layer 11, the ratio of the number of Al atoms to the number of Ga atoms is not particularly limited and may be any ratio, for example, undoped Al. _0.05 Ga _0.95 N can be used.

  In the present embodiment, base nitride semiconductor layer 11 preferably has a larger band gap than first nitride semiconductor layer 12. By providing the base nitride semiconductor layer 11 having a larger band gap than the first nitride semiconductor layer 12 in this way, negative polarization is caused at the heterojunction interface between the first nitride semiconductor layer 12 and the base nitride semiconductor layer 11. Electric charge can be generated. And since the conduction band in the heterojunction interface is discontinuous, it is possible to form a barrier against electrons.

  As a result, even when a high bias voltage is applied between the source electrode 6 and the drain electrode 7 during the off operation, a path through which electrons in a region away from the heterojunction interfaces 16a and 16b flow can be blocked. Thus, the leakage current flowing between the source electrode 6 and the drain electrode 7 can be suppressed.

<Underlying semiconductor layer>
In the present embodiment, it is preferable to provide base semiconductor layer 2 between substrate 1 and base nitride semiconductor layer 11. By providing the base semiconductor layer 2 in this manner, distortion between the crystal lattice of the substrate 1 and the crystal lattice of the base nitride semiconductor layer 11 can be relaxed. Note that if the substrate 1 has a role equivalent to that of the base semiconductor layer, the base semiconductor layer may not be formed by regarding the substrate 1 as the base semiconductor layer. That is, a structure in which the underlying nitride semiconductor layer 11 is directly laminated on the substrate 1 is also included in the scope of the present invention.

  Such a base semiconductor layer 2 may be either a single layer or a plurality of layers. When the underlying semiconductor layer 2 is a single layer, for example, AlN, GaN, AlGaN or the like can be used as the material. On the other hand, when the base semiconductor layer 2 includes a plurality of layers, an AlN / GaN multilayer, an AlGaN / GaN multilayer, or the like can be used for the base semiconductor layer 2. The underlying semiconductor layer 2 is preferably a multiple layer in which a thick undoped GaN layer is stacked on a thin undoped AlN layer. Note that the expression “GaN / AlN” indicates that the upper surface is GaN and the lower surface is AlN.

<Nitride semiconductor film>
In the group III nitride field effect transistor of the present embodiment, the nitride semiconductor film 23 is formed on the first nitride semiconductor layer 12 in the recess region 20. By forming the nitride semiconductor film 23 in this way, the resistance of the recess interface 20c at the time of ON is reduced, and an ON operation with a small loss becomes possible. As such a nitride semiconductor film 23, it is preferable to use an undoped or doped nitride semiconductor such as GaN, AlGaN, InGaN, AlInN, and AlGaInN, and In _1-x Ga _x N (0 <x ≦ 1). It is more preferable that

  Further, it is more preferable to dope impurities so that the nitride semiconductor film 23 becomes either a p-type nitride semiconductor or an i-type nitride semiconductor. Thus, by doping the nitride semiconductor film 23 with impurities, it is possible to control to a desired threshold voltage. From the viewpoint of increasing the threshold voltage of the field effect transistor, the nitride semiconductor film 23 is preferably a p-type nitride semiconductor.

  In addition, by doping the nitride semiconductor film 23 with p-type impurities, the depletion layer extends above and below the nitride semiconductor stacked body 100 during the off operation, thereby improving the pressure resistance of the group III nitride field effect transistor. Can be made.

  Here, as the p-type impurity for doping the nitride semiconductor film 23, any dopant can be used as long as it is an impurity that can make the nitride semiconductor p-type or i-type. For example, Mg, Zn , C, Fe, or the like can be used.

The hole concentration contained in the nitride semiconductor film 23 is preferably 1 × 10 ¹⁷ cm ⁻³ or less. By setting such a hole concentration, the threshold voltage can be controlled to a desired value, and the pressure resistance during the off operation of the group III nitride field effect transistor can be improved. In addition, the inclusion of holes at the above concentration in the nitride semiconductor film 23 can suppress the scattering of carriers traveling on the recess interface 20c as much as possible.

  The nitride semiconductor film 23 preferably has a thickness of 30 nm or more. This is because when the thickness of the nitride semiconductor film 23 is 30 nm or more, the movement of carriers formed at the interface between the nitride semiconductor film 23 and the insulating film 9 causes the nitride semiconductor film 23 and the first nitride semiconductor to move. This is because it is less affected by the interface roughness with the layer 12 and the carrier mobility is further improved.

  Such a nitride semiconductor film 23 is preferably formed by using a regrowth method on the inner surface of the recess region after the recess region 20 is formed by dry etching. By forming the nitride semiconductor film 23 in this way, the surface of the first nitride semiconductor layer 12 roughened by dry etching can be covered with the nitride semiconductor film 23. The interface roughness value between the nitride semiconductor film 23 and the insulating film 9 is preferably approximately the same as that of the heterojunction interfaces 16a and 16b.

<First nitride semiconductor layer>
In the present embodiment, the first nitride semiconductor layer 12 preferably has the same forbidden band width as the nitride semiconductor film 23. When the nitride semiconductor film 23 is made of GaN, the first nitride semiconductor layer 12 is also It is preferably made of GaN. Such first nitride semiconductor layer 12 may be either a single layer or a multilayer nitride semiconductor. When the first nitride semiconductor layer 12 is made of a single layer nitride semiconductor, undoped AlGaN, doped AlGaN, AlInN, AlGaInN, or the like may be used.

On the other hand, when the first nitride semiconductor layer 12 is formed of a multilayer nitride semiconductor, a multiple AlGaN layer including a plurality of AlGaN layers having different Al composition ratios and doping concentrations, GaN / Al _0.25 Ga _0.75 N / AlN, GaN / AlGaN InGaN / AlGaN, InGaN / AlGaN / AlN, or the like may be used. It should be noted that other doped nitride semiconductors can be used for each layer constituting the multilayer nitride semiconductor.

<Second nitride semiconductor layer>
In the present embodiment, the second nitride semiconductor layers 13 a and 13 b are barrier layers having a forbidden band width wider than that of the first nitride semiconductor layer 12. Such second nitride semiconductor layers 13a and 13b are preferably multi-nitride semiconductor layers, and the material of each layer constituting the multi-nitride semiconductor layer is undoped such as GaN, AlGaN, InGaN, AlInN, AlGaInN or the like. Alternatively, a doped nitride semiconductor or the like can be used. As the second nitride semiconductor layers 13a and 13b, for example, those containing undoped GaN / Al _0.25 Ga _0.75 N / AlN in a thickness of 1 nm / 22 nm / 1 nm, respectively, from the top can be used.

<Source electrode, drain electrode>
In the present embodiment, the source electrode 6 and the drain electrode 7 are preferably formed of a single layer or a multilayer metal layer. Examples of the electrode material used for the source electrode 6 and the drain electrode 7 include Ti / Al, Ni / Au, Ti / Au, Pt / Au, Ni / Au, W, WN _x , and WSi _x .

<Gate electrode>
In the present embodiment, the gate electrode 8 is an electrode that controls the concentration of electrons at the recess interface 20c where the insulating film 9 and the underlying nitride semiconductor layer 11 are in contact. By adjusting the bias voltage applied to the gate electrode 8, the electron concentration at the recess interface 20c can be controlled, and the channel formation can be controlled. Examples of the metal material used for the gate electrode 8 include Ti / Al, Ni / Au, Ti / Au, Pt / Au, Ni / Au, W, WN _x , and WSi _x .

<Insulating film>
In the present embodiment, insulating film 9 is formed on the upper surface of nitride semiconductor film 23, the inner wall surface of recess region 20, and the upper surfaces of second nitride semiconductor layers 13a and 13b. The insulating film 9 formed in this way is not limited to a single layer film, but may be a multilayer film. That is, when the insulating film 9 is formed of a single layer film, SiO ₂ , SiN _x , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , TiO ₂ , TaO _x , MgO, Ga ₂ O ₃ , MgF ₂ or the like may be used. it can. By using SiO ₂ as the insulating film 9, the insulating film 9 is easily stabilized. Further, by using SiN _x as the insulating film 9, the electron mobility at the recess interface 20c can be increased.

When the insulating film 9 is composed of a plurality of films, a structure such as SiN _x / SiO ₂ , SiO ₂ / SiN _x , SiN _x / SiO ₂ / SiN _x can be used. Note that the expression “SiO ₂ / SiN _x ” indicates that the upper surface is SiO ₂ and the lower surface is SiN _x . By using a plurality film made of SiO ₂ / SiN _x as the insulating film 9, easily suppressed collapse phenomenon by SiN _x in contact with the recess surface 20c, it is possible to obtain a higher electron mobility, by SiO ₂ thereon Stability can be obtained.

<Recess area>
In the present embodiment, recess region 20 is preferably formed on nitride semiconductor multilayer body 100 by dry etching. A nitride semiconductor film 23 is formed on the recess region 20 thus fabricated. In the present embodiment, the side surface of the recess region 20 is formed perpendicular to the surface of the first nitride semiconductor layer 12. However, the present invention is not limited to such a form. The side surfaces of the region 20 may be inclined with respect to the surfaces of the underlying nitride semiconductor layer 11 and the first nitride semiconductor layer 12.

(Production method)
The outline of the manufacturing method of the group III nitride field effect transistor of the present embodiment will be described below. The group III nitride field effect transistor according to the present embodiment includes a step of forming a first nitride semiconductor layer 12 and a second nitride semiconductor layer 13 on the underlying semiconductor layer 2 (FIG. 2), and a second nitridation. A step of forming the selective growth mask 50 on a part of the physical semiconductor layer 13 (FIG. 3), the second nitride semiconductor layers 13a and 13b in the region where the selective growth mask 50 is not formed, and the first Removing the upper portion of the nitride semiconductor layer 12, exposing a part of the first nitride semiconductor layer 12 to form a recess region (FIG. 4), and forming the nitride semiconductor film 23 on the recess region 20; (FIG. 5), removing the selective growth mask 50 on the second nitride semiconductor layers 13a and 13b, the upper surface of the nitride semiconductor film 23, the inner wall surface of the recess region 20, and the second nitride semiconductor layer Insulating film 9 on the upper surface of 13a Forming a (FIG. 6) can be produced by including in this order. Each of these steps will be described in detail below.

  FIG. 2 is a schematic cross-sectional view showing a state after the nitride semiconductor layer stack is formed on the substrate. In the present embodiment, as shown in FIG. 2, a base semiconductor layer 2 and a nitride semiconductor laminate are formed on a substrate 1 by using a metal organic chemical vapor deposition (MOCVD) method. 100 are stacked in this order. Here, the nitride semiconductor multilayer body 100 is obtained by laminating a base nitride semiconductor layer 11, a first nitride semiconductor layer 12, and a second nitride semiconductor layer 13 in this order.

Here, the nitride semiconductor multilayer body 100 is formed by, for example, MOCVD using trimethylgallium (TMG), trimethylammonium (TMA), ammonia (NH ₃ ), molecular beam epitaxy (MBE), It can be formed by a halide vapor phase epitaxy (HVPE) method or the like.

  FIG. 3 is a schematic cross-sectional view showing the substrate after a selective growth mask and a resist are formed on part of the second nitride semiconductor layer 13. Next, a protective film is formed on the second nitride semiconductor layer 13 using the CVD method. Then, after forming the resist 51 on the necessary portion of the protective film, the unnecessary portion of the protective film is removed by using the photolithography technique, thereby forming the selective growth mask 50 as shown in FIG. . In this way, the selective growth mask 50 and the resist 51 are formed on the second nitride semiconductor layer 13. The resist 51 is preferably left without being peeled off. Note that the selective growth mask 50 is not limited to being formed using the CVD method, and may be formed using a sputtering method or the like.

Here, as a material used for the selective growth mask 50, SiO ₂ , SiN _x or the like can be used, or a material having a two-layer structure of SiO ₂ / SiN _x may be used. Here, when SiO ₂ and / or SiN _x is used as the selective growth mask 50, an unnecessary portion as a protective film can be easily removed by etching with hydrofluoric acid diluted with hydrofluoric acid or ammonium fluoride.

  FIG. 4 is a schematic cross-sectional view showing a state after the recess region is formed in the nitride semiconductor multilayer body. Next, as shown in FIG. 4, by removing a part of the nitride semiconductor stacked body 100 on the second nitride semiconductor layer 13 where the selective growth mask 50 is not formed by etching, A recess region 20 is formed in the nitride semiconductor multilayer body 100.

  In the present embodiment, the recess region 20 is formed by removing all of the second nitride semiconductor layer 13 and the upper portion of the first nitride semiconductor layer 12 by etching. Here, the thickness of the first nitride semiconductor layer 12 removed by etching is T1. T1 may be any thickness as long as it is equal to or less than the thickness of the first nitride semiconductor layer 12. Then, after the recess region 20 is formed, the resist 51 is removed.

  FIG. 5 is a schematic cross-sectional view showing a state after the nitride semiconductor film is formed on the upper surface of the first nitride semiconductor layer in the recess region. In the present embodiment, as shown in FIG. 5, nitridation semiconductor film 23 is formed by performing regrowth using MOCVD on the upper surface of first nitride semiconductor layer 12 located on the inner surface of recess region 20. Form. Here, the nitride semiconductor film 23 having a thickness T2 is formed so that the upper surface of the nitride semiconductor film 23 does not exceed the upper surface of the first nitride semiconductor layer 12. That is, the relationship between the etching depth T1 of the first nitride semiconductor layer 12 and the thickness T2 of the nitride semiconductor film 23 may be in a range satisfying 0 <T2 <T1.

  After forming the nitride semiconductor film 23 as described above, the selective growth mask 50 is removed. Next, the upper surface of the nitride semiconductor film 23, the inner wall surface of the recess region 20, and the upper surfaces of the second nitride semiconductor layers 13a and 13b are washed with sulfuric acid / hydrogen peroxide solution, and further washed with hydrochloric acid / hydrogen peroxide solution. To do.

  FIG. 6 is a schematic cross-sectional view showing a state after an insulating film is formed on the upper surface of the nitride semiconductor film, the inner wall surface of the recess region, and the upper surface of the second nitride semiconductor layer. In the present embodiment, as shown in FIG. 6, insulating film 9 is formed on the inner surface of recess region 20 and the upper surfaces of second nitride semiconductor layers 13a and 13b using a CVD method.

  When the insulating film 9 is formed in this way, the interface between the first nitride semiconductor layer 12 and the insulating film 9 is referred to as a recess interface 20c. Since the recess interface 20c is not damaged by dry etching, high mobility at the recess interface 20c can be obtained, and the resistance of the recess interface 20c at the time of ON can be reduced.

  FIG. 7 is a schematic cross-sectional view showing a state after the contact region is formed in the insulating film. As shown in FIG. 7, the portion of the insulating film 9 on the upper surface of the second nitride semiconductor layers 13a and 13b where the source electrode and the drain electrode are formed is removed by photolithography to form a contact region 25. To do. Then, by performing annealing at 400 ° C. to 1100 ° C. in a nitrogen atmosphere, the interface state of the surface where insulating film 9 and nitride semiconductor multilayer body 100 are in contact can be reduced.

  FIG. 8 is a schematic cross-sectional view showing a state after forming the source electrode and the drain electrode. After the above annealing, as shown in FIG. 8, the source region is removed from the contact region from which the insulating film 9 on the second nitride semiconductor layers 13a and 13b is removed by using the photolithography technique and the EB evaporation method. An electrode 6 and a drain electrode 7 are formed.

  Then, the source electrode 6 and the drain electrode 7 and the channel are brought into ohmic contact by alloying by heat treatment. The method of obtaining the ohmic contact is not limited to the method of alloying by heat treatment, but a method of forming an ohmic contact by a tunnel current mechanism, an n-type impurity such as Si in the contact region 25 by ion implantation, or the like. For example, a method of forming the source electrode 6 and the drain electrode 7 in the contact region 25 after doping at a high concentration can be used.

  Next, the gate electrode 8 made of Ni / Au is formed on the insulating film by using a photolithography technique and an EB vapor deposition method. Through the above steps, as shown in FIG. 1, the group III nitride field effect transistor of the present embodiment can be manufactured.

  In the conventional group III nitride field effect transistor, the second nitride semiconductor layer and part of the first nitride semiconductor layer are removed by dry etching to form a recess region. For this reason, the first nitride semiconductor layer at the recess interface may be damaged by dry etching, and the surface roughness of the first nitride semiconductor layer may be large. As a result, there is a problem in that mobility decreases at the interface between the first nitride semiconductor layer and the insulating film, and the on-resistance of the group III nitride field effect transistor increases.

  In the group III nitride field effect transistor of the present embodiment, a region damaged by dry etching can be covered with the nitride semiconductor film 23. Thus, the on-resistance of the group III nitride field effect transistor can be made difficult to increase without lowering the mobility of the nitride semiconductor film in the recess region.

(Embodiment 2)
The group III nitride field effect transistor of the present embodiment is a group III nitride electric field having the same configuration as that of the first embodiment except that a p-type nitride semiconductor is used as the nitride semiconductor film of the first embodiment. It is an effect transistor.

(Production method)
The manufacturing method of the group III nitride field effect transistor of the present embodiment is the same as that of the first embodiment except that a p-type nitride semiconductor is formed as the nitride semiconductor film 23. A group nitride field effect transistor is fabricated.

  Thus, by using the nitride semiconductor film 23 made of a p-type nitride semiconductor, the threshold voltage can be improved, and the threshold voltage can be controlled by the p-type concentration.

  Further, it is preferable to perform annealing for activating the p-type dopant contained in the nitride semiconductor film 23. By activating the p-type dopant contained in the nitride semiconductor film 23 by annealing in this way, the threshold voltage can be improved.

(Embodiment 3)
The group III nitride field effect transistor of the present embodiment is characterized in that the forbidden band width of the nitride semiconductor film 23 is smaller than the forbidden band width of the first nitride semiconductor layer 12. By using the nitride semiconductor film 23 smaller than the forbidden band width of the first nitride semiconductor layer 12 in this way, the activation rate of p-type increases, and a higher p-type with a lower concentration of p-type impurities. Carrier concentration can be obtained.

  Depending on the composition ratio, thickness, and carrier concentration of first nitride semiconductor layer 12 as described above, carriers may be formed at the heterojunction interface between nitride semiconductor film 23 and first nitride semiconductor layer 12. However, it is more preferable because the carrier concentration of the entire group III nitride field effect transistor increases.

(Production method)
The manufacturing method of the group III nitride field effect transistor of the present embodiment is the same as that of the first embodiment except that a nitride semiconductor film 23 smaller than the forbidden band width of the first nitride semiconductor layer 12 is formed. A III-nitride field effect transistor is manufactured by the same manufacturing method.

The group III nitride field effect transistor of Example 1 is produced as follows.
In this embodiment, first, a substrate 1 made of Si is prepared. Then, as shown in FIG. 2, a thin undoped AlN layer and a thick undoped GaN multiple nitride semiconductor layer are formed on the substrate 1 by using a metal organic chemical vapor deposition (MOCVD) method. A base semiconductor layer 2 made of the above and a nitride semiconductor multilayer body 100 are laminated. The nitride semiconductor stacked body 100 includes a base nitride semiconductor layer 11 made of undoped Al _0.05 Ga _0.95 N having a thickness of 1000 nm, a first nitride semiconductor layer 12 made of an undoped GaN layer having a thickness of 100 nm, and sequentially from the top. A second nitride semiconductor layer 13 having a three-layer structure of undoped GaN / Al _0.25 Ga _0.75 N / AlN having a thickness of 1 nm / 22 nm / 1 nm is stacked in this order.

Next, a SiO ₂ film is formed on the second nitride semiconductor layer 13 using a CVD method. Then, a resist 51 on the SiO ₂ film and the SiO ₂ film is removed in the portion that becomes the recess region using a photolithography technique. As shown in FIG. 3, the portion of the SiO ₂ film that has not been removed becomes the selective growth mask 50. Note that the resist 51 manufactured by using the photolithography technique is left without being peeled off.

  Next, as shown in FIG. 4, an inductively coupled plasma (ICP) etching apparatus is used for the portion where the second nitride semiconductor layer 13 is exposed without the selective growth mask 50 being formed. Then, the recess region 20 is formed by removing the upper thickness T1 (T1 is 50 nm) of the second nitride semiconductor layer 13 and the first nitride semiconductor layer 12, and then the resist 51 is removed.

  Next, as shown in FIG. 5, an undoped layer having a thickness T2 (T2 is 30 nm) is formed on the region where the first nitride semiconductor layer 12 is exposed without the selective growth mask 50 being formed. A nitride semiconductor film 23 made of GaN is formed by regrowth. Then, the selective growth mask 50 is removed.

Next, the upper surface of the nitride semiconductor film 23, the inner wall surface of the recess region 20, and the upper surfaces of the second nitride semiconductor layers 13a and 13b are washed with sulfuric acid / hydrogen peroxide solution, and further washed with hydrochloric acid / hydrogen peroxide solution. To do. Then, as shown in FIG. 6, an insulating film 9 made of SiO ₂ having a thickness of 30 nm is formed on the inner surface of the recess region 20 and the upper surfaces of the second nitride semiconductor layers 13 a and 13 b by using the CVD method.

  Then, as shown in FIG. 7, the insulating film 9 in the upper surface of the second nitride semiconductor layers 13 a and 13 b where the source electrode and the drain electrode are formed is removed by photolithography, and the contact region 25 is removed. Make it. Then, annealing is performed at 1000 degrees under a nitrogen atmosphere, thereby reducing the interface state of the surface where insulating film 9 and nitride semiconductor multilayer body 100 are in contact with each other.

  Thereafter, as shown in FIG. 8, the source electrode 6 made of Ti / Al and the source electrode 6 are formed on the contact regions 25 of the second nitride semiconductor layers 13 a and 13 b by using a photolithography technique and an EB vapor deposition method. A drain electrode 7 having the same composition is formed. Then, the source electrode 6 and the drain electrode 7 are brought into ohmic contact with the two-dimensional electron gases 14a and 14b by performing heat treatment at 800 ° C. for 1 minute in a vacuum atmosphere.

  Next, the gate electrode 8 made of Ni / Au is formed on the insulating film 9 by using a photolithography technique and an EB vapor deposition method. Through the above steps, the group III nitride field effect transistor of this example is fabricated.

  In the group III nitride field effect transistor of Example 1 manufactured as described above, since the nitride semiconductor film 23 in contact with the recess interface 20c is not damaged by dry etching, high mobility is obtained at the recess interface 20c. Thus, the resistance of the recess interface 20c at the time of ON can be reduced. This is considered due to an increase in mobility at the recess interface 20c and an increase in inversion layer electron concentration.

This embodiment is the same as the embodiment except that a p-type GaN layer doped with Mg at a concentration of 1 × 10 ¹⁹ cm ⁻³ is used as the nitride semiconductor film 23 of the group III nitride field effect transistor of the first embodiment. 1 is a group III nitride field effect transistor having the same configuration as in FIG. The underlying nitride semiconductor layer 11 made of p-type GaN is doped with p-type impurity Mg at a concentration of 1 × 10 ¹⁹ cm ⁻³ , but the activation rate of Mg in GaN is low, so p-type GaN Has a hole concentration of 1 × 10 ¹⁷ cm ⁻³ .

(Production method)
In the group III nitride field effect transistor of this example, as the nitride semiconductor film 23, a p-type GaN layer doped with Mg at a concentration of 1 × 10 ¹⁹ cm ⁻³ is formed, and an insulating film is formed A III-nitride field effect transistor is manufactured by the same manufacturing method as in Example 1 except that annealing for activating the p-type dopant is performed before the step.

Example 3 uses p-type In _0.1 Ga _0.9 N doped with Mg at a concentration of 1 × 10 ¹⁸ cm ⁻³ as the nitride semiconductor film 23 of the group III nitride field effect transistor of Example 1 3 is a group III nitride field effect transistor having the same configuration as in Example 1. Here, the hole concentration contained in the underlying nitride semiconductor layer is 1 × 10 ¹⁷ cm ⁻³ . As a result, the activation rate of the p-type conversion of the underlying nitride semiconductor layer 11 increases, and the same p-type carrier concentration can be obtained with a lower concentration of p-type impurities.

(Production method)
In the group III nitride field effect transistor of this example, a p-type In _0.1 Ga _0.9 N layer doped with Mg at a concentration of 1 × 10 ¹⁸ cm ⁻³ was formed as a nitride semiconductor film, and A group III nitride field effect transistor is manufactured by the same manufacturing method as in Example 1 except that annealing for activating the p-type dopant is performed after the formation of the two nitride semiconductor layers 13a and 13b. .

(Comparative Example 1)
Comparative Example 1 is a Group III nitride field effect transistor having the same configuration as Example 1 except that the nitride semiconductor film 23 is not formed in the Group III nitride field effect transistor of Example 1. Therefore, since the manufacturing method of the group III nitride field effect transistor of Comparative Example 1 is the same up to the step of forming the recess region of Example 1 (FIG. 4), the steps after this step will be described.

  FIG. 9 is a schematic cross-sectional view showing a state after an insulating film is formed on the inner surface of the recess region and on the second nitride semiconductor layer. In this comparative example, as shown in FIG. 9, after forming the recess region by etching, the insulating film 9 is formed without forming the nitride semiconductor film.

  FIG. 10 is a schematic cross-sectional view showing a group III nitride field effect transistor of Comparative Example 1. After the insulating film 9 is formed as described above, the group III nitride field effect transistor shown in FIG. 10 is fabricated by the same method as in the first embodiment.

  In the group III nitride field effect transistor of Comparative Example 1, since the insulating film is formed after the recess region 20 is formed by etching, the interface of the insulating film 9 in contact with the recess interface 20c is damaged by dry etching. For this reason, mobility is lowered at the recess interface, and the on-resistance of the group III nitride field effect transistor has a high value.

  As is apparent from the above description, the group III nitride field effect transistors according to the present invention of Examples 1 to 3 have lower on-resistance than the group III nitride field effect transistor of Comparative Example 1. Obviously. This reveals that the on-resistance can be lowered by forming a nitride semiconductor film on the recess region after forming the recess region of the group III nitride field effect transistor by dry etching. .

  Although the embodiments and examples of the present invention have been described as described above, it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments and examples.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Substrate, 2 Underlying semiconductor layer, 6 Source electrode, 7 Drain electrode, 8 Gate electrode, 9 Insulating film, 11 Underlying nitride semiconductor layer, 12 First nitride semiconductor layer, 13, 13a, 13b Second nitride semiconductor layer 14a, 14b Two-dimensional electron gas, 16a, 16b heterojunction interface, 20 recess region, 20c recess interface, 23 nitride semiconductor film, 25 contact region, 50 selective growth mask, 100 nitride semiconductor laminate.

Claims (9)

An underlying semiconductor layer;
A nitride semiconductor stacked body in which a first nitride semiconductor layer and a second nitride semiconductor layer are sequentially stacked on the base semiconductor layer;
A source electrode and a drain electrode in contact with an upper surface of the nitride semiconductor multilayer body;
A recess region that is a region in which a part of the first nitride semiconductor layer and the second nitride semiconductor layer are not formed in the nitride semiconductor stacked body between the source electrode and the drain electrode;
A nitride semiconductor film formed on the recess region;
An upper surface of the nitride semiconductor film, an inner wall surface of the recess region, and an insulating film formed on the upper surface of the second nitride semiconductor layer;
A gate electrode formed on the insulating film,
The second nitride semiconductor layer has a wider forbidden band than the first nitride semiconductor layer,
Upper surface of the nitride semiconductor film, rather lower than the upper surface of the first nitride semiconductor layer,
The first nitride semiconductor layer is GaN;
The nitride semiconductor film is a group III nitride field effect transistor made of In _x Ga _1-x N (0 <x ≦ 1) . 2. The group III nitride field effect transistor according to claim 1, wherein the second nitride semiconductor layer has a three-layer structure in which GaN / AlGaN / AlN are sequentially stacked from the source electrode and drain electrode sides. 3. The group III nitride field effect transistor according to claim 1, wherein the nitride semiconductor film is made of a p-type nitride semiconductor or an i-type nitride semiconductor. The group III nitride field effect transistor according to claim 3 , wherein a hole concentration contained in the nitride semiconductor film is 1 × 10 ¹⁷ cm ⁻³ or less. The group III nitride field effect transistor according to any one of claims 1 to 4 , wherein the nitride semiconductor film has a thickness of 30 nm or more. The nitride semiconductor laminate, the surface opposite to the second nitride semiconductor layer in contact with the surface of the first nitride semiconductor layer has a base nitride semiconductor layer, any one of claims 1 to 5 A group III nitride field-effect transistor described in 1. The recess region is produced by dry etching,
The nitride semiconductor film, the prepared using a regrowth method the inner surface of the recess region, III-nitride based field effect transistor according to any one of claims 1-6. Forming a first nitride semiconductor layer and a second nitride semiconductor layer on the underlying semiconductor layer;
Forming a selective growth mask on a portion of the second nitride semiconductor layer;
In the region where the selective growth mask is not formed, all of the second nitride semiconductor layer and the upper part of the first nitride semiconductor layer are removed, and a part of the first nitride semiconductor layer is exposed. Forming a recess region;
Forming a nitride semiconductor film on the recess region;
Removing the selective growth mask on the second nitride semiconductor layer;
Upper surface of the nitride semiconductor film, viewing including the step of forming the inner wall surface, and an insulating film on the upper surface of the second nitride semiconductor layer of the recessed region,
The first nitride semiconductor layer is GaN;
The second nitride semiconductor layer is a nitride semiconductor layer having a wider forbidden band than the first nitride semiconductor layer,
The method for producing a group III nitride field effect transistor, wherein the nitride semiconductor film is made of In _x Ga _1-x N (0 <x ≦ 1) . The group III nitride field effect transistor according to claim 8, wherein the second nitride semiconductor layer has a three-layer structure in which GaN / AlGaN / AlN are sequentially stacked from the source electrode and drain electrode sides. Method.

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