JP5641821B2 - Method for manufacturing heterojunction field effect transistor - Google Patents

Description

  The present invention relates to a method for manufacturing a heterojunction field effect transistor made of a semiconductor containing nitride.

  In a conventional heterojunction field effect transistor (heterojunction field effect transistor) made of a nitride semiconductor, the gate electrode is directly formed on the semiconductor surface, and when the gate electrode is operated by applying a pulse voltage to the drain, A phenomenon (current collapse) in which the current is greatly reduced occurs, and the drain current is greatly reduced as compared with the output and efficiency that can be predicted from the DC characteristics when actually operating at a high frequency.

  Since current collapse is caused by trap levels formed on the semiconductor surface, in order to suppress current collapse, it is effective to keep the gate electrode / semiconductor interface to which the electric field is most intense away from the semiconductor surface. Therefore, it is desirable to have a recessed gate structure in which the gate electrode is formed after etching only the region where the gate electrode is formed on the semiconductor surface. The deeper the recess portion is, the greater the effect is because the gate electrode / semiconductor interface is further away from the semiconductor surface.

  However, in order to form the recess gate structure, it is necessary to etch the recess depth of the semiconductor layer directly under the gate electrode with good controllability, and it is difficult to control this only by the etching rate.

  Therefore, in the case of a heterojunction FET using an AlGaN / GaN heterostructure, a GaN cap layer equal to the etching depth is formed on the outermost surface to obtain a GaN / AlGaN / GaN structure, and the difference in etching rate between GaN and AlGaN is determined. A method of selectively etching only the GaN cap layer is often used (see, for example, Non-Patent Document 1).

IEEE EDL, VOL.29, NO.4, APRIL 2008, p303

  Many n-type impurities are mixed in the surface of the AlGaN or GaN layer, particularly on the surface side, during epitaxial growth or a process for manufacturing a transistor. Since a region where the effect of polarization by AlGaN works effectively is a depletion layer, n-type impurities existing in this region are not activated and do not become a current leakage path.

  However, since the polarization effect does not reach in a region far from AlGaN, the n-type impurity mixed in this region is activated and becomes a carrier, which can be a current leakage path.

  Accordingly, when the outermost GaN cap layer is so thick that the polarization effect of AlGaN does not reach, when the transistor is operated by applying a high voltage between the gate electrode and the drain electrode, a large voltage is applied from the gate electrode to the drain electrode. Leakage current occurs, resulting in a decrease in breakdown voltage that leads to a decrease in output and efficiency, a deterioration in noise characteristics, a decrease in reliability, and the like.

  In view of the above-described problems, an object of the present invention is to provide a method of manufacturing a heterojunction field effect transistor that suppresses current collapse and reduces gate leakage current.

The method of manufacturing a heterojunction field effect transistor according to the present invention includes: (a) preparing a nitride semiconductor layer including a stacked body in which a channel layer, a barrier layer, and a cap layer are sequentially stacked; and (b) the nitride. A step of forming a cap film not containing Si on the semiconductor layer; and (c) after the step (b), an impurity is selectively implanted into the nitride semiconductor layer, and the impurity is activated by a heat treatment to cause the impurity Forming a region; (d) after the step (c), removing the cap film to form a source electrode and a drain electrode on the doping region; and (e) forming the nitride semiconductor layer. and a step of forming a gate electrode in a region at least partially removed, step (a) is inferior thickness on the surface side opposite to the surface on which the effect of the polarization occurring in the barrier layer is in contact with the barrier layer of the cap layer A step of preparing a nitride semiconductor layer containing a cap layer.

  In the method of manufacturing a heterojunction field effect transistor according to the present invention, since a cap film not containing Si is formed on the nitride semiconductor layer, Si is mixed from the cap film into the nitride semiconductor layer in a subsequent heat treatment step. Therefore, even when a thick cap film is used, the gate leakage current can be reduced, so that both current collapse suppression and gate leakage current reduction can be achieved.

1 is a cross-sectional view illustrating a configuration of a heterojunction field effect transistor according to a first embodiment. 7 is a cross-sectional view showing a manufacturing process of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction field effect transistor according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing process of the heterojunction field effect transistor according to the first embodiment. FIG. It is the figure which showed the relationship between the thickness of a cap layer, gate current, and gate edge electric field strength. FIG. 6 is a cross-sectional view showing a configuration of a modification of the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration of a modification of the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration of a modification of the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration of a modification of the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration of a modification of the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration of a modification of the heterojunction field effect transistor according to the first embodiment. FIG. 10 is a cross-sectional view showing a manufacturing process of a variation of the heterojunction field effect transistor according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration of a heterojunction field effect transistor according to a second embodiment. 11 is a cross-sectional view showing a manufacturing process of the heterojunction field effect transistor according to the second embodiment. FIG. It is sectional drawing which shows the structure of the heterojunction field effect transistor which concerns on this invention.

(Embodiment 1)
<Prerequisite technology>
In the GaN / AlGaN / GaN structure as in Non-Patent Document 1, the distance from the semiconductor surface to the AlGaN / GaN interface where a two-dimensional electron gas serving as a channel is generated is increased by the amount of the GaN layer formed in the uppermost layer. Therefore, a sufficiently low resistance cannot be obtained with a source / drain electrode that is generally used in a conventional structure in which a GaN cap layer is not formed and an electrode metal is deposited and alloyed on a semiconductor surface.

  Therefore, in Non-Patent Document 1, a GaN layer and an AlGaN layer in a region where a source / drain electrode is to be formed are removed, and then a source / drain electrode is formed in that region, thereby realizing a low resistance electrode. However, since the source / drain electrode occupies a wider area than the gate electrode, the step caused by removing the GaN layer and the AlGaN layer adversely affects the process stability after forming the source / drain electrode, and the yield is reduced. There is a concern to bring.

  Since the Si ion implantation doping technique shown in “Phys. Status Solidi, C3, p.2364 2006” can reduce the resistance of only the source / drain electrode region without forming a step on the semiconductor surface, GaN / AlGaN / GaN This is one of effective means for forming a low resistance source / drain electrode in the structure. However, in the Si ion implantation doping technique, it is common to use SiN as a cap film at the time of heat treatment for activating the implanted Si ions, and this process is almost the same as when GaN or AlGaN crystals are grown. Since the treatment is performed at a temperature exceeding 1000 ° C., Si acting as an n-type dopant may be mixed into the semiconductor layer other than the source / drain electrode regions and activated. In a conventional AlGaN / GaN structure that does not form a GaN cap layer, the AlGaN barrier layer is depleted due to the polarization effect that occurs in the AlGaN barrier layer even if Si is mixed into the AlGaN barrier layer on the surface side and activated. Therefore, even when a high voltage is applied between the gate electrode and the drain electrode to operate the transistor, no leakage current is generated between the gate electrode and the drain electrode. On the other hand, in a heterojunction FET having a GaN cap layer formed on the surface, when the GaN cap layer is so thick that the polarization effect generated in the AlGaN barrier layer does not reach, the region on the surface side of the GaN cap layer is not depleted. Carriers are generated from Si that is mixed and activated in the region, which can be a current leakage path.

  Therefore, the present invention aims to reduce the leakage current by devising the material of the cap film during the heat treatment for activating the implanted Si ions.

<Configuration>
FIG. 1 is a cross-sectional view showing a configuration of a heterojunction field effect transistor (heterojunction FET) according to the present embodiment.

  The heterojunction FET according to the first embodiment includes a semi-insulating substrate 10 made of SiC, a buffer layer 20 formed on the SiC substrate 10, a channel layer 30 made of GaN formed on the buffer layer 20, The barrier layer 40 made of AlGaN formed on the channel layer 30, the gate electrode 100 made of Ni / Au formed on the barrier layer 40, and the thickness made of GaN are larger than 28 nm (as will be described later, according to the present invention). Cap layer 50, source electrode 80 and drain electrode 90 made of Ti / Al formed on cap layer 50, element isolation region 70, and channel layer below source / drain electrodes 80, 90. 30, a barrier layer 40, and a high concentration impurity region 60 formed in the cap layer 50.

  The gate electrode 100 is formed in a region where the cap layer 50 is removed, and the lower surface of the gate electrode 100 is formed in contact with the upper surface of the barrier layer 40. The high concentration impurity region 60 is a region doped with Si ions as an n-type impurity, and has an effect of suppressing the resistance of the source / drain electrodes 80 and 90.

<Process>
2 to 9 are diagrams showing an example of the manufacturing process of the heterojunction FET according to the first embodiment. In these drawings, the same or corresponding components as those in FIG. 1 are denoted by the same reference numerals. Hereinafter, the manufacturing process of the heterojunction FET according to the first embodiment will be described with reference to FIGS.

  First, an epitaxial growth method such as MOCVD method or MBE method is applied on the semi-insulating substrate 10, and a buffer layer 20, a channel layer 30 made of GaN, a barrier layer 40 made of AlGaN, and a thickness made of GaN are applied as nitride semiconductor layers. The cap layers 50 having a thickness of larger than 28 nm are epitaxially grown in order from the bottom (FIG. 2).

  Next, a cap film 110 made of a material not containing Si, such as AlN, is deposited on the cap layer 50 using a sputtering method or the like (FIG. 3). As a formation method other than the sputtering method, the cap film 110 may be grown as the uppermost layer during the epitaxial layer growth of FIG. Or you may form by CVD method, EB vapor deposition method, etc. after epitaxial layer growth.

Thereafter, a resist mask 120 is formed, and Si ions are implanted into at least a part of the semiconductor layer below the region where the source / drain electrodes 80 and 90 are to be formed using, for example, an ion implantation method. The implantation dose is 1 × 10 ¹³ to 1 × 10 ¹⁷ (cm ⁻² ), and the implantation energy is 10 to 1000 (keV). Then, heat treatment is performed to activate the implanted Si ions, and a high concentration impurity region 60 is formed (FIG. 4).

  Next, the cap film 110 is removed by wet etching using KOH or the like (FIG. 5). Then, a source electrode 80 and a drain electrode 90 made of Ti / Al are deposited by vapor deposition or sputtering, and are formed by lift-off or the like (FIG. 6).

  Next, an element isolation region 70 is formed in the channel layer 30, the barrier layer 40, and the cap layer 50 outside the region where the transistor is to be formed by using, for example, ion implantation or etching (FIG. 7).

Then, a resist mask 130 is formed, and the cap layer 50 in a region where the gate electrode 100 is formed is removed by a dry etching method using Cl ₂ or the like (FIG. 8). In the case where the Al composition ratios of the cap layer 50 and the barrier layer 40 are different, selective etching is performed by using, for example, a fluorine-based gas such as oxygen or SF ₆ in addition to a chlorine-based gas such as Cl _2. Further, only the cap layer 50 can be etched, and the controllability of the etching depth is improved.

  After removing the resist mask 130, a gate electrode 100 made of Ni / Au is deposited by vapor deposition or sputtering, and formed by a lift-off method or the like (FIG. 9).

  Through the above steps, the heterojunction FET having the structure shown in FIG. 1 can be manufactured. Although only the minimum necessary elements that operate as a transistor are described above, the element is finally used as a device through a formation process of a protective film, a wiring, a via hole, and the like.

<Cap layer>
In the heterojunction FET manufactured by the above-described method, even when the GaN cap layer 50 is thicker than 28 nm, a material such as AlN not containing Si is used for the cap film 110 during the heat treatment for activating the implanted Si ions. Therefore, the gate leakage current can be kept sufficiently low. The reason will be described below.

  Four types of heterojunction FETs having the structure shown in FIG. 1 and having a thickness of the GaN cap layer 50 different from 0, 20, 50, and 100 nm are manufactured by the method shown in FIGS. The current value when a voltage of -10 V was applied between them was measured and shown in FIG. Note that SiN is used for the cap film 110 instead of AlN.

As shown in FIG. 10, when the GaN cap layer 50 was thinner than 20 nm, the gate leakage current was a sufficiently low value of 2.0 × 10 ⁻⁶ (A / mm) or less. On the other hand, the gate leakage current when the GaN cap layer 50 is thicker than 50 nm is about 1.0 × 10 ⁻⁴ (A / mm), which is about two orders of magnitude larger than the case of 20 nm or less. There is a concern about the deterioration.

  The cause of such a large gate leakage current is that Si is mixed from the SiN of the cap film 110 into the GaN cap layer 50 especially in the surface side during the heat treatment for activating the implanted Si ions. Behave as a career. Since the region on the AlGaN layer 40 side of the GaN cap layer 50 is depleted due to the polarization effect of the AlGaN barrier layer 40, even if Si that is an n-type impurity is mixed into GaN and activated, the carrier Does not occur and does not become a leak path. That is, when the GaN cap layer 50 is thin enough to exert the polarization effect generated in the AlGaN barrier layer 40, no leak current is generated even if n-type impurities are mixed in the GaN cap layer 50.

  On the other hand, when the GaN cap layer 50 is thick and there is a region on the surface side where the effect of polarization by the AlGaN layer 40 does not reach, the region is not depleted, and carriers are generated when n-type impurities are mixed. Therefore, the region becomes a leak path and a large leak current is generated.

  FIG. 10 also shows the result of calculating the gate leakage current value due to this effect. In this calculation, the carrier concentration generated on the surface side of the GaN cap layer 50 was first derived from the band structure calculated using the Poisson equation in the structure where the thickness of the GaN cap layer 50 is different. Subsequently, the current flowing through the Schottky barrier from the gate electrode 100 into the GaN cap layer 50 was calculated using them. Finally, the current value in the actual heterojunction FET in the case where the GaN cap layer 50 is not formed is added to the tunnel current calculated on the assumption that the current value flows outside the GaN cap layer 50 and plotted in FIG. . The calculated value is in good agreement with the actually measured value, and it has been found from this calculation result that a large leakage current occurs when the thickness of the GaN cap layer 50 is greater than 28 nm. That is, the region where the polarization effect generated in the AlGaN barrier layer 40 reaches only the range within 28 nm of the GaN cap layer 50 from the AlGaN barrier layer 40, and n-type impurities such as Si are mixed on the surface side of the region. In some cases, carriers are generated and cause a leakage current.

  FIG. 10 also shows the result of calculating the electric field strength generated at the gate electrode end on the drain electrode 90 side when the thickness of the GaN cap layer 50 is different by solving the Poisson equation. Since current collapse increases as the electric field strength generated at the gate electrode end increases, it can be seen from this calculation result that the thicker the GaN cap layer 50 is, the more preferable the structure is from the viewpoint of suppressing current collapse. That is, it can be said that suppression of current collapse and suppression of gate leakage current are in a trade-off relationship with respect to the thickness of the GaN cap layer 50.

  In order to get out of this trade-off, it is necessary to prevent the n-type impurity such as Si from entering a region of the GaN cap layer 50 that is away from the AlGaN barrier layer 50 by 28 nm. Since the heat treatment for activating the implanted Si ions needs to be performed at a temperature exceeding 1000 ° C., which is close to the epitaxial growth temperature of the nitride semiconductor, SiN having Si as an n-type impurity as a constituent element is used as the cap film 110. When used as, there is a high possibility that Si diffuses into the semiconductor layer, which causes the leakage current described above. Therefore, by making the thickness of the GaN cap layer 50 larger than 28 nm and using a film made of AlN or the like not containing Si for the cap film 110 during the activation heat treatment, current collapse is suppressed and gate leakage current is also reduced. It becomes possible to do.

<Modification 1>
By using a material not containing Si for the cap film 110, it is possible to prevent Si from being mixed into the GaN cap in the heat treatment step. Therefore, the material of the cap film 110 is not limited to the exemplified AlN, and BN, diamond, DLC (Diamond Like Carbon), AlO _x , AlO _x N _y , MgO _x or the like may be used. In addition, one or more of these films may be used in an overlapping manner.

  In the above description, the cap film used when Si ions are implanted is also used as a cap film in the heat treatment process for activating the Si ions after implantation. However, these films may be different films. That is, the cap film may be removed once after the Si ion implantation is completed, and the cap film during the activation heat treatment made of the same material or a different material may be deposited again. When the cap film is re-deposited in this way, it is sufficient to use a film made of a material that does not contain Si as at least the cap film at the time of the activation heat treatment. A material containing Si can also be used. Nonetheless, the substrate temperature rises even during Si ion implantation compared to the active heat treatment, but when a Si-containing material is used as a cap film, Si can be slightly mixed into the semiconductor layer. Therefore, it is preferable to use a cap film made of a material that does not contain Si.

<Modification 2>
In addition to SiC, Si, sapphire, GaN, AlN or the like can be used for the semi-insulating substrate 10. In the case of using GaN, the channel layer 30 and the like can be formed on the semi-insulating substrate 10 without forming the buffer layer 20, so that the buffer layer 20 can be formed arbitrarily.

<Modification 3>
In the high-concentration impurity region 60, as long as n-type impurities are contained at a high concentration, the dopant does not necessarily need to be Si, and may be oxygen, for example. 1 and 4, the high-concentration impurity region 60 is formed from the semiconductor surface to the channel layer 30, but is not necessarily limited to this region, and even if the region is large or small, It may be formed in at least a part of the semiconductor layer below the source electrode 80 and the drain electrode 90.

  The dopant can be changed, and the implantation region and depth can be controlled by changing the implanted ion species, mask pattern, implantation energy, and dose during the Si ion implantation shown in FIG.

<Modification 4>
The source / drain electrodes 80 and 90 are not necessarily made of Ti / Al. As long as ohmic characteristics can be obtained, metals such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, and W can be used. , And may be formed of a multilayer film composed of these.

  For example, Ti / Al, Nb, Hf, Zr, Sr, Ni, source / drain electrodes 80 and 90 having such a structure are used instead of Ti / Al when the source / drain electrodes 80 and 90 shown in FIG. A metal such as Ta, Au, Mo, W, or a multilayer film composed of these is deposited by vapor deposition or sputtering, and formed by lift-off or the like.

<Modification 5>
The gate electrode 100 is not necessarily a Ni / Au, Ti, Al, Pt, Au, Ni, or metals such as Pd, IrSi, PtSi, silicide such as NiSi _2, TiN, metal nitride such as WN, or, It may be a multilayer film composed of these.

The gate electrode 100 having such a structure is formed in the gate electrode forming step shown in FIG. 9 in place of Ni / Au, for example, a metal such as Ti, Al, Pt, Au, Ni, Pd, IrSi, PtSi, NiSi _2. A gate electrode 100 made of a silicide such as TiN, a nitride metal such as TiN or WN, or a multilayer film composed of these is deposited by vapor deposition or sputtering, and formed by a lift-off method or the like.

<Modification 6>
If the bottom surface of the gate electrode 100 is not in contact with the surface of the cap layer 50, current collapse can be suppressed as compared with the case of being in contact with the surface of the cap layer 50. Therefore, the bottom surface of the gate electrode 100 is not necessarily in contact with the barrier layer 40. For example, a structure in contact with the inside of the cap layer 50 (FIG. 11) or a structure in contact with the inside of the barrier layer 40 (FIG. 12). But you can.

  However, in order to etch the semiconductor layer immediately below the gate electrode 100 with good controllability, it is preferable to use a difference in etching rate when etching layers having different structures. In that case, as shown in FIGS. Thus, a structure in which the bottom surface of the gate electrode 100 is in contact with the top surface of the barrier layer 40 is more preferable.

  A heterostructure FET having a gate structure as shown in FIGS. 11 and 12 can be manufactured by adjusting the etching time and the gas flow rate in the etching process shown in FIG. 8 to a desired etching depth.

<Modification 7>
In addition, the gate electrode is not limited to a rectangular cross section, and may be a T-type or Y-type structure in which a region in contact with the barrier layer 40 is reduced as in the gate electrode 101 shown in FIG. With such a structure, the gate resistance can be reduced while maintaining an area where the gate electrode 101 is in contact with the semiconductor layer.

  Further, as shown in FIG. 14, the collar portion of the gate electrode 101 may be formed in contact with the surface of the cap layer 50. With such a structure, an electric field concentrated on the edge portion on the drain electrode 90 side of the gate electrode 101 during high-voltage operation can be relaxed, and current breakdown can be suppressed and the breakdown voltage can be increased.

  In the structure of the gate electrode 101 shown in FIG. 14, at least one kind of atoms of Al, Ga, Si, Hf, and Ti is formed on the surface of the cap layer 50 including at least the gap between the gate electrode 101. A structure as shown in FIG. 15 in which an insulating film 150 made of oxide, nitride, oxynitride, or the like is formed may be used. With such a structure, an electric field concentrated on the edge portion on the drain electrode 90 side of the gate electrode 101 during high-voltage operation can be relaxed, and current breakdown can be suppressed and the breakdown voltage can be increased.

  Further, as shown in FIG. 16, by forming the insulating film 150 only between the collar portion of the gate electrode 101 and the cap layer 50, between the source electrode 80 and the gate electrode 101 or between the gate electrode 101 and the drain electrode 90. The capacitance generated between them can be reduced, and the gain and efficiency during high-frequency operation can be improved.

  The gate electrode 101 shown in FIG. 16 is formed by depositing an electrode by an evaporation method or the like using a resist pattern wider than the etching region in the gate electrode formation step of FIG.

  Further, in the pre-process for etching the cap layer 50 shown in FIG. 8, an oxide of at least one kind of atoms of Al, Ga, Si, Hf, Ti, etc. using, for example, a vapor deposition method or a plasma CVD method, By depositing an insulating film 150 made of nitride, oxynitride, or the like (FIG. 17) and then forming the gate electrode 101, a heterojunction FET having the structure shown in FIG. 15 can be fabricated.

  Further, after the heterojunction FET having the structure shown in FIG. 15 is formed, the insulating film 150 is completely removed by wet etching using hydrofluoric acid or the like, whereby the heterojunction FET having the structure shown in FIG. 13 can be manufactured. Further, by adjusting the wet etching process conditions (time and concentration), a heterojunction FET having the structure shown in FIG. 16 can be produced in which the insulating film 150 is left only between the collar portion of the gate electrode 101 and the cap layer 50. .

<Effect>
The method for manufacturing a heterojunction field effect transistor according to the present embodiment includes (a) a step of preparing a nitride semiconductor layer including a stacked body in which a channel layer 30, a barrier layer 40, and a cap layer 50 are sequentially stacked; b) a step of forming a cap film 110 containing no Si on the nitride semiconductor layer; and (c) after step (b), an impurity is selectively implanted into the nitride semiconductor layer, and the impurity is subjected to heat treatment. After the step of forming the high concentration impurity region 60 (impurity region) and (d) step (c), the cap film 110 is removed and the source electrode 80 and the drain electrode 90 are formed on the high concentration impurity region 60. And (e) forming a gate electrode 100 in a region where at least a part of the nitride semiconductor layer is removed. By forming the cap film 110 not containing Si, Si is not mixed into the nitride semiconductor layer from the cap film 110 in the heat treatment in the step (c), and even when the thick cap film 110 is used, the gate leakage current is reduced. Therefore, both current suppression and gate leakage current can be reduced.

  In addition, the current collapse can be suppressed by making the thickness of the cap layer 50 larger than 28 nm in the step (a).

  Further, in the step (e), when the gate electrode 100 is formed such that the cap layer 50 is removed and the bottom of the gate electrode 100 is in contact with the upper surface of the barrier layer 40, the difference in etching rate between the cap layer 50 and the barrier layer 40 Since the etching can be performed with good controllability, the yield is improved.

  Moreover, the resistance of the source / drain electrodes 80 and 90 can be reduced by injecting Si into the nitride semiconductor layer as an impurity in the step (c).

  Further, by forming the cap film 110 made of AlN in the step (b), Si is not mixed into the nitride semiconductor layer from the cap film 110 in the heat treatment of the step (c), and the thick cap film 110 is formed. Even when it is used, the gate leakage current can be reduced, so that both current collapse suppression and gate leakage current reduction can be achieved.

(Embodiment 2)
FIG. 18 is a cross-sectional view showing the configuration of the heterojunction FET according to the second embodiment. In FIG. 18, the same reference numerals are given to the same or corresponding components as those in FIG. In the heterojunction FET according to the second embodiment, a spacer layer 140 made of a material (for example, AlN) having a larger band gap than the material forming these layers is formed between the channel layer 30 and the barrier layer 40. . Since the configuration other than this is the same as that of the first embodiment, the description thereof is omitted.

  By providing the spacer layer 140, the confinement effect of the two-dimensional electron gas (2DEG) generated on the barrier layer 40 side of the channel layer 30 can be increased, so that the concentration is increased and the alloy scattering is also reduced, thereby improving the mobility. In addition, the current of the transistor can be increased and the output can be increased.

  In the heterojunction FET according to the second embodiment, after the channel layer 30 shown in FIG. 2 is epitaxially grown, the spacer layer 110 is formed using a material having a larger band gap than the material forming the channel layer 30 and the barrier layer 40. (FIG. 19). Thereafter, in the same manner as in the first embodiment, the heterojunction FET shown in FIG. 18 is formed.

<Modification>
Channel layer 30, spacer layer 140, the barrier layer 40, the bandgap respective B ₃₀ of the cap layer 50, B _140, B _40, when the B _50, these _{B 30 <B 40 <B 100} , B 50 <B If the relationship is ₄₀ , the heterojunction FET is operated, the concentration and mobility of the two-dimensional electron gas by the spacer layer 140 are improved, and only the cap layer 50 in the region of the gate electrode 100 is selectively removed. I can do it. Therefore, the cap layer 50 is not necessarily made of GaN, and the barrier layer 40 is not necessarily made of AlGaN, but may be made of a compound semiconductor composed of at least two elements including N among Al, Ga, and N having different constituent compositions. good.

For example, the compound semiconductors constituting the channel layer 30, the spacer layer 140, the barrier layer 40, and the cap layer 50 are Al _X30 Ga _{1 -X30} N, Al _X140 Ga _{1 -X140} N, Al _X40 Ga _{1 -X40} N, and Al _{X50, respectively. Assuming} Ga _{1 -X50} N, 0 ≦ X ₃₀ <1, 0 <X ₁₄₀ ≦ 1, 0 <X ₄₀ ≦ 1, 0 ≦ X ₅₀ <1, X ₃₀ <X ₄₀ <X _140, X ₅₀ ≦ X ₄₀ What is necessary is just to be comprised with the compound semiconductor which satisfy | fills the relationship. Furthermore, it is not necessary to be composed of a compound composed of at least two elements including N out of Al, Ga, and N, for example, composed of a compound semiconductor composed of at least two kinds including N among In, Al, Ga, and N. May be.

  However, when the channel layer 30, the spacer layer 140, the barrier layer 40, and the cap layer 50 are composed of a compound composed of at least two elements including N among Al, Ga, and N, a large polarization effect is generated in the barrier layer 40. Therefore, a high-concentration two-dimensional electron gas can be generated on the barrier layer 40 side of the channel layer 30, which is advantageous for increasing the current and output of the transistor.

The heterojunction FET has a higher breakdown voltage as the dielectric breakdown field of the semiconductor material used for the channel layer 30 is higher. Since Al _X Ga _{1 -X} N has a higher band gap and a higher breakdown electric field as the Al composition is higher, the Al composition is higher when the channel layer 30 is composed of Al _X30 Ga _{1 -X30} N as described above. (X ₃₀ is close to 1) is preferred. In addition, since the gate leakage current flowing from the gate electrode 100 to the hetero interface through the barrier layer 40 is suppressed as the band gap of the semiconductor material used for the barrier layer 40 is larger, Al _X40 Ga _{1 -X40} used as the barrier layer 40. Similarly, it is preferable that N has a higher Al composition.

  In addition, the channel layer 30, the spacer layer 140, the barrier layer 40, and the cap layer 50 do not necessarily have a single-layer structure with the same composition. As long as the above-described band gap is satisfied, the In composition and Al composition The Ga composition may be spatially changed, or a multilayer film composed of several different layers may be used. These layers may contain n-type and p-type impurities.

  In the epitaxial growth of the channel layer 30, the spacer layer 140, the barrier layer 40, and the cap layer 50 shown in FIG. 19, trimethylammonium, trimethylgallium, trimethylindium, ammonia, which is a source gas for nitride semiconductor, or silane which is a source gas for impurities The channel layer 30, the barrier layer 40, and the cap layer 50 are formed to have desired compositions, film thicknesses, and doping concentrations by adjusting the flow rate, pressure, temperature, and time of oxygen, oxygen, etc. An FET is formed.

<Effect>
In the heterojunction FET of the present embodiment, the spacer layer 140 made of a material having a larger band gap than the material forming these layers is formed between the channel layer 30 and the barrier layer 40, and thus the barrier of the channel layer 30. Since the confinement effect of the two-dimensional electron gas generated on the layer 40 side can be increased, the concentration is increased and the alloy scattering is also reduced, so that the mobility is improved and the current of the transistor can be increased and the output can be increased. I can do it.

(Other)
Although the present invention has been described with respect to various embodiments, it is possible to implement the present invention by appropriately combining these embodiments including modifications. For example, as shown in FIG. 20, the bottom surface of the T-shaped gate electrode 101 is positioned in the barrier layer 40, and the insulating film 150 is formed on the surface of the cap layer 50 including the gap of the gate electrode 101. A heterojunction FET may be used.

  Moreover, although the manufacturing process was demonstrated in the various Example, you may replace a process suitably. For example, the element isolation region 70 may be formed before the source / drain electrodes 80 and 90 are formed.

  10 semi-insulating substrate, 20 buffer layer, 30 channel layer, 40 barrier layer, 50 cap layer, 60 heavily doped region, 70 element isolation region, 80 source electrode, 90 drain electrode, 100, 101 gate electrode, 110 cap film 120, 130 Resist mask, 140 Spacer layer, 150 Insulating film.

Claims (4)

(A) preparing a nitride semiconductor layer including a laminate in which a channel layer, a barrier layer, and a cap layer are sequentially laminated;
(B) forming a cap film not containing Si on the nitride semiconductor layer;
(C) after the step (b), selectively injecting impurities into the nitride semiconductor layer and activating the impurities by heat treatment to form impurity regions;
(D) after the step (c), removing the cap film and forming a source electrode and a drain electrode on the impurity region;
(E) forming a gate electrode in a region where at least a part of the nitride semiconductor layer is removed;
With
The step (a) is a step of preparing the nitride semiconductor layer including the cap layer having a thickness such that the polarization effect generated in the barrier layer does not reach the surface side opposite to the surface of the cap layer in contact with the barrier layer. Is,
A method of manufacturing a heterojunction field effect transistor. The heterojunction field effect transistor according to claim 1, wherein the step (e) is a step of removing the cap layer and forming the gate electrode so that a bottom portion of the gate electrode is in contact with an upper surface of the barrier layer. Manufacturing method. The method of manufacturing a heterojunction field effect transistor according to claim 1 or 2, wherein the step (c) is a step of implanting Si into the nitride semiconductor layer as the impurity. The method of manufacturing a heterojunction field effect transistor according to claim 1, wherein the step (b) is a step of forming the cap film made of AlN.

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