JP2011044647A - Group-iii nitride-based field-effect transistor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a group-III nitride-based field-effect transistor having low ON resistance, and to provide a method of manufacturing the same. <P>SOLUTION: The group-III nitride-based field-effect transistor includes: a base semiconductor layer; a nitride semiconductor laminate comprising a first nitride semiconductor layer, a second nitride semiconductor layer, and a third nitride semiconductor layer laminated in order on the base semiconductor layer; a source electrode and a drain electrode; a recessed region as a region where neither the second nitride semiconductor nor the third nitride semiconductor layer is formed, an insulating film formed on an inner surface of the recessed region and an upper surface of the nitride semiconductor laminate, and a gate electrode formed on the insulating film, wherein no step is formed between an upper surface of the first nitride semiconductor layer coming into contact with the insulating film and an upper surface of the first nitride semiconductor layer coming into contact with the second nitride semiconductor layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a group III nitride field effect transistor and a manufacturing method thereof, and more particularly to a group III nitride field effect transistor using a nitride semiconductor and a manufacturing method thereof.

  Since nitride-based semiconductors have high values of breakdown field strength, thermal conductivity, and saturation electron velocity, group III nitride-based field effect transistors using nitride-based semiconductors are small and It is characterized by low on-resistance and excellent pressure resistance. Group III nitride field effect transistors having such characteristics are expected to be applied to high-efficiency power conversion devices and high-frequency power devices.

  The group III nitride field effect transistor is formed by laminating a GaN layer and an AlGaN layer. By laminating the GaN layer and the AlGaN layer in this manner, spontaneous polarization and piezo polarization occur between these two layers. Due to the polarization electric field generated due to these polarizations, a two-dimensional electron gas (2-DEG) is formed at the heterointerface, and a high-concentration sheet carrier is generated. As a result, a normally-on group III nitride field effect transistor having a low on-resistance and excellent pressure resistance can be manufactured.

  On the other hand, a normally-off group III nitride field effect transistor having a high threshold voltage is desired from the viewpoint of suppressing overcurrent and simplifying the circuit configuration. Patent Document 1 discloses a technique for imparting a normally-off operation to a group III nitride field effect transistor.

  In Patent Document 1, a normally-off operation is obtained by forming a recess in the electron supply layer and providing an insulating film in the recess so that the two-dimensional electron gas is not formed in the electron transit layer. Yes.

International Publication No. 2003/071607 Pamphlet

  However, in Patent Document 1, since the recess region is formed by the dry etching technique, the recess region is damaged by the dry etching. Further, the surface roughness in the recess region is deteriorated. As a result, the mobility is lowered in the recess region, and there is a problem that the on-resistance of the group III nitride field effect transistor is increased.

  On the other hand, when a positive voltage is applied to the gate electrode, the inversion layer carrier is formed under the gate electrode, thereby connecting the inversion layer carrier and the two-dimensional electron gas, thereby obtaining a group III nitride electric field. The effect transistor is turned on.

  However, since the distance between the inversion layer carrier formed in the vertical direction of the recess region and the gate electrode is long, the number of carriers in the inversion layer carrier formed in the vertical direction of the recess region with respect to the gate electrode is reduced, and the on-resistance is reduced. There was a problem of increasing.

  The present invention has been made in view of such a current situation, and an object thereof is to provide a group III nitride field effect transistor having a high electron mobility in a recess region and a low on-resistance, and a method for manufacturing the same. To do.

  The group III nitride field effect transistor of the present invention includes a base semiconductor layer, and a nitridation in which a first nitride semiconductor layer, a second nitride semiconductor layer, and a third nitride semiconductor layer are sequentially stacked on the base semiconductor layer. A second nitride semiconductor layer and a third nitride semiconductor in the nitride semiconductor multilayer body, the source electrode and the drain electrode in contact with the upper surface of the nitride semiconductor multilayer body, and the nitride semiconductor multilayer body between the source electrode and the drain electrode A third nitride comprising: a recess region which is a region in which no layer is formed; an insulating film formed on the inner surface of the recess region and the upper surface of the nitride semiconductor stacked body; and a gate electrode formed on the insulating film. The semiconductor layer has a wider forbidden band width than the first nitride semiconductor layer and the second nitride semiconductor layer, and is in contact with the upper surface of the first nitride semiconductor layer in contact with the insulating film and the second nitride semiconductor layer. First Characterized in that there is no difference in level and the upper surface of the compound semiconductor layer.

  It is preferable that there is no difference in surface roughness between the upper surface of the first nitride semiconductor layer in contact with the insulating film and the upper surface of the first nitride semiconductor layer in contact with the second nitride semiconductor layer.

  The first nitride semiconductor layer is preferably made of a p-type nitride semiconductor or an i-type nitride semiconductor.

The concentration of holes contained in the first nitride semiconductor layer is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

The first nitride semiconductor layer and the second nitride semiconductor layer are preferably GaN.
The first nitride semiconductor layer is preferably In _x Ga _1-x N (0 <x ≦ 1).

The thickness of the second nitride semiconductor layer is preferably 30 nm or more.
The second nitride semiconductor layer and the third nitride semiconductor layer are preferably formed using a regrowth method.

  The present invention includes a step of forming a first nitride semiconductor layer on a base semiconductor layer, a step of forming a selective growth mask on a part of the first nitride semiconductor layer, and no selective growth mask is formed. A step of forming the second nitride semiconductor layer and the third nitride semiconductor layer on the first nitride semiconductor layer, and removing the selective growth mask to expose a part of the first nitride semiconductor layer. It is also a method for manufacturing a group III nitride field effect transistor, including a step of forming a recess region, and a step of forming an insulating film on the inner surface of the recess region and the third nitride semiconductor layer.

  Preferably, the method further includes a step of cleaning the inner surface of the recess region and the third nitride semiconductor layer after the step of removing the selective growth mask.

  Further, it is preferable to include a step of annealing the insulating film.

  According to the present invention, it is possible to provide a group III nitride field effect transistor having a high electron mobility in a recess region and a low on-resistance, and a method for manufacturing the same.

It is typical sectional drawing which shows an example of the group III nitride field effect transistor of this invention. It is typical sectional drawing which shows the state after forming the 1st nitride semiconductor layer on a board | substrate. It is a typical sectional view showing the state after forming a selective growth mask on a part of the first nitride semiconductor layer. It is typical sectional drawing which shows the state after forming the nitride semiconductor laminated body on a board | substrate. FIG. 6 is a schematic cross-sectional view showing a state after an insulating film is formed on the inner surface of the recess region and the upper surface of the third nitride semiconductor layer. It is typical sectional drawing which shows the state after forming a contact region in an insulating film. It is typical sectional drawing which shows the state after forming a source electrode and a drain electrode. It is typical sectional drawing which shows the state after forming the nitride semiconductor laminated body on a board | substrate. It is typical sectional drawing which shows the state after forming a recess area | region by etching. 6 is a schematic cross-sectional view showing an example of a group III nitride field effect transistor of Comparative Example 1. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The configurations shown in the drawings and the following description are merely examples, and the scope of the present invention is not limited to those shown in the drawings and the following description. In the drawings of the present application, the same reference numerals represent the same or corresponding parts. In the drawings of the present application, the dimensional relationships such as length, width, and thickness are appropriately changed for clarity and simplification of the drawings and do not represent actual dimensional relationships.

(Embodiment 1)
<Group III nitride field effect transistor>
FIG. 1 is a schematic cross-sectional view of a group III nitride field effect transistor of the present embodiment. In the group III nitride field effect transistor of the present embodiment, a base semiconductor layer 2 is formed on a substrate 1 as shown in FIG. Then, the first nitride semiconductor layer 11, the second nitride semiconductor layers 12a and 12b, and the third nitride semiconductor layers 13a and 13b are stacked in this order on the underlying semiconductor layer 2. The first nitride semiconductor layer 11, the second nitride semiconductor layers 12a and 12b, and the third nitride semiconductor layers 13a and 13b are referred to as a nitride semiconductor stacked body 100, and the first nitride semiconductor layer 11, the interfaces of the second nitride semiconductor layers 12a and 12b and the third nitride semiconductor layers 13a and 13b are referred to as heterojunction interfaces 15a, 15b, 16a, and 16b.

  Here, since the forbidden band width of the third nitride semiconductor layers 13a and 13b is wider than the forbidden band width of the second nitride semiconductor layers 12a and 12b, the second nitride semiconductor layer 12a and the third nitride semiconductor layer At the heterojunction interface 16a with 13a, a two-dimensional electron gas 14a is generated on the second nitride semiconductor layer 12a side due to positive polarization charges. Similarly, at the heterojunction interface 16b between the second nitride semiconductor layer 12b and the third nitride semiconductor layer 13b, a two-dimensional electron gas 14b is generated on the second nitride semiconductor layer 12b side due to positive polarization charges.

  Further, the source electrode 6 is provided so as to be in contact with the upper surface of the third nitride semiconductor layer 13a. On the other hand, the drain electrode 7 is provided in contact with the upper surface of the third nitride semiconductor layer 13b. Here, the source electrode 6 and the drain electrode 7 are in ohmic contact with the third nitride semiconductor layers 13a and 13b.

  A part of the nitride semiconductor stacked body 100 between the source electrode 6 and the drain electrode 7 has a region where the second nitride semiconductor layers 12a and 12b and the third nitride semiconductor layers 13a and 13b are not formed. . This area is referred to as a recess area 20. An insulating film 9 is formed on the inner surface of the recess region 20 and the upper surfaces of the third nitride semiconductor layers 13a and 13b. Here, the interface between the first nitride semiconductor layer 11 and the insulating film 9 (that is, the bottom surface of the recess region 20) is referred to as a recess interface 20c. Then, the gate electrode 8 is formed on the insulating film 9 in the recess region 20.

  The group III nitride field effect transistor according to the present embodiment includes an upper surface of the first nitride semiconductor layer 11 in contact with the insulating film 9 and the first nitride semiconductor layer 11 in contact with the second nitride semiconductor layers 12a and 12b. It is characterized in that there is no step between the top surface.

  As described above, there is no step between the upper surface of the first nitride semiconductor layer 11 in contact with the insulating film 9 and the upper surface of the first nitride semiconductor layer 11 in contact with the second nitride semiconductor layers 12a and 12b. Therefore, the on-resistance of the group III nitride field effect transistor can be made difficult to increase.

  It is preferable that there is no difference in surface roughness between the upper surface of the first nitride semiconductor layer 11 in contact with the insulating film 9 and the upper surface of the first nitride semiconductor layer 11 in contact with the second nitride semiconductor layers 12a and 12b. Thus, since there is no difference in surface roughness on the upper surface of the first nitride semiconductor layer 11, it is possible to further suppress a decrease in mobility in the recess region 20. Here, “surface roughness” is an index indicating the smoothness of the surface, and the larger the surface roughness, the rougher the surface.

  In the following, the operation of the group III nitride field effect transistor of the present embodiment will be described.

<Operation of Group III Nitride Field Effect Transistor>
The group III nitride field effect transistor of the present embodiment is a normally-off type field effect transistor. That is, in the group III nitride field effect transistor of the present embodiment, the two-dimensional electron gas 14 a on the source electrode 6 side and the two-dimensional electron gas 14 b on the drain electrode 7 side are separated by the recess region 20. For this reason, in a state where no voltage is applied to the gate electrode 8 or in a state where 0 V is applied, even if a voltage is applied between the source electrode 6 and the drain electrode 7, it is difficult for current to flow through the channel.

  On the other hand, when a positive voltage is applied to gate electrode 8, electrons are accumulated in first nitride semiconductor layer 11 in contact with the bottom surface of insulating film 9 and second nitride semiconductor layers 12 a and 12 b in contact with insulating film 9. The two-dimensional electron gas 14a on the source electrode 6 side and the two-dimensional electron gas 14b on the drain electrode 7 side are electrically connected by the electrons. When a voltage is applied to the source electrode 6 and the drain electrode 7 in this state, a current flows through the channel and an on operation occurs.

  The group III nitride field effect transistor of the present embodiment has a reduced resistance at the recess interface 20c when turned on, and can be turned on with low loss. This is due to an increase in mobility and an increase in inversion layer electron concentration at the recess interface 20c.

<Board>
In the present embodiment, the substrate 1 may be a conventionally known substrate as long as it is a substrate 1 used for a field effect transistor. Examples of such a substrate material include Si, GaN, SiC, AlN, GaAs, and ZnO.

<Underlying semiconductor layer>
In the present embodiment, it is preferable to provide base semiconductor layer 2 between substrate 1 and first nitride semiconductor layer 11. By providing the base semiconductor layer 2 in this manner, distortion between the crystal lattice of the substrate 1 and the crystal lattice of the first nitride semiconductor layer 11 can be relaxed. Note that if the substrate 1 has a role equivalent to that of the base semiconductor layer, the base semiconductor layer may not be formed by regarding the substrate 1 as the base semiconductor layer. That is, a structure in which the first nitride semiconductor layer 11 is directly laminated on the substrate 1 is also included in the scope of the present invention.

  Such a base semiconductor layer 2 may be either a single layer or a plurality of layers. When the underlying semiconductor layer 2 is a single layer, for example, AlN, GaN, AlGaN or the like can be used as the material. On the other hand, when the base semiconductor layer 2 includes a plurality of layers, an AlN / GaN multilayer, an AlGaN / GaN multilayer, or the like can be used for the base semiconductor layer 2. The underlying semiconductor layer 2 is preferably a multiple layer in which a thick undoped GaN layer is stacked on a thin undoped AlN layer. Note that the expression “GaN / AlN” indicates that the upper surface is GaN and the lower surface is AlN.

<Nitride semiconductor layer>
In the present embodiment, a nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer 11 may be formed between the base semiconductor layer 2 and the first nitride semiconductor layer 11. Thus, by providing the nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer 11 between the base semiconductor layer 2 and the first nitride semiconductor layer 11, the nitride semiconductor layer and the first nitride are provided. Negative polarization charges can be generated at the heterojunction interface with the semiconductor layer 11. Thus, polarization charges are generated, and the conduction band at the heterojunction interface is discontinuous, whereby a barrier can be formed against electrons.

  As a result, even when a high bias voltage is applied between the source electrode 6 and the drain electrode 7 during the off operation, a path through which electrons in a region away from the heterojunction interfaces 16a and 16b flow can be blocked. Thus, the leakage current flowing between the source electrode 6 and the drain electrode 7 can be suppressed.

Examples of the material used for such a nitride semiconductor layer include GaN, AlGaN, InAlGaN, and InGaN. Such a material may be doped with impurities so as to be p-type or i-type. Here, when AlGaN is used as the material used for the nitride semiconductor layer, the ratio of the number of Al atoms to the number of Ga atoms is not particularly limited and may be any ratio, for example, undoped Al _0.05 Ga _0.95 N can be used.

<First nitride semiconductor layer>
In the group III nitride field effect transistor of the present embodiment, the first nitride semiconductor layer 11 is preferably an undoped or doped nitride semiconductor such as GaN, AlGaN, InGaN, AlInN, and AlGaInN. It is more preferable that In _1-x Ga _x N (0 <x ≦ 1).

  More preferably, the first nitride semiconductor layer 11 is doped with impurities so that it is either a p-type nitride semiconductor or an i-type nitride semiconductor. Thus, by doping the first nitride semiconductor layer 11 with impurities, the threshold voltage can be controlled to a desired value. From the viewpoint of obtaining a field effect transistor having a higher threshold voltage, the first nitride semiconductor layer 11 is preferably a p-type nitride semiconductor.

  In addition, by doping the first nitride semiconductor layer 11 with the p-type impurity, the depletion layer extends above and below the nitride semiconductor stacked body 100 during the off operation, and the pressure resistance of the group III nitride field effect transistor is increased. Can be improved.

  Here, as the p-type impurity for doping the first nitride semiconductor layer 11, any dopant can be used as long as it is an impurity that can make the nitride semiconductor p-type or i-type, for example, Mg Zn, C, Fe, or the like can be used.

The hole concentration contained in the first nitride semiconductor layer 11 is preferably 1 × 10 ¹⁷ cm ⁻³ or less. By setting such a hole concentration, the threshold voltage can be controlled to a desired value, and the pressure resistance during the off operation of the group III nitride field effect transistor can be improved. In addition, by containing holes at the above concentration in the first nitride semiconductor layer 11, scattering of carriers traveling on the recess interface 20c can be suppressed as much as possible.

<Second nitride semiconductor layer>
In the present embodiment, the second nitride semiconductor layers 12a and 12b preferably have the same forbidden band width as the first nitride semiconductor layer 11, and when the first nitride semiconductor layer 11 is made of GaN, The nitride semiconductor layers 12a and 12b are also preferably made of GaN. Such second nitride semiconductor layers 12a and 12b may be either single-layer or multilayer nitride semiconductor layers. When the second nitride semiconductor layers 12a and 12b are formed of a single nitride semiconductor layer, undoped AlGaN or doped AlGaN, AlInN, AlGaInN, or the like may be used.

On the other hand, when the second nitride semiconductor layers 12a and 12b are formed of multiple nitride semiconductor layers, a multiple AlGaN layer including a plurality of AlGaN layers having different Al composition ratios and doping concentrations, GaN / Al _0.25 Ga _0.75 N / AlN, GaN / AlGaN, InGaN / AlGaN, InGaN / AlGaN / AlN, etc. may be used. It should be noted that other doped nitride semiconductor layers can be used for each layer constituting the multilayer nitride semiconductor layer.

  The second nitride semiconductor layers 12a and 12b preferably have a thickness of 30 nm or more. This is because the distance from the heterojunction interfaces 15a and 15b between the first nitride semiconductor layer 11 and the second nitride semiconductor layers 12a and 12b to the two-dimensional electron gases 14a and 14b is set to 30 nm or more, thereby forming two-dimensional electrons. This is because the carrier mobility of the gases 14a and 14b can be improved.

<Third nitride semiconductor layer>
In the present embodiment, the third nitride semiconductor layers 13a and 13b are barrier layers having a wider forbidden band width than the forbidden band widths of the first nitride semiconductor layer 11 and the second nitride semiconductor layers 12a and 12b. is there. Such third nitride semiconductor layers 13a and 13b are preferably multi-nitride semiconductor layers, and the material of each layer constituting the multi-nitride semiconductor layers is undoped such as GaN, AlGaN, InGaN, AlInN, AlGaInN, etc. Alternatively, a doped nitride semiconductor or the like can be used. As the third nitride semiconductor layers 13a and 13b, for example, those containing undoped GaN / Al _0.25 Ga _0.75 N / AlN in a thickness of 1 nm / 22 nm / 1 nm, respectively, from the top can be used.

<Source electrode, drain electrode>
In the present embodiment, the source electrode 6 and the drain electrode 7 are preferably formed of a single layer or a multilayer metal layer. Examples of the electrode material used for the source electrode 6 and the drain electrode 7 include Ti / Al, Ni / Au, Ti / Au, Pt / Au, Ni / Au, W, WN _x , and WSi _x .

<Gate electrode>
In the present embodiment, the gate electrode 8 is an electrode that controls the concentration of electrons at the recess interface 20 c where the insulating film 9 and the first nitride semiconductor layer 11 are in contact. By adjusting the bias voltage applied to the gate electrode 8, the electron concentration at the recess interface 20c can be controlled, and the channel formation can be controlled. Examples of the metal material used for the gate electrode 8 include Ti / Al, Ni / Au, Ti / Au, Pt / Au, Ni / Au, W, WN _x , and WSi _x .

<Insulating film>
In the present embodiment, the insulating film 9 formed on the inner surface of the recess region and the upper surfaces of the third nitride semiconductor layers 13a and 13b is not limited to a single layer film but may be a multilayer film. That is, when the insulating film 9 is formed of a single layer film, SiO ₂ , SiN _x , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , TiO ₂ , TaO _x , MgO, Ga ₂ O ₃ , MgF ₂ or the like may be used. it can. By using SiO ₂ as the insulating film 9, the insulating film 9 is easily stabilized. Further, by using SiN _x as the insulating film 9, the electron mobility at the recess interface 20c can be increased.

When the insulating film 9 is composed of a plurality of films, a structure such as SiN _x / SiO ₂ , SiO ₂ / SiN _x , SiN _x / SiO ₂ / SiN _x can be used. Note that the expression “SiO ₂ / SiN _x ” indicates that the upper surface is SiO ₂ and the lower surface is SiN _x . By using a plurality film made of SiO ₂ / SiN _x as the insulating film 9, easily suppressed collapse phenomenon by SiN _x in contact with the recess surface 20c, it is possible to obtain a higher electron mobility, by SiO ₂ thereon Stability can be obtained.

<Recess area>
In the present embodiment, the side surface of the recess region 20 is shown to be formed perpendicular to the surfaces of the first nitride semiconductor layer 11 and the second nitride semiconductor layers 12a and 12b. The side surface of the recess region 20 may be inclined with respect to the surfaces of the first nitride semiconductor layer 11 and the second nitride semiconductor layers 12a and 12b.

(Production method)
The group III nitride field effect transistor of the present embodiment can be manufactured as follows.

  FIG. 2 is a schematic cross-sectional view showing a state after the first nitride semiconductor layer is formed on the substrate. In the present embodiment, as shown in FIG. 2, the base semiconductor layer 2 and the first nitride semiconductor layer are formed on the substrate 1 using a metal organic chemical vapor deposition (MOCVD) method. 11 are stacked in this order.

  FIG. 3 is a schematic cross-sectional view showing the substrate after the selective growth mask is formed on a part of the first nitride semiconductor layer 11. Next, as shown in FIG. 3, a selective growth mask 50 is formed on part of the first nitride semiconductor layer 11. Here, the selective growth mask 50 is formed by forming a protective film on the first nitride semiconductor layer 11 using the CVD method and then removing unnecessary portions of the protective film by etching. 50 is formed. Note that the selective growth mask 50 may be formed using a sputtering method or the like.

Further, as a material used for the selective growth mask 50, SiO ₂ , SiN _x or the like can be used, and SiO ₂ / SiN _x may be used. Here, when SiO ₂ and / or SiN _x is used as the protective film, an unnecessary portion as the selective growth mask 50 can be easily removed by etching with hydrofluoric acid diluted with hydrofluoric acid or ammonium fluoride.

  FIG. 4 is a schematic cross-sectional view showing a state after the nitride semiconductor multilayer body is formed on the substrate. Next, as shown in FIG. 4, the second nitride semiconductor layers 12a and 12b and the third nitride semiconductor are formed on the portion of the first nitride semiconductor layer 11 where the selective growth mask 50 is not formed. Layers 13a and 13b are formed.

Here, the second nitride semiconductor layers 12a and 12b and the third nitride semiconductor layers 13a and 13b are formed by MOCVD using, for example, trimethylgallium (TMG), trimethylammonium (TMA), or ammonia (NH ₃ ). It can be formed by a molecular beam epitaxy (MBE) method, a halide vapor phase epitaxy (HVPE) method, or the like. Then, after forming the third nitride semiconductor layers 13a and 13b, the selective growth mask 50 is removed to form the recess region 20.

  Next, the inner surface of the recess region 20 and the upper surfaces of the third nitride semiconductor layers 13a and 13b are washed with sulfuric acid / hydrogen peroxide solution, and further washed with hydrochloric acid / hydrogen peroxide solution.

  FIG. 5 is a schematic cross-sectional view showing a state after an insulating film is formed on the inner surface of the recess region 20 and the upper surfaces of the third nitride semiconductor layers 13a and 13b. In the present embodiment, as shown in FIG. 5, insulating film 9 is formed on the inner surface of recess region 20 and the upper surfaces of third nitride semiconductor layers 13a and 13b.

  FIG. 6 is a schematic cross-sectional view showing a state after the contact region is formed in the insulating film. As shown in FIG. 6, the portion of the insulating film 9 on the upper surface of the third nitride semiconductor layers 13a and 13b where the source and drain electrodes are to be formed is removed by photolithography. Then, by performing annealing at 400 ° C. to 1100 ° C. in a nitrogen atmosphere, the interface state of the surface where the insulating film 9 and the nitride semiconductor multilayer body 100 are in contact is reduced.

  Thereafter, the source electrode 6 and the drain electrode 7 are formed on the third nitride semiconductor layers 13a and 13b where the insulating film 9 has been removed using the photolithography technique and the EB vapor deposition method (FIG. 7). FIG. 7 is a schematic cross-sectional view showing a state after forming the source electrode and the drain electrode.

  Then, the source electrode 6 and the drain electrode 7 and the channel are brought into ohmic contact by alloying by heat treatment. The method of obtaining the ohmic contact is not limited to the method of alloying by heat treatment, but a method of forming an ohmic contact by a tunnel current mechanism, an n-type impurity such as Si in the contact region 25 by ion implantation, or the like. For example, a method of forming the source electrode 6 and the drain electrode 7 in the contact region 25 after doping at a high concentration can be used.

  Next, the gate electrode 8 made of Ni / Au is formed on the insulating film by using a photolithography technique and an EB vapor deposition method. Through the above steps, as shown in FIG. 1, the group III nitride field effect transistor of the present embodiment can be manufactured.

  In the conventional group III nitride field effect transistor, the first nitride semiconductor layer, the second nitride semiconductor layer, and the third nitride semiconductor layer are formed, and then the second nitride semiconductor layer and the third nitride are formed. The semiconductor layer was removed by dry etching to form a recess region. For this reason, the first nitride semiconductor layer at the recess interface may be damaged by dry etching, and the surface roughness of the first nitride semiconductor layer may be large. As a result, the mobility in the recess region is lowered, and there is a problem that the on-resistance of the group III nitride field effect transistor is increased.

  In the group III nitride field effect transistor of the present embodiment, the recess region 20 can be formed without exposing the recess interface 20c to dry etching. Accordingly, a group III nitride field effect transistor can be produced in which the first nitride semiconductor layer 11 in contact with the recess interface 20c is not damaged by dry etching and the surface roughness is not deteriorated by dry etching. As a result, the on-resistance of the group III nitride field effect transistor can be made difficult to increase.

(Embodiment 2)
The group III nitride field effect transistor of the present embodiment is a group III nitride having the same configuration as that of the first embodiment except that a p-type nitride semiconductor is used as the first nitride semiconductor layer 11 of the first embodiment. It is a physical field effect transistor.

  When a p-type nitride semiconductor is used as the first nitride semiconductor layer 11, a p-type ohmic electrode that is in ohmic contact with the first nitride semiconductor layer 11 is formed in addition to the source electrode 6 and the drain electrode 7 that are in ohmic contact with the channel. Is preferred. By forming the p-type ohmic electrode in this manner, even when the group III nitride field effect transistor is turned off, holes located under the gate electrode are easily driven out of the depletion layer. Further, by forming a p-type ohmic electrode, when the group III nitride field effect transistor is turned on, holes can be quickly formed under the gate electrode 8 even if the nitride semiconductor stacked body has a wide band gap. Can be collected. Thus, a group III nitride field effect transistor with good switching characteristics can be produced by allowing holes to be taken in and out quickly.

(Production method)
The manufacturing method of the group III nitride field effect transistor of the present embodiment is the same as that of the first embodiment, except that a p-type nitride semiconductor is formed as the first nitride semiconductor layer 11. A group III nitride field effect transistor is fabricated.

  Thus, by using the first nitride semiconductor layer 11 made of a p-type nitride semiconductor, the threshold voltage can be improved, and the threshold voltage can be controlled by the p-type concentration.

  Moreover, it is preferable to perform annealing for activating the p-type dopant contained in the first nitride semiconductor layer 11 after forming the third nitride semiconductor layers 13a and 13b. Thus, the threshold voltage can be improved by activating the p-type dopant contained in the first nitride semiconductor layer 11 by annealing.

(Embodiment 3)
The group III nitride field effect transistor of the present embodiment is characterized in that the forbidden band width of the first nitride semiconductor layer 11 is smaller than the forbidden band widths of the second nitride semiconductor layers 12a and 12b. As described above, by using the first nitride semiconductor layer 11 smaller than the forbidden band width of the second nitride semiconductor layers 12a and 12b, the activation rate of the p-type increases, and the concentration of the p-type impurity is smaller. A higher p-type carrier concentration can be obtained.

  Depending on the composition ratio, thickness, and carrier concentration of the second nitride semiconductor layers 12a and 12b as described above, a heterojunction is formed at the interface between the first nitride semiconductor layer 11 and the second nitride semiconductor layers 12a and 12b. Although carriers may be formed at the interfaces 15a and 15b, it is more preferable because the overall carrier concentration of the group III nitride field effect transistor increases.

(Production method)
The manufacturing method of the group III nitride field effect transistor of the present embodiment is different in that the first nitride semiconductor layer 11 smaller than the forbidden band width of the second nitride semiconductor layers 12a and 12b is different. A group III nitride field effect transistor is fabricated by the same manufacturing method as in the first embodiment.

The group III nitride field effect transistor of Example 1 was produced as follows.
In this example, first, a substrate 1 made of Si was prepared. Then, as shown in FIG. 2, an underlying semiconductor layer 2 made of AlN and GaN having a thickness of 1000 nm is formed on the substrate 1 by using a metal organic chemical vapor deposition (MOCVD) method. A nitride semiconductor layer (not shown) made of undoped Al _0.05 Ga _0.95 N and a first nitride semiconductor layer 11 made of an undoped GaN layer having a thickness of 100 nm were stacked in this order.

Next, a SiO ₂ film was formed on the first nitride semiconductor layer 11 using the CVD method. Then, using a photolithography technique, the SiO ₂ film other than the portion that becomes the recess region in a later process was removed. FIG. 3 is a schematic cross-sectional view showing the substrate after the selective growth mask is formed on a part of the first nitride semiconductor layer 11. As shown in FIG. 3, the portion of the SiO ₂ film that has not been removed becomes the selective growth mask 50.

Next, on the portion of the first nitride semiconductor layer 11 where the selective growth mask 50 is not formed and the first nitride semiconductor layer 11 is exposed, the second nitride semiconductor layer 12a is formed by regrowth. , 12b and third nitride semiconductor layers 13a, 13b. The second nitride semiconductor layers 12a and 12b were made of undoped GaN and had a thickness of 50 nm. The third nitride semiconductor layers 13a and 13b have a three-layer structure of undoped GaN / Al _0.25 Ga _0.75 N / AlN, and the thicknesses were 1 nm / 22 nm / 1 nm, respectively. Then, after forming the third nitride semiconductor layers 13a and 13b, the selective growth mask 50 is removed to form the recess region 20.

Next, the inner surface of the recess region 20 and the upper surfaces of the third nitride semiconductor layers 13a and 13b were washed with sulfuric acid / hydrogen peroxide solution, and further washed with hydrochloric acid / hydrogen peroxide solution. Then, an insulating film 9 made of SiO ₂ having a thickness of 30 nm was formed on the inner surface of the recess region 20 and the upper surfaces of the third nitride semiconductor layers 13a and 13b by using the CVD method.

  Then, the insulating film 9 on the upper surfaces of the third nitride semiconductor layers 13a and 13b where the source electrode and the drain electrode are formed is removed by photolithography, and the contact region 25 is manufactured. Then, annealing was performed at 1000 degrees under a nitrogen atmosphere, so that the interface state of the surface in contact with the insulating film 9 and the nitride semiconductor multilayer body 100 was reduced.

  Thereafter, the source electrode 6 made of Ti / Al and the drain electrode 7 having the same composition as the source electrode 6 are formed in the contact region 25 of the third nitride semiconductor layers 13a and 13b by using the photolithography technique and the EB vapor deposition method. did. Then, the source electrode 6 and the drain electrode 7 were brought into ohmic contact with the two-dimensional electron gases 14a and 14b by performing heat treatment in a vacuum atmosphere at 800 degrees for 1 minute.

  Next, the gate electrode 8 made of Ni / Au was formed on the insulating film 9 by using a photolithography technique and an EB vapor deposition method. Through the above steps, the group III nitride field effect transistor of this example was fabricated.

  In the group III nitride field effect transistor of Example 1 manufactured as described above, the first nitride semiconductor layer 11 in contact with the recess interface 20c is not damaged by dry etching, and the surface roughness is deteriorated by dry etching. There is no. In addition, there was no step between the upper surface of the first nitride semiconductor layer in contact with the insulating film and the upper surface of the first nitride semiconductor layer in contact with the second nitride semiconductor layer. Therefore, the on-resistance of the group III nitride field effect transistor was low.

In this example, a p-type GaN layer doped with Mg at a concentration of 1 × 10 ¹⁹ cm ⁻³ was used as the first nitride semiconductor layer 11 of the group III nitride field effect transistor of Example 1. 3 is a group III nitride field effect transistor having the same configuration as in Example 1. Here, the hole concentration contained in the first nitride semiconductor layer was 1 × 10 ¹⁷ cm ⁻³ . The first nitride semiconductor layer 11 made of p-type GaN is doped with the p-type impurity Mg at a concentration of 1 × 10 ¹⁹ cm ^−3. The hole concentration of GaN is 1 × 10 ¹⁷ cm ⁻³ .

(Production method)
In the group III nitride field effect transistor of this example, a p-type GaN layer doped with Mg at a concentration of 1 × 10 ¹⁹ cm ⁻³ was formed as the first nitride semiconductor layer, and the third nitridation A group III nitride field effect transistor was manufactured by the same manufacturing method as in Example 1 except that annealing for activating the p-type dopant was performed after the formation of the semiconductor layers 13a and 13b.

Example 3 uses p-type In _0.1 Ga _0.9 N doped with Mg at a concentration of 1 × 10 ¹⁸ cm ⁻³ as the first nitride semiconductor layer 11 of the group III nitride field effect transistor of Example 1. The other structure is a group III nitride field effect transistor having the same configuration as that of the first embodiment. Here, the hole concentration contained in the first nitride semiconductor layer was 1 × 10 ¹⁷ cm ⁻³ . Thereby, the activation rate of the p-type conversion of the first nitride semiconductor layer 11 is increased, and the same p-type carrier concentration can be obtained with a lower concentration of p-type impurities.

(Production method)
In the group III nitride field effect transistor of this example, a p-type In _0.1 Ga _0.9 N layer doped with Mg at a concentration of 1 × 10 ¹⁸ cm ⁻³ was formed as the first nitride semiconductor layer. A group III nitride field effect transistor is manufactured by the same manufacturing method as in Example 1 except that annealing for activating the p-type dopant is performed after forming the third nitride semiconductor layers 13a and 13b. Manufactured.

(Comparative Example 1)
The group III nitride field effect transistor of Comparative Example 1 was produced as follows.

FIG. 8 is a schematic cross-sectional view showing a state after the nitride semiconductor multilayer body is formed on the substrate. First, a base semiconductor layer 202 made of AlN and GaN, a nitride semiconductor layer made of undoped Al _0.05 Ga _0.95 N (not shown) having a thickness of 1000 nm, a thickness on a substrate 201 made of Si using MOCVD. First nitride semiconductor layer 211 made of 100 nm undoped GaN layer, second nitride semiconductor layer 212 made of undoped GaN having a thickness of 50 nm, and undoped GaN / Al _0.25 Ga _0.75 N each having a thickness of 1 nm / 22 nm / 1 nm The nitride semiconductor multilayer body 200 shown in FIG. 3 was formed by laminating the third nitride semiconductor layer 213 made of / AlN in this order.

Next, a SiO ₂ film was formed on the third nitride semiconductor layer 213 using the CVD method. Then, by using a photolithography technique, a portion of the SiO ₂ film that becomes a recess region in a later process was removed, and the third nitride semiconductor layer was exposed. FIG. 9 is a schematic cross-sectional view showing a state after the recess region is formed by etching. Thereafter, as shown in FIG. 9, the second nitride semiconductor layer 212 and the third nitride semiconductor layer 213 are removed by etching from the portion where the surface of the third nitride semiconductor layer 213 is exposed, thereby forming a recess. Region 220 was formed.

  FIG. 10 is a schematic cross-sectional view showing an example of a group III nitride field effect transistor of Comparative Example 1. Thereafter, an insulating film 209, a source electrode 206, a drain electrode 207, and a gate electrode 208 are formed by the same method as in Example 1, and the Group III nitride field effect transistor of Comparative Example 1 shown in FIG. Produced.

  In the group III nitride field effect transistor of Comparative Example 1, since the recess region 220 is formed by etching, the first nitride semiconductor layer 211 in contact with the recess interface 220c is damaged by dry etching, and the surface roughness is deteriorated. is doing. In addition, a part of the first nitride semiconductor layer is removed by dry etching, and the upper surface of the first nitride semiconductor layer in contact with the insulating film and the upper surface of the first nitride semiconductor layer in contact with the second nitride semiconductor layer There is a difference in level. For this reason, the on-resistance of the group III nitride field effect transistor was high.

  As is apparent from the above description, the group III nitride field effect transistors according to the present invention of Examples 1 to 3 have lower on-resistance than the group III nitride field effect transistor of Comparative Example 1. Obviously. From this, it was confirmed that the on-resistance can be lowered by not using etching when forming the recess region of the group III nitride field effect transistor.

  Although the embodiments and examples of the present invention have been described as described above, it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments and examples.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1,201 Substrate, 2,202 Base semiconductor layer, 6,206 Source electrode, 7,207 Drain electrode, 8,208 Gate electrode, 9,209 Insulating film, 11, 211 First nitride semiconductor layer, 12a, 12b, 212 Second nitride semiconductor layer, 13a, 13b, 213 Third nitride semiconductor layer, 14a, 14b Two-dimensional electron gas, 15a, 15b, 16a, 16b Heterojunction interface, 20,220 Recess region, 20c, 220c Recess interface , 25 contact region, 50 selective growth mask, 100, 200 nitride semiconductor laminate.

Claims (11)

An underlying semiconductor layer;
A nitride semiconductor stacked body in which a first nitride semiconductor layer, a second nitride semiconductor layer, and a third nitride semiconductor layer are sequentially stacked on the base semiconductor layer;
A source electrode and a drain electrode in contact with an upper surface of the nitride semiconductor multilayer body;
A recess region that is a region where the second nitride semiconductor layer and the third nitride semiconductor layer are not formed in the nitride semiconductor multilayer body between the source electrode and the drain electrode;
An insulating film formed on the inner surface of the recess region and the upper surface of the nitride semiconductor multilayer body;
A gate electrode formed on the insulating film,
The third nitride semiconductor layer has a wider band gap than the first nitride semiconductor layer and the second nitride semiconductor layer,
A group III nitride field effect transistor having no step between an upper surface of the first nitride semiconductor layer in contact with the insulating film and an upper surface of the first nitride semiconductor layer in contact with the second nitride semiconductor layer.   The III of claim 1, wherein there is no difference in surface roughness between an upper surface of the first nitride semiconductor layer in contact with the insulating film and an upper surface of the first nitride semiconductor layer in contact with the second nitride semiconductor layer. Group nitride field effect transistor.   3. The group III nitride field effect transistor according to claim 1, wherein the first nitride semiconductor layer is made of a p-type nitride semiconductor or an i-type nitride semiconductor. 4. The group III nitride field effect transistor according to claim 3, wherein a hole concentration contained in the first nitride semiconductor layer is 1 × 10 ¹⁷ cm ⁻³ or less.   5. The group III nitride field effect transistor according to claim 1, wherein the first nitride semiconductor layer and the second nitride semiconductor layer are GaN. 5. The group III nitride field effect transistor according to claim 1, wherein the first nitride semiconductor layer is In _x Ga _1-x N (0 <x ≦ 1).   The group III nitride field effect transistor according to any one of claims 1 to 6, wherein a thickness of the second nitride semiconductor layer is 30 nm or more.   The group III nitride field effect transistor according to any one of claims 1 to 7, wherein the second nitride semiconductor layer and the third nitride semiconductor layer are formed by using a regrowth method. Forming a first nitride semiconductor layer on the underlying semiconductor layer;
Forming a selective growth mask on a portion of the first nitride semiconductor layer;
Forming a second nitride semiconductor layer and a third nitride semiconductor layer on the first nitride semiconductor layer on which the selective growth mask is not formed;
Removing the selective growth mask to expose a part of the first nitride semiconductor layer to form a recess region;
Forming an insulating film on the inner surface of the recess region and the third nitride semiconductor layer. A method for manufacturing a group III nitride field effect transistor.   The method of manufacturing a group III nitride field effect transistor according to claim 9, further comprising a step of cleaning the inner surface of the recess region and the third nitride semiconductor layer after the step of removing the selective growth mask.   The method of manufacturing a group III nitride field effect transistor according to claim 9 or 10, comprising a step of annealing the insulating film.

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