JP2015106627A - Semiconductor laminated substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor laminated substrate capable of suppressing generation of a two-dimentional carrier gas that can be a lateral direction leakage source.SOLUTION: A semiconductor laminated substrate comprises first, second, third, and fourth semiconductor layers of nitride semiconductor. The second semiconductor layer is arranged above the first semiconductor layer, and the third semiconductor layer is arranged on an upper surface of the second semiconductor layer, and the fourth semiconductor layer is arranged on an upper surface of the first semiconductor layer and below the second semiconductor layer, respectively. Bandgaps of the second and fourth semiconductor layers are respectively smaller than that of the first semiconductor layer, and a bandgap of the third semiconductor layer is larger than that of the second semiconductor layer. The second and third semiconductor layers form a heterojunction, and are configured so that a first two-dimentional carrier gas layer can be generated on a lower layer side of an interface between the second and third semiconductor layers. Bandgaps are substantially the same as each other from the second semiconductor layer to the fourth semiconductor layer. The first and fourth semiconductor layer form a heterojunction. Impurities with the same conductivity type as a carrier that forms the first two-dimentional carrier gas layer exist in the fourth semiconductor layer.

Description

  The present invention relates to a semiconductor multilayer substrate used for a semiconductor switching element typified by HEMT (High Electron Mobility Transistor).

  In recent years, nitride semiconductors, which are III-V group compound semiconductors represented by gallium nitride (GaN), are expected to be applied to switching elements such as power devices. This is because nitride semiconductors have a large band gap of about 3.4 eV, a dielectric breakdown electric field of about 10 times, and an electron saturation speed of about 2.5 times that of conventional semiconductors using silicon (Si). This is because it has characteristics suitable for power devices, such as being large.

For example, a switching element is proposed in which a GaN / AlGaN heterostructure is provided on a substrate such as silicon carbide (SiC), sapphire (Al ₂ O ₃ ), or silicon (Si). In the power device, in addition to the spontaneous polarization due to the asymmetric structure in the C-axis direction of the crystal structure of GaN (wurtzite type), the polarization due to the piezoelectric effect due to lattice mismatch of AlGaN and GaN results in 1 × 10 ¹² A two-dimensional electron gas layer having a high electron density of about cm ⁻² to 1 × 10 ¹³ cm ⁻² is generated. The switching element controls the electron density of the two-dimensional electron gas layer so that predetermined electrodes are electrically connected (on state) and predetermined electrodes are not electrically connected ( (Off state).

  An example of a cross-sectional structure of the switching element is shown in FIG. 9 includes a substrate 101, a buffer layer 102 formed on the upper surface of the substrate 101, and non-doped GaN which is formed on the upper surface of the buffer layer 102 and is not intentionally doped with impurities. A semiconductor crystal substrate 105 composed of an electron transit layer 103 and an electron supply layer 104 made of AlGaN formed on the upper surface of the electron transit layer 103, and a source electrode 106 and a drain electrode formed on the upper surface of the electron supply layer 104 107 and a gate electrode 108 formed between the source electrode 106 and the drain electrode 107. In some cases, the gate electrode 108 is formed on the upper surface of the electron supply layer 104 via the gate insulating film 109 in order to suppress the gate leakage current, and the structure illustrated in FIG.

The switching element 100 is a normally-on element, and even when the potential of the gate electrode 108 is the same as that of the source electrode 106 (the voltage between both electrodes is 0 V), the gate electrode 108 is applied with a voltage. Even in a floating state that is not performed, the two-dimensional electron gas layer 110 is generated at the interface of the electron transit layer 103 in contact with the electron supply layer 104 and is turned on. By making the potential of the drain electrode 107 higher than that of the source electrode 106, a current flows between the drain electrode 107 and the source electrode 106.

  On the other hand, when the potential of the gate electrode 108 is set to a negative potential lower than the threshold voltage with respect to the potential of the source electrode 106, 2 below the interface of the electron transit layer 103 contacting the electron supply layer 104 below the gate electrode 108. The three-dimensional electron gas layer 110 is not generated and is turned off. In this state, no current flows between the drain electrode 107 and the source electrode 106.

  As shown in FIG. 10, a pressure-resistant layer 111 having a carbon concentration higher than that of the electron transit layer 103 may be inserted between the electron transit layer 103 and the buffer layer 102 as necessary (for example, Patent Document 1). Etc.). By providing the withstand voltage layer 111, it is expected that the withstand voltage in the vertical direction and the horizontal direction of the switching element is improved and the leakage current is suppressed.

JP 2010-245504 A

  However, there are concerns about the following problems in switching elements using the above-described semiconductor multilayer substrate.

  The buffer layer 102 is composed of a superlattice layer in which several tens of layers having different Al compositions are combined and periodically laminated to several tens layers, and several layers having different compositions so that the Al composition becomes lower toward the upper layer. There are cases where the inclined buffer layers are laminated, and cases where both are combined. What can be said in common is that the buffer layer 102 has a larger Al composition and a larger band gap than the electron transit layer 103.

  Therefore, the two-dimensional hole gas layer 112 is formed at the interface of the electron transit layer 103 in contact with the buffer layer 102 in the same manner as the two-dimensional electron gas layer 110 is generated at the interface of the electron transit layer 103 in contact with the electron supply layer 104. Occurs (see FIG. 11A). In the case of the structure having the breakdown voltage layer 111 described in Patent Document 1 (see FIG. 10), when the band gap between the electron transit layer 103 and the breakdown voltage layer 111 is the same or substantially the same, the gap between the breakdown voltage layer 111 and the buffer layer 102 is A heterojunction interface having a large band gap difference is formed, and a two-dimensional hole gas layer 112 is generated on the pressure-resistant layer 111 side of the heterojunction interface (see FIG. 12).

  The two-dimensional hole gas layer 112 is not eliminated by the depletion layer 113 formed below the gate electrode 108 even when the switching element is in an off state (see FIG. 11B). Therefore, the two-dimensional hole gas layer 112 may cause a lateral leak between the source electrode 106 and the drain electrode 107.

  As described in Patent Document 1, when a semiconductor laminated substrate having a pressure-resistant layer containing a lot of carbon is used, the carbon atom has a radius close to that of the nitrogen atom, so that the carbon atom fills the nitrogen defect in the pressure-resistant layer. In many cases, holes are supplied by the carbon atoms. Therefore, the hole density of the two-dimensional hole gas layer 112 becomes higher, and the lateral leakage may be deteriorated.

  Even when the two-dimensional carrier gas layer generated at the interface of the electron transit layer 103 in contact with the electron supply layer 104 is not a two-dimensional electron gas layer but a two-dimensional hole gas layer, the electron transit layer 103 or the pressure-resistant layer is used. Since a two-dimensional electron gas layer that is not rejected by the depletion layer 113 may be generated at the interface of the buffer layer 102 in contact with the buffer layer 102 even when the switching element is in an OFF state, it may cause a lateral leakage as described above. There is.

  In view of the above problems, an object of the present invention is to provide a semiconductor laminated substrate in which generation of a two-dimensional carrier gas that can be a lateral leakage source is suppressed.

  In order to achieve the above object, the present invention includes first, second, third and fourth semiconductor layers of nitride semiconductor, the second semiconductor layer being disposed above the first semiconductor layer, Three semiconductor layers are disposed on the upper surface of the second semiconductor layer, the fourth semiconductor layer is disposed on the upper surface of the first semiconductor layer and below the second semiconductor layer, and the second semiconductor layer and The band gap of the fourth semiconductor layer is smaller than that of the first semiconductor layer, the band gap of the third semiconductor layer is larger than that of the second semiconductor layer, and the second semiconductor layer and the third semiconductor layer are heterojunction. The first two-dimensional carrier gas layer is configured to be generated on the second semiconductor layer side of the interface between the second and third semiconductor layers, the lower surface side interface of the second semiconductor layer, and the fourth Semiconductor on the other side at the upper surface side interface of the semiconductor layer There is no band gap difference between the first layer and the first two-dimensional carrier gas layer, or the second two-dimensional carrier gas layer having a conductivity opposite to that of the first two-dimensional carrier gas layer cannot be generated. A semiconductor having a heterojunction between a first semiconductor layer and the fourth semiconductor layer, and an impurity having the same conductivity type as a carrier forming the first two-dimensional carrier gas layer is present in the fourth semiconductor layer. A multilayer substrate is provided.

  In the semiconductor laminated substrate having the above characteristics, the first semiconductor layer and the second semiconductor layer are directly heterojunctioned by inserting the fourth semiconductor layer on the upper surface of the first semiconductor layer and below the second semiconductor layer. The first two-dimensional carrier gas layer generated on the second semiconductor layer side of the interface between the second and third semiconductor layers, which may be generated in the vicinity of the second semiconductor layer side of the interface. The second two-dimensional carrier gas layer of the mold does not occur at the lower surface side interface of the second semiconductor layer and the upper surface side interface of the fourth semiconductor layer, and the fourth semiconductor layer at the interface between the first and fourth semiconductor layers It may occur when moving to the side. However, an impurity having the same conductivity type as that of the carrier forming the first two-dimensional carrier gas layer is present at a place where the second two-dimensional carrier gas layer may be generated. The carriers in the second two-dimensional carrier gas layer cancel each other because they are oppositely conductive, so that the carrier density in the second two-dimensional carrier gas layer decreases, and the second two-dimensional carrier gas layer Electrical conductivity is greatly reduced. Therefore, by using the semiconductor multilayer substrate having the above characteristics, lateral leakage due to the second two-dimensional carrier gas layer is suppressed.

  When the first two-dimensional carrier gas layer is, for example, a two-dimensional electron gas layer, the second two-dimensional carrier gas layer is a two-dimensional hole gas layer, and the interface between the first and fourth semiconductor layers. Impurities existing on the fourth semiconductor layer side are n-type impurities.

  More preferably, in the semiconductor multilayer substrate having the above characteristics, the impurity includes an impurity added in the formation process of the fourth semiconductor layer.

  Specifically, since the impurity is present by intentional doping or the like to the fourth semiconductor layer, the concentration of the impurity is appropriately set according to the carrier density of the second two-dimensional carrier gas layer. Can be adjusted.

  More preferably, the semiconductor multilayer substrate having the above characteristics is formed on an upper surface of the fourth semiconductor layer and below the second semiconductor layer, and has a band gap smaller than that of the first semiconductor layer, and the second semiconductor layer. A fifth semiconductor layer of a nitride semiconductor having a higher carbon concentration is further provided.

  By providing the fifth semiconductor layer, it is expected that the breakdown voltage in the vertical direction and the horizontal direction is improved and the leakage current is suppressed in the switching element using the semiconductor laminated substrate. However, when the second two-dimensional carrier gas layer is a two-dimensional hole gas layer, as described above, hole supply from the fifth semiconductor layer to the two-dimensional hole gas layer can occur, so that the two-dimensional positive gas layer is generated. The hole density of the hole gas layer may increase. However, in this semiconductor multi-layer substrate, impurities of a conductivity type opposite to the carriers of the second two-dimensional carrier gas layer (two-dimensional hole gas layer) (n Type impurity), the increase in the hole density of the two-dimensional hole gas layer can be suppressed and further reduced. Thereby, the disadvantages caused by providing the fifth semiconductor layer can be eliminated, and the benefits of providing the fifth semiconductor layer can be enjoyed.

  More preferably, in the semiconductor multilayer substrate having the above characteristics, the fourth semiconductor layer is formed of a plurality of layers in which at least one of an impurity concentration and an impurity element is different from each other.

  As described above, by configuring the fourth semiconductor layer with a plurality of layers, as will be described later, it is possible to improve the vertical breakdown voltage, prevent the crystallinity of the semiconductor layer above the fourth semiconductor layer from deteriorating, and the like. it can.

  Here, when the fourth semiconductor layer is formed of a plurality of layers having different impurity concentrations, it is preferable that the higher the impurity concentration, the closer to the first semiconductor layer. In the case where the fourth semiconductor layer is composed of a plurality of layers having different impurity elements, it is preferable that an impurity having an atomic radius closer to that of a substituted atom is arranged closer to the first semiconductor layer.

  More preferably, in the semiconductor multilayer substrate having the above characteristics, the first two-dimensional carrier gas layer is a two-dimensional electron gas layer, the second two-dimensional carrier gas layer is a two-dimensional hole gas layer, An impurity present on the fourth semiconductor layer side of the interface between the first semiconductor layer and the fourth semiconductor layer is an n-type impurity.

  More preferably, in the semiconductor multilayer substrate having the above characteristics, the fourth semiconductor layer has one or more elements selected from Si, Ge, Sn, S, Te, O, and Se as the n-type impurity. Including.

  Furthermore, the semiconductor multilayer substrate having the above-described characteristics is a two-dimensional hole gas layer in which electrons, which are majority carriers existing in the fourth semiconductor layer, are generated at the junction interface between the fourth semiconductor layer and the first semiconductor layer. The hole density of the two-dimensional hole gas layer is reduced by recombination with holes.

  The present invention further provides a semiconductor multilayer substrate having any one of the above characteristics, a source electrode and a drain electrode formed on an upper surface of the third semiconductor layer of the semiconductor multilayer substrate, and between the source electrode and the drain electrode. And a gate electrode formed on or above the third semiconductor layer. A semiconductor switching element is provided.

  As described above, by using the semiconductor laminated substrate having the above characteristics, it is possible to provide a semiconductor switching element in which lateral leakage is suppressed.

1 is a structural cross-sectional view showing a configuration of a semiconductor multilayer substrate according to a first embodiment of the present invention. Structural sectional drawing which shows the structure of the semiconductor laminated substrate which concerns on 2nd Embodiment of this invention. Structural sectional drawing which shows the structure of the semiconductor laminated substrate which concerns on 3rd Embodiment of this invention. Structural sectional drawing which shows the structure of the semiconductor laminated substrate which concerns on 4th Embodiment of this invention. Structural sectional view showing a first configuration example of a switching element using a semiconductor multilayer substrate according to the present invention Structural sectional view showing a second configuration example of a switching element using a semiconductor multilayer substrate according to the present invention Structural sectional view showing a third configuration example of a switching element using a semiconductor multilayer substrate according to the present invention Structural sectional view showing a fourth configuration example of a switching element using a semiconductor multilayer substrate according to the present invention Structural sectional view showing an example of the configuration of a switching element using a conventional semiconductor multilayer substrate Structural sectional view showing another configuration example of a switching element using a conventional semiconductor multilayer substrate Structural sectional view showing problems of switching elements using the conventional semiconductor multilayer substrate shown in FIG. Cross-sectional view of structure showing problems of switching element using conventional semiconductor multilayer substrate shown in FIG.

  Hereinafter, embodiments of a semiconductor multilayer substrate according to the present invention (hereinafter, appropriately referred to as “the present multilayer substrate”) will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals in the drawings to facilitate the understanding of the description. Further, in the structural cross-sectional views of the respective drawings, the main parts are appropriately emphasized, and the dimensional ratios of the respective constituent elements on the drawings do not necessarily coincide with the actual dimensional ratios.

<First Embodiment>
A structural example of the multilayer substrate 1 according to the first embodiment is shown in the structural cross-sectional view of FIG. As shown in FIG. 1, the multilayer substrate 1 includes a substrate 11, a buffer layer 12 formed on the upper surface of the substrate 11, an electron transit layer 13 formed above the buffer layer 12, and an upper surface of the electron transit layer 13. And an n-type layer 15 formed on the upper surface of the buffer layer 12 and below the electron transit layer 13. The buffer layer 12, the electron transit layer 13, the electron supply layer 14, and the n-type layer 15 correspond to the first, second, third, and fourth semiconductor layers, respectively, and are all well-known gas phases. It is a group III nitride semiconductor formed by an epitaxial growth method (for example, MOCVD (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), etc.).

The substrate 11 is made of, for example, silicon (Si), silicon carbide (SiC), sapphire (Al ₂ O ₃ ), gallium nitride (GaN), aluminum nitride (AlN), zinc oxide (ZnO), gallium arsenide (GaAs), or the like. Selected. The buffer layer 12 is made of, for example, Al _W Ga _1-W N (where 0 ≦ W ≦ 1). The buffer layer 12 includes AlN (when W = 1) and GaN (when W = 0). The substrate 11 may use the same nitride semiconductor as the buffer layer 12. Further, the substrate 11 and the buffer layer 12 are not limited to those exemplified above as long as warpage and cracks of the laminated substrate 1 are suppressed, and any substrate may be selected.

The electron transit layer 13 is made of, for example, non-doped In _X Ga _1-X N (where 0 ≦ X ≦ 1) having a thickness of 1 μm to 5 μm. The electron transit layer 13 is InN when X = 1 and GaN when X = 0. Since the electron transit layer 13 is required to have good crystallinity, the carbon concentration is desirably 1 × 10 ¹⁸ cm ⁻³ or less, and more desirably 1 × 10 ¹⁶ cm ⁻³ or less. Although the In composition ratio X can be in the range of 0 to 1, the band gap of the electron transit layer 13 is smaller than the band gap of the buffer layer 12, so that the buffer layer 12 is GaN (W = 0). In, the In composition ratio X is set larger than 0.

Electron supply layer 14 is, for example, a non-doped a thickness of 10nm or more 100nm or less _Al Z _{Ga 1-Z} N (where, 0 <Z ≦ 1) consists. 0.1 ≦ Z ≦ 0.3 is more preferable. The electron supply layer _{14, In Y Al Z Ga 1-} Y-Z N ( where, 0 ≦ Y ≦ 1,0 <Z ≦ 1) of may be quaternary nitride semiconductor. However, the band gap of the electron supply layer 14 is larger than the band gap of the electron transit layer 13, and the electron transit layer 13 and the electron supply layer 14 are heterojunction. A two-dimensional electron gas layer 16 (corresponding to a first two-dimensional carrier gas layer) is generated near the electron transit layer 13 side of the heterojunction interface. The electron supply layer 14 may be doped n-type, and the impurity concentration in this case is preferably about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

n-type layer 15, for example, the thickness is less 100nm or more _{1nm In X Ga 1-X N} ( where, 0 ≦ X ≦ 1) consists. In the present embodiment, the In composition ratio X of the n-type layer 15 is the same as the In composition ratio X of the electron transit layer 13, and the band gaps of both layers 13 and 15 are the same. It should be noted that the In composition ratio X of the two layers 13 and 15 does not necessarily have to be the same, but the difference is that the two-dimensional hole gas layer (second layer) is located near the interface between the n-type layer 15 and the electron transit layer 13. (E.g., a band gap difference of 0.2 eV or less). Further, the concentration of carbon that can be a hole generation source in the n-type layer 15 is desirably 1 × 10 ¹⁸ cm ⁻³ or less, and more desirably 1 × 10 ¹⁶ cm ⁻³ or less.

In the present embodiment, the n-type layer 15 contains one or more n-type impurities of Si, Ge, Sn, S, Te, O, Se, etc., and has n-type conductivity. Assume the case. Even if oxygen which is one of the n-type impurities is not intentionally doped, for example, oxygen released from quartz or the like as an apparatus member, or the chamber is opened to the atmosphere by loading / unloading wafers or replacing members. For example, the oxygen that has entered when left is left and taken into the film, so that it can be contained in the n-type layer 15 in a concentration range of about 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁸ cm ^−3. The n-type layer 15 can exhibit n-type conductivity without intentionally doping the n-type impurity. For the above reason, the oxygen concentration in the n-type layer 15 when not intentionally doped tends to be higher when the film is formed by MOCVD than MBE having a high degree of vacuum.

  Therefore, when the above-described n-type impurity is not intentionally doped into the n-type layer 15, the concentration of oxygen present in the n-type layer 15 depends on the n level of the heterojunction interface between the buffer layer 12 and the n-type layer 15. The two-dimensional hole gas layer that can be generated on the mold layer 15 side is comparable to the hole density (in terms of volume density) before recombining with electrons that are majority carriers in the n-type layer 15 and decreasing. When electrons that are majority carriers having a density of (for example, about 0.1 to 1 times) can be supplied, the n-type layer 15 is a non-doped layer that is not intentionally doped with the n-type impurity. May be.

  However, when the hole density before conversion of the two-dimensional hole gas layer (in terms of volume density) is higher than the oxygen concentration, the n-type at the heterojunction interface between the buffer layer 12 and the n-type layer 15 Since a two-dimensional hole gas layer is generated with a high hole density on the layer 15 side, n-type impurities are intentionally doped in the n-type layer 15 to reduce the hole density of the two-dimensional hole gas layer. It actively decreases and suppresses the generation of the two-dimensional hole gas layer.

As an example, when the electron density (surface density) of the two-dimensional electron gas layer 16 generated at the heterojunction interface between the electron transit layer 13 and the electron supply layer 14 is particularly high, such as about 1 × 10 ¹³ cm ⁻² , the buffer When the hole density (surface density) of the two-dimensional hole gas layer generated at the heterojunction interface between the layer 12 and the n-type layer 15 also greatly exceeds 1 × 10 ¹² cm ⁻² , it is converted into a volume density. Thus, the oxygen concentration in the non-doped n-type layer 15 (approximately 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ ) is greatly exceeded. Since holes in the hole gas layer cannot be canceled out, n-type impurities are intentionally doped in the n-type layer 15. Further, even when the hole density (surface density) of the two-dimensional hole gas layer does not greatly exceed 1 × 10 ¹² cm ⁻² , the oxygen concentration in the non-doped n-type layer 15 is lower than that. In this case, the n-type layer 15 is intentionally doped with n-type impurities.

  Here, when the n-type impurity is intentionally doped in the n-type layer 15, if it is excessively doped, a large number of electrons remain even after canceling out the holes in the two-dimensional hole gas layer, Since the remaining electrons can be a lateral leakage source in place of the two-dimensional hole gas layer, the thickness of the doped layer intentionally doped with n-type impurities is limited to 5 nm or less, preferably 3 nm or less. Is preferred. That is, it is preferable to intentionally dope the n-type impurity in a region where the two-dimensional hole gas layer may be generated. Thereby, it can suppress that the electron which remains after cancelling with the hole of the said two-dimensional hole gas layer becomes a new lateral leak source.

Further, instead of or in addition to limiting the thickness of the doped layer, the high concentration region of the n-type impurity is difficult to grow in the lateral direction (in the case of MOCVD, as an example of the normal growth condition, Using the low temperature, the low pressure, the high organometallic gas flow rate, the low ammonia flow rate, the high impurity gas flow rate such as SiH ₄ or GeCl _4, etc., the lateral direction (parallel to the upper surface of the substrate 11) on the upper surface of the buffer layer 12. In which the current flows between the drain electrode and the source electrode of the semiconductor switching element using the multilayer substrate 1), and is formed on the upper side of the non-doped or n-type low concentration It is also preferable to form the n-type layer 15 by forming a doped layer on the entire surface. Thereby, it can suppress that the electron which remains after cancelling with the hole of the said two-dimensional hole gas layer becomes a new lateral leak source.

  As a result of the above, the n-type impurity is adjusted so that the impurity concentration corresponds to the hole density of the two-dimensional hole gas layer that can be generated on the n-type layer 15 side of the heterojunction interface between the buffer layer 12 and the n-type layer 15. By forming the n-type layer 15 having, electrons in the n-type layer 15 cancel out with the holes in the two-dimensional hole gas layer, and the hole density in the two-dimensional hole gas layer is reduced. Since the conductivity is greatly lowered, the lateral leakage of the laminated substrate 1 can be greatly reduced.

Second Embodiment
A structural example of the laminated substrate 2 according to the second embodiment is shown in the structural cross-sectional view of FIG. As shown in FIG. 2, the laminated substrate 2 includes a substrate 11, a buffer layer 12 formed on the upper surface of the substrate 11, an electron transit layer 13 formed above the buffer layer 12, and an upper surface of the electron transit layer 13. Formed on the upper surface of the electron supply layer 14 and the buffer layer 12 and on the upper surface of the n-type layer 15 and the n-type layer 15 formed below the electron transit layer 13 and below the electron transit layer 13. The formed withstand voltage layer 17 is provided. The buffer layer 12, the electron transit layer 13, the electron supply layer 14, the n-type layer 15, and the breakdown voltage layer 17 correspond to the first, second, third, fourth, and fifth semiconductor layers, respectively. Both are group III nitride semiconductors formed by a known vapor phase epitaxial growth method (for example, MOCVD (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), etc.).

  The difference between the present multilayer substrate 2 and the present multilayer substrate 1 of the first embodiment is that the present multilayer substrate 2 includes a pressure-resistant layer 17 between the n-type layer 15 and the electron transit layer 13. The buffer layer 12, the electron transit layer 13, the electron supply layer 14, and the n-type layer 15 are the same as those of the multilayer substrate 1 of the first embodiment, and a duplicate description is omitted.

The breakdown voltage layer 17 is made of, for example, non-doped In _X Ga _1-X N (where 0 ≦ X ≦ 1) having a carbon concentration of 10 nm to 5 μm and a carbon concentration of 1 × 10 ¹⁸ cm ⁻³ or more. The breakdown voltage layer 17 is InN when X = 1 and GaN when X = 0. In the present embodiment, the In composition ratio X of the breakdown voltage layer 17 is the same as the In composition ratio X of the electron transit layer 13 and the n-type layer 15, and the band gaps of the layers 13, 15, and 17 are the same. The In composition ratios X of the layers 13, 15, and 17 do not necessarily have to be the same, but the difference is in the vicinity of the interface between the breakdown voltage layer 17 and the electron transit layer 13 and between the n-type layer 15 and the breakdown voltage layer 17. It is sufficient that the two-dimensional hole gas layer (corresponding to the second two-dimensional carrier gas layer) is not generated in the vicinity of the interface (substantially 0) (for example, a band gap difference of 0.2 eV). Less than).

In the present embodiment, since the breakdown voltage layer 17 having a carbon concentration of 1 × 10 ¹⁸ cm ⁻³ or more exists on the upper surface of the n-type layer 15, the breakdown voltage improvement effect in the vertical direction of the multilayer substrate 2 is expected. However, since the carbon atoms in the pressure-resistant layer 17 have an atomic radius close to that of the nitrogen atoms, carbon atoms often enter so as to fill the nitrogen defects in the pressure-resistant layer 17, and in that case, the buffer layer 12 and the n-type layer Holes can be supplied to the two-dimensional hole gas layer that can be generated on the n-type layer 15 side of the heterojunction interface between 15. Therefore, there is a possibility that the hole density of the two-dimensional hole gas layer is higher than that of the present laminated substrate 1 of the first embodiment that does not include the breakdown voltage layer 17.

As described above in the first embodiment, the n-type layer 15 does not intentionally dope the n-type impurity, but oxygen as one of the n-type impurities is 1 × 10 ¹⁴ cm ⁻³ to 1 × 1. It may be contained in a concentration range of about × 10 ¹⁸ cm ⁻³ and may exhibit n-type conductivity. Therefore, even when holes are supplied from the pressure-resistant layer 17 to the two-dimensional hole gas layer, the two-dimensional hole gas layer before the recombination with the electrons in the n-type layer 15 is lowered. In the case where the n-type layer 15 can supply electrons having the same concentration (for example, about 0.1 to 1 times) with respect to the hole density (in terms of volume density), the n-type layer 15 is intended. Alternatively, it may be a non-doped layer not doped with n-type impurities.

However, in addition to the case where the electron density (surface density) of the two-dimensional electron gas layer 16 generated at the heterojunction interface between the electron transit layer 13 and the electron supply layer 14 is particularly high as about 1 × 10 ¹³ cm ⁻² , The hole density (surface density) of the two-dimensional hole gas layer generated at the heterojunction interface between the buffer layer 12 and the n-type layer 15 even when the carbon concentration of the layer 17 is particularly high of about 1 × 10 ¹⁹ cm ^−3. ) ^May greatly exceed 1 × 10 ¹² cm ⁻² . In such a case, the oxygen concentration in the non-doped n-type layer 15 (about 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ ) greatly exceeds the n-type layer 15 in terms of volume density. Since the electrons inside cannot completely cancel out the holes in the two-dimensional hole gas layer, the n-type impurity is intentionally doped into the n-type layer 15. Further, even when the hole density (surface density) of the two-dimensional hole gas layer does not greatly exceed 1 × 10 ¹² cm ⁻² , the oxygen concentration in the non-doped n-type layer 15 is lower than that. In this case, the n-type layer 15 is intentionally doped with n-type impurities.

  Since suitable manufacturing conditions and the like for the n-type layer 15 intentionally doped with n-type impurities are the same as those described above in the first embodiment, they are omitted.

  As a result of the above, the n-type impurity is adjusted so that the impurity concentration corresponds to the hole density of the two-dimensional hole gas layer that can be generated on the n-type layer 15 side of the heterojunction interface between the buffer layer 12 and the n-type layer 15. By forming the n-type layer 15 having n, the electrons in the n-type layer 15 are converted into the two-dimensional hole gas layer even when the pressure-resistant layer 17 having a high carbon concentration is provided on the upper surface of the n-type layer 15. Since the hole density of the two-dimensional hole gas layer is reduced and the electrical conductivity is greatly reduced, the lateral leakage of the laminated substrate 2 can be greatly reduced.

<Third Embodiment>
A structural example of the laminated substrate 3 according to the third embodiment is shown in the structural cross-sectional view of FIG. As shown in FIG. 3, the multilayer substrate 3 includes a substrate 11, a buffer layer 12 formed on the upper surface of the substrate 11, an electron transit layer 13 formed above the buffer layer 12, and an upper surface of the electron transit layer 13. And an n-type layer 15 formed on the upper surface of the buffer layer 12 and below the electron transit layer 13. The buffer layer 12, the electron transit layer 13, the electron supply layer 14, and the n-type layer 15 correspond to the first, second, third, and fourth semiconductor layers, respectively, and are all well-known gas phases. It is a group III nitride semiconductor formed by an epitaxial growth method (for example, MOCVD (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), etc.).

  The difference between the present laminated substrate 3 and the present laminated substrate 1 of the first embodiment is that, in the present laminated substrate 3, the n-type layer 15 is not a single layer, and n or more n layers having different impurity concentrations of n-type impurities. It is a point comprised by type | mold layers 15a and 15b, About the board | substrate 11, the buffer layer 12, the electron transit layer 13, and the electron supply layer 14, it is the same as this laminated substrate 1 of 1st Embodiment, and overlaps I will omit the explanation.

  In the cross-sectional structure of FIG. 3, the n-type layer 15 is exemplified by the two n-type layers 15a and 15b. However, the number of layers constituting the n-type layer 15 is three or more. May be.

  Further, in the cross-sectional structure illustrated in FIG. 3, the electron transit layer 13 is disposed on the upper surface of the n-type layer 15, but the n-type layer 15 and the electron transit layer 13 are similar to those in the second embodiment. A pressure-resistant layer 17 may be provided therebetween. In addition, the pressure | voltage resistant layer 17 is the same as this laminated substrate 2 of 2nd Embodiment, The overlapping description is abbreviate | omitted.

  In the laminated substrates 1 and 2 of the first and second embodiments described above, when the n-type layer 15 formed as a single layer is a high-concentration doped layer doped with an n-type impurity at a high concentration, n The internal electric field in the mold layer 15 becomes high, and the breakdown voltage in the vertical direction is reduced as compared with the case of the non-doped layer and the case where the n-type impurity has a low concentration.

  Therefore, in the present embodiment, the n-type layer 15 is divided into two or more n-type layers 15a and 15b so that the impurity concentration of the n-type impurity is higher on the lower layer side and decreases toward the upper layer. . By adopting such a multilayer structure, the low-concentration layer is included in the multilayer structure, whereby the vertical breakdown voltage is improved. Here, the lower the lower layer side, the higher the impurity concentration is because the two-dimensional hole gas layer is generated in the vicinity of the interface with the lower buffer layer 12, so that the electrons canceling out the holes in the two-dimensional hole gas layer. This is because a layer with a high impurity concentration and a high impurity concentration is disposed near the location where the two-dimensional hole gas layer is generated.

The uppermost layer of the n-type layer 15 having a multilayer structure is not intentionally doped with an n-type impurity, but an n-type in which oxygen is contained in a concentration range of about 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁸ cm ^−3. It may be a non-doped layer. In this case, the improvement of the breakdown voltage is particularly expected.

  The thickness and impurity concentration of each layer of the n-type layer 15 having a multilayer structure may be determined according to the hole density of the two-dimensional hole gas layer before canceling out the electrons in the n-type layer 15. As an example, when the n-type layer 15 is composed of two layers, n-type layers 15a and 15b, the upper n-type layer 15b is a non-doped layer, the lower n-type layer 15a is a doped layer, and impurities in the n-type layer 15a The concentration is set according to the hole density of the two-dimensional hole gas layer so that holes that cannot be canceled out by electrons supplied from the upper n-type layer 15b can be canceled. In this case, it is preferable that the thickness of the lower n-type layer 15a is, for example, 1 nm or more and 5 nm or less, more preferably 3 nm or less, and the total thickness of the n-type layer 15 is, for example, 100 nm or less.

  As a result of the above, the n-type impurity is adjusted so that the impurity concentration corresponds to the hole density of the two-dimensional hole gas layer that can be generated on the n-type layer 15 side of the heterojunction interface between the buffer layer 12 and the n-type layer 15. When the n-type layer 15 is formed by intentionally doping the n-type layer 15, the n-type layer 15 has a multi-layer structure even when the n-type impurity has a high concentration and there is a concern about a decrease in the breakdown voltage in the vertical direction. By setting the impurity concentration higher on the lower layer side, the electrons in the n-type layer 15 cancel out the holes in the two-dimensional hole gas layer while suppressing the decrease in the breakdown voltage, and the two-dimensional hole gas layer. The hole density is reduced and the electrical conductivity is greatly reduced, so that the lateral leakage of the laminated substrate 3 can be greatly reduced.

<Fourth embodiment>
A structural example of the multilayer substrate 4 according to the fourth embodiment is shown in the structural cross-sectional view of FIG. As shown in FIG. 4, the laminated substrate 4 includes a substrate 11, a buffer layer 12 formed on the upper surface of the substrate 11, an electron transit layer 13 formed above the buffer layer 12, and an upper surface of the electron transit layer 13. And an n-type layer 15 formed on the upper surface of the buffer layer 12 and below the electron transit layer 13. The buffer layer 12, the electron transit layer 13, the electron supply layer 14, and the n-type layer 15 correspond to the first, second, third, and fourth semiconductor layers, respectively, and are all well-known gas phases. It is a group III nitride semiconductor formed by an epitaxial growth method (for example, MOCVD (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), etc.).

  The difference between the present laminated substrate 4 and the present laminated substrate 1 of the first embodiment is that, in the present laminated substrate 4, the n-type layer 15 is not a single layer, and n or more n layers having different n-type impurity elements from each other. The substrate 11, the buffer layer 12, the electron transit layer 13, and the electron supply layer 14 are the same as those of the laminated substrate 1 of the first embodiment, and are overlapped. I will omit the explanation.

  In the cross-sectional structure of FIG. 4, the n-type layer 15 is exemplified by the two n-type layers 15c and 15d, but the number of layers constituting the n-type layer 15 is three or more. May be.

  Furthermore, in the cross-sectional structure illustrated in FIG. 4, the electron transit layer 13 is disposed on the upper surface of the n-type layer 15, but the n-type layer 15 and the electron transit layer 13 are similar to those in the second embodiment. A pressure-resistant layer 17 may be provided therebetween. In addition, the pressure | voltage resistant layer 17 is the same as this laminated substrate 2 of 2nd Embodiment, The overlapping description is abbreviate | omitted.

In the laminated substrates 1 and 2 of the first and second embodiments described above, the n-type layer 15 formed as a single layer (in the case of In composition ratio X ≠ 1, as an example of GaN) is an n-type impurity. In the case of a doped layer intentionally doped with Si as Si, since Si has a difference in atomic radius from Ga of group III atoms to be substituted, a high concentration of 1 × 10 ¹⁹ cm ⁻³ or more Doping causes surface roughness due to the three-dimensional growth of the film, and deteriorates the crystallinity of the electron transit layer 13 or the breakdown voltage layer 17 disposed on the upper side. Therefore, the n-type layer 15 has a high impurity concentration according to the hole density of the two-dimensional hole gas layer that can be generated on the n-type layer 15 side of the heterojunction interface between the buffer layer 12 and the n-type layer 15. It becomes difficult. In addition, the wafer tends to warp during film growth due to tensile stress in the n-type layer 15 due to lattice mismatch.

On the other hand, Ge has an atomic radius close to that of Ga of the group III atom to be substituted, and thus does not have the above-described adverse effects when Si is used as an n-type impurity, and has a high concentration of 3 × 10 ²⁰ cm ⁻³ or more. It is possible to set the impurity concentration in a wide range according to the hole density of the two-dimensional hole gas layer.

  Therefore, in this embodiment, the n-type layer 15 is divided into two or more n-type layers 15c and 15d, Ge is used as the n-type impurity of the lower n-type layer 15c, and the upper n-type layer is used. Si is used as the 15d n-type impurity. In this case, since the two-dimensional hole gas layer is generated on the n-type layer 15c side of the heterojunction interface between the buffer layer 12 and the lower n-type layer 15c, the impurity concentration of the lower n-type layer 15c is reduced. It is possible to set a wide range according to the hole density of the two-dimensional hole gas layer. Even electrons in the n-type layer 15d on the upper layer side can cancel holes in the two-dimensional hole gas layer, and when compressive stress is generated in the semiconductor layer on the upper side of the n-type layer 15, It is possible to suppress the tensile stress generated in the upper n-type layer 15d and the compressive stress generated in the upper semiconductor layer from canceling out, and the wafer from being warped and cracked during film growth. Specifically, when the breakdown voltage layer 17 is provided on the upper surface of the n-type layer 15, the breakdown voltage layer 17 corresponds to the semiconductor layer that generates compressive stress.

  As a result of the above, the n-type impurity is adjusted so that the impurity concentration corresponds to the hole density of the two-dimensional hole gas layer that can be generated on the n-type layer 15 side of the heterojunction interface between the buffer layer 12 and the n-type layer 15. When the n-type layer 15 is formed by intentionally doping the n-type layer 15, the n-type layer 15 has a multi-layer structure, and impurities in the lower n-type layer 15 c in contact with the buffer layer 12 By using a close impurity (for example, Ge when the atom to be substituted is Group III Ga), the impurity concentration in the vicinity of the region where the two-dimensional hole gas layer is generated is increased according to the hole density. Even in the case of concentration, it is possible to avoid causing surface roughness due to three-dimensional growth and deteriorating the crystallinity of the electron transit layer 13 or the breakdown voltage layer 17 disposed on the upper side. Further, when compressive stress is generated in the semiconductor layer formed on the upper surface of the n-type layer 15d, the two types of stress are canceled out as a doped layer doped with an impurity that generates tensile stress in the upper n-type layer 15d. By matching, warpage and cracking of the wafer due to the stress can be avoided. Furthermore, as described above in the third embodiment, the impurity concentration can be set higher as the lower layer side, and the lateral leakage of the multilayer substrate 4 is greatly reduced while suppressing the decrease in the vertical breakdown voltage. it can.

<Fifth Embodiment>
Next, a configuration example of a semiconductor switching element (hereinafter, referred to as “the switching element” as appropriate) configured using the multilayer substrates 1 to 4 described in the first to fourth embodiments will be described with reference to FIGS. This is shown in the sectional view of FIG. 5 to 8 show, as an example, the case where the main substrate 1 of the first embodiment is used. The main substrates used are the main substrates 2 to 4 described in the second to fourth embodiments. It may be modified based on the present laminated substrates 1 to 4.

  The switching element 5 shown in FIG. 5 includes the laminated substrate 1 shown in FIG. 1, the source electrode 18 and the drain electrode 19 formed on the upper surface of the electron supply layer 14 of the laminated substrate 1, the source electrode 18 and the drain. A gate electrode 21 formed via a gate insulating film 20 is provided above the electron supply layer 14 between the electrodes 19.

  The switching element 6 shown in FIG. 6 includes the laminated substrate 1 shown in FIG. 1, the source electrode 18 and the drain electrode 19 formed on the upper surface of the electron supply layer 14 of the laminated substrate 1, the source electrode 18 and the drain. A gate electrode 22 formed on the upper surface of the electron supply layer 14 between the electrodes 19 and having a Schottky junction with the electron supply layer 14 is provided.

  The switching element 7 shown in FIG. 7 includes the laminated substrate 1 shown in FIG. 1, the source electrode 18 and the drain electrode 19 formed on the upper surface of the electron supply layer 14 of the laminated substrate 1, the source electrode 18 and the drain. A gate electrode 24 formed via a p-type layer 23 is provided above the electron supply layer 14 between the electrodes 19.

  The switching element 8 shown in FIG. 8 includes the laminated substrate 1 shown in FIG. 1, the source electrode 18 and the drain electrode 19 formed on the upper surface of the electron supply layer 14 of the laminated substrate 1, the source electrode 18 and the drain. A gate electrode 25 that is formed on the portion of the electron supply layer 14 between the electrodes 19 that has been thinned by etching and that has a Schottky junction with the electron supply layer 14 is provided.

  The source electrode 18 and the drain electrode 19 of the switching elements 5 to 8 are formed of a well-known single layer or multilayer structure metal material that is in ohmic contact with the electron supply layer 14. As the metal material of the electrodes 18 and 19, for example, Ti, Ni, Al, Cu, Au, Pt, W, Ta, Ru, Ir, Pd, Hf, etc. can be used, and any one or more of these can be used. Including alloys or nitrides can also be used. Furthermore, in the case of a multilayer structure, Ti / Al / TiN, Ti / Au, Ti / Al / Ni / Au, etc. can be used.

The gate electrode 21 of the switching element 5 is formed of a well-known single layer or multilayer metal material. The gate insulating film 20 is made of a known insulating material (for example, SiO _X , AlO _X , HfO _X , LaO _X , ZrO _X , YO _X , SiN, AlN, etc.). The gate electrode 22 of the switching element 6 is formed of a well-known single layer or multi-layer metal material that forms a Schottky junction with the electron supply layer 14. The gate electrode 24 of the switching element 7 is formed of a well-known single layer or multilayer metal material. The p-type layer 23 is made of a group III nitride semiconductor (eg, AlGaN having the same Al composition ratio as the electron supply layer 14) doped with a p-type impurity (eg, Mg). The gate electrode 25 of the switching element 8 is formed of a well-known single-layer or multi-layer metal material that forms a Schottky junction with the electron supply layer 14. As the metal material of each gate electrode 21, 22, 24, 25, for example, Ti, Ni, Al, Cu, Au, Pt, W, Ta, Ru, Ir, Pd, Hf, etc. can be used. An alloy or nitride containing any one or more can also be used. Furthermore, in the case of a multilayer structure, W / TiN, W / WN, Ni / Au, Pd / Au, etc. can be used. Since the gate electrode 21 is formed on the gate insulating film 20, it is not necessary to make a Schottky junction with the electron supply layer 14, and there are few restrictions on material selection. The gate electrode 24 often contains Ni.

  As shown in FIGS. 7 and 8, the switching elements 7 and 8 are configured so that the gate electrodes 24 and 25 have the same potential as that of the source electrode 18 or when the gate electrodes 24 and 25 are in a floating state. This is a normally-off type device in which the channel below the interface between the electron transit layer 13 and the electron supply layer 14 immediately below 24 and 25 is depleted and the two-dimensional electron gas layer 16 disappears. On the other hand, the switching elements 5 and 6 shown in FIGS. 5 and 6 are normally-on type elements as in the conventional switching element shown in FIG.

  Note that each element structure (especially a structure around each electrode) of the switching elements 5 to 8 illustrated in FIGS. 5 to 8 is an example, and the laminated substrates 1 to 4 are semiconductor switching elements other than the element structures described above. It can also be applied to.

<Another embodiment>
Hereinafter, another embodiment of the circuit of the present invention will be described.

  In each of the above embodiments, an example of a preferred embodiment of the present laminated substrate and the present switching element using the present laminated substrate has been described in detail. The configurations of the multilayer substrate and the switching element are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  <1> In the first to fourth embodiments, it is assumed that the first two-dimensional carrier gas layer generated at the heterojunction interface between the electron transit layer 13 and the electron supply layer 14 is the two-dimensional electron gas layer 16. However, the present invention is not limited to the case where the first two-dimensional carrier gas layer is the two-dimensional electron gas layer 16, and the first two-dimensional carrier gas layer is a two-dimensional hole gas having a conductivity type opposite to that of the first two-dimensional carrier gas layer. Even in the case of a layer, the present invention can be applied by replacing the conductivity type of the n-type layer 15 of the laminated substrates 1 to 4 from a p-type to a p-type layer. However, in the case of a p-type layer, it is necessary to intentionally dope a p-type impurity. In the nitride semiconductor, since the mobility of electrons is larger than that of holes, it is preferable that the carriers constituting the first two-dimensional carrier gas layer are electrons (two-dimensional electron gas layer).

<2> In the second embodiment, it is assumed that the breakdown voltage layer 17 is formed on the upper surface of the n-type layer 15 and below the electron transit layer 13, but the breakdown voltage layer 17 and the n-type layer 15 are respectively formed. Further, it may be formed so as to overlap the same region in the thickness direction of the laminated substrate 2 on the upper surface of the buffer layer 12 and below the electron transit layer 13. That is, it is equivalent to the case where the n-type layer 15 of the multilayer substrate 1 of the first embodiment includes a region having a carbon concentration of 1 × 10 ¹⁸ cm ⁻³ or more. Also in this case, as in the case of the laminated substrates 1 and 2 of the first and second embodiments, even if the breakdown voltage layer 17 having a high carbon concentration is provided, electrons in the n-type layer 15 This cancels out the holes in the hole gas layer, the hole density of the two-dimensional hole gas layer decreases, and the electrical conductivity is greatly reduced. Therefore, the lateral leakage of the laminated substrate 1 can be greatly reduced.

  <3> In the third embodiment, the impurity concentration of the n-type impurity in the n-type layer 15 of the multilayer substrate 3 is higher on the lower layer side, and is divided into a plurality of layers and gradually decreases toward the upper layer. In some cases, the impurity concentration may be an impurity concentration distribution that continuously decreases from the lower layer side toward the upper layer in the entire n-type layer 15 or a part of the divided layers.

  <4> In the fourth embodiment, in the example illustrated in FIG. 4, the n-type layer 15 of the laminated substrate 4 is divided into two layers, n-type layers 15 c and 15 d, and the n-type layer 15 c on the lower layer side is separated. Ge is used as the n-type impurity, Si is used as the n-type impurity of the upper n-type layer 15d, and the impurity concentration of the lower n-type layer 15c is set higher than that of the upper n-type layer 15d. However, the impurity concentration of the two or more n-type layers 15c and 15d having different n-type impurity elements is not necessarily higher in the lower layer side as in the third embodiment, and is directed toward the upper layer. Therefore, the concentration distribution of each n-type layer may be the same.

<5> Furthermore, in the fourth embodiment, each of the two or more n-type layers 15c and 15d having different n-type impurity elements is intentionally doped with n-type impurities in each layer. However, the uppermost layer of the two or more n-type layers is not intentionally doped with n-type impurities, but oxygen is about 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁸ cm ^−3. An n-type non-doped layer included in a concentration range of may be used.

  The semiconductor multilayer substrate according to the present invention can be used for a semiconductor switching element, and can be suitably used particularly for a semiconductor switching element applied to a power device.

1-4: Semiconductor laminated substrate 5-8: Semiconductor switching element 11, 101: Substrate 12, 102: Buffer layer (first semiconductor layer)
13, 103: Electron traveling layer (second semiconductor layer)
14, 104: Electron supply layer (third semiconductor layer)
15: n-type layer (fourth semiconductor layer)
15a, 15b: n-type layers having different impurity concentrations 15c, 15d: n-type layers having different impurity elements 16, 110: two-dimensional electron gas layer (first two-dimensional carrier gas layer)
17, 111: Withstand voltage layer 18, 106: Source electrode 19, 107: Drain electrode 20, 109: Gate insulating film 21, 22, 24, 25, 108: Gate electrode 23: P-type layer 100: Conventional semiconductor switching element 105 : Conventional semiconductor multilayer substrate 112: Two-dimensional hole gas layer (second two-dimensional carrier gas layer)
113: Depletion layer

Claims (5)

Comprising first, second, third and fourth semiconductor layers of nitride semiconductor;
The second semiconductor layer is disposed above the first semiconductor layer;
The third semiconductor layer is disposed on an upper surface of the second semiconductor layer;
The fourth semiconductor layer is disposed on an upper surface of the first semiconductor layer and below the second semiconductor layer;
Band gaps of the second semiconductor layer and the fourth semiconductor layer are smaller than the first semiconductor layer, respectively.
A band gap of the third semiconductor layer is larger than that of the second semiconductor layer;
The second semiconductor layer and the third semiconductor layer are heterojunctioned, and a first two-dimensional carrier gas layer can be generated on the second semiconductor layer side of the interface between the second and third semiconductor layers,
There is no band gap difference between the other semiconductor layer at the lower surface side interface of the second semiconductor layer and the upper surface side interface of the fourth semiconductor layer, or the first two-dimensional carrier gas. The layer is so small that a second two-dimensional carrier gas layer of a reverse conductivity type cannot be generated,
The first semiconductor layer and the fourth semiconductor layer are heterojunction,
A semiconductor multilayer substrate, wherein the fourth semiconductor layer contains impurities of the same conductivity type as carriers forming the first two-dimensional carrier gas layer.   The semiconductor multilayer substrate according to claim 1, wherein the impurity includes an impurity added in a process of forming the fourth semiconductor layer.   A fifth semiconductor of a nitride semiconductor formed on the upper surface of the fourth semiconductor layer and below the second semiconductor layer, having a band gap smaller than that of the first semiconductor layer and having a carbon concentration higher than that of the second semiconductor layer. The layered semiconductor substrate according to claim 1, further comprising a layer.   4. The semiconductor multilayer substrate according to claim 1, wherein the fourth semiconductor layer includes a plurality of layers in which at least one of an impurity concentration and an impurity element is different from each other. 5. .   The first two-dimensional carrier gas layer is a two-dimensional electron gas layer, the second two-dimensional carrier gas layer is a two-dimensional hole gas layer, and an interface between the first semiconductor layer and the fourth semiconductor layer The semiconductor multilayer substrate according to claim 1, wherein the impurity present on the fourth semiconductor layer side is an n-type impurity.

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